Commit 84260e668bed6fcb18de7cc39fc94f7687e414c9
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e947c772f3
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u-boot lcd enable
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4 changed files
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25 additions
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32 deletions
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bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/mx6s_prime_oven.c
... | ... | @@ -387,18 +387,10 @@ static iomux_v3_cfg_t const backlight_pads[] = { |
387 | 387 | // Dual LVDS |
388 | 388 | static void enable_lvds(struct display_info_t const *dev) |
389 | 389 | { |
390 | - struct iomuxc *iomux = (struct iomuxc *) IOMUXC_BASE_ADDR; | |
391 | - u32 reg = readl(&iomux->gpr[2]); | |
392 | - | |
393 | - reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; | |
394 | - writel(reg, &iomux->gpr[2]); | |
395 | - | |
396 | 390 | /* backlights off until needed */ |
397 | 391 | imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); |
398 | 392 | |
399 | - gpio_direction_output(IMX_GPIO_NR(6, 7), 1); | |
400 | - | |
401 | - /* enable backlight PWM 1 */ | |
393 | + /* enable backlight PWM 1 */ | |
402 | 394 | if (pwm_init(0, 0, 0)) |
403 | 395 | goto error; |
404 | 396 | /* duty cycle 500ns, period: 3000ns */ |
... | ... | @@ -406,6 +398,11 @@ static void enable_lvds(struct display_info_t const *dev) |
406 | 398 | goto error; |
407 | 399 | if (pwm_enable(0)) |
408 | 400 | goto error; |
401 | + | |
402 | + gpio_direction_output(IMX_GPIO_NR(6, 7), 0); | |
403 | + mdelay(100); | |
404 | + gpio_set_value(IMX_GPIO_NR(6, 7), 1); | |
405 | + | |
409 | 406 | return; |
410 | 407 | |
411 | 408 | error: |
... | ... | @@ -425,10 +422,6 @@ static void enable_lvds_jeida(struct display_info_t const *dev) |
425 | 422 | /* backlights off until needed */ |
426 | 423 | imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); |
427 | 424 | |
428 | - gpio_direction_output(IMX_GPIO_NR(6, 7), 0); | |
429 | - mdelay(100); | |
430 | - gpio_set_value(IMX_GPIO_NR(6, 7), 1); | |
431 | - | |
432 | 425 | /* enable backlight PWM 1 */ |
433 | 426 | if (pwm_init(0, 0, 0)) |
434 | 427 | goto error; |
... | ... | @@ -437,6 +430,11 @@ static void enable_lvds_jeida(struct display_info_t const *dev) |
437 | 430 | goto error; |
438 | 431 | if (pwm_enable(0)) |
439 | 432 | goto error; |
433 | + | |
434 | + gpio_direction_output(IMX_GPIO_NR(6, 7), 0); | |
435 | + mdelay(100); | |
436 | + gpio_set_value(IMX_GPIO_NR(6, 7), 1); | |
437 | + | |
440 | 438 | return; |
441 | 439 | |
442 | 440 | error: |
... | ... | @@ -448,7 +446,7 @@ struct display_info_t const displays[] = { |
448 | 446 | { |
449 | 447 | .bus = -1, |
450 | 448 | .addr = 0, |
451 | - .pixfmt = IPU_PIX_FMT_RGB24, | |
449 | + .pixfmt = IPU_PIX_FMT_RGB666, // IPU_PIX_FMT_LVDS666 | |
452 | 450 | .detect = NULL, |
453 | 451 | .enable = enable_lvds, |
454 | 452 | .mode = { |
... | ... | @@ -456,18 +454,14 @@ struct display_info_t const displays[] = { |
456 | 454 | .refresh = 60, |
457 | 455 | .xres = 1600, |
458 | 456 | .yres = 900, |
459 | - .pixclock = 10800, // ((1000000000 / (1600+44+24+24) * 1000) / (900+7+2+3)) / 60 = 10800 | |
460 | -// .pixclock = KHZ2PICOS(108000), // ((1000000000 / (1600+44+24+24) * 1000) / (900+7+2+3)) / 60 = 10800 | |
461 | - .left_margin = 44, // hsync back porch | |
457 | + .pixclock = 10800, // ((1000000000 / (1600+44+24+24) * 1000) / (900+7+2+3)) / 60 = 10800 | |
458 | + .left_margin = 54, // hsync back porch | |
462 | 459 | .right_margin = 24, // hsync front porch |
463 | 460 | .upper_margin = 7, // vsync back porch |
464 | 461 | .lower_margin = 2, // hsync fron porch |
465 | 462 | .hsync_len = 24, |
466 | 463 | .vsync_len = 3, |
467 | -// .sync = 0, | |
468 | - .sync = FB_SYNC_HOR_HIGH_ACT | | |
469 | - FB_SYNC_VERT_HIGH_ACT | | |
470 | - FB_SYNC_EXT, | |
464 | + .sync = FB_SYNC_EXT, | |
471 | 465 | .vmode = FB_VMODE_NONINTERLACED |
472 | 466 | } |
473 | 467 | } |
... | ... | @@ -488,7 +482,8 @@ static void setup_display(void) |
488 | 482 | |
489 | 483 | /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */ |
490 | 484 | reg = readl(&mxc_ccm->cscmr2); |
491 | - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; | |
485 | + reg &= ~(MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV); // divide by 3.5 | |
486 | +// reg |= (MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV); // divide by 7 | |
492 | 487 | writel(reg, &mxc_ccm->cscmr2); |
493 | 488 | |
494 | 489 | /* Set LDB_DI0, LDB_DI1 as clock source for IPU_DI0, IPU_DI1 */ |
... | ... | @@ -516,9 +511,9 @@ static void setup_display(void) |
516 | 511 | |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
517 | 512 | |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
518 | 513 | |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
519 | - |IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT | |
514 | + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | |
520 | 515 | |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
521 | - |IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | |
516 | + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | |
522 | 517 | |IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
523 | 518 | |IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 |
524 | 519 | |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; |
... | ... | @@ -529,7 +524,6 @@ static void setup_display(void) |
529 | 524 | | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
530 | 525 | | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); |
531 | 526 | writel(reg, &iomux->gpr[3]); |
532 | - | |
533 | 527 | } |
534 | 528 | #endif |
535 | 529 | |
... | ... | @@ -637,5 +631,5 @@ int misc_init_r(void) |
637 | 631 | #endif |
638 | 632 | setenv_hex("reset_cause", get_imx_reset_cause()); |
639 | 633 | |
640 | - return 0; | |
634 | + return 0; | |
641 | 635 | } | ... | ... |
bootloader/u-boot_2015_04/drivers/video/ipu_disp.c
... | ... | @@ -887,15 +887,15 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, |
887 | 887 | } |
888 | 888 | clk_set_parent(g_pixel_clk[disp], g_ldb_clk); |
889 | 889 | } else { |
890 | - if (clk_get_usecount(g_pixel_clk[disp]) != 0) | |
890 | + if (clk_get_usecount(g_pixel_clk[disp]) != 0) { | |
891 | 891 | clk_set_parent(g_pixel_clk[disp], g_ipu_clk); |
892 | + } | |
892 | 893 | } |
893 | 894 | rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk); |
894 | 895 | clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk); |
895 | 896 | udelay(5000); |
896 | 897 | /* Get integer portion of divider */ |
897 | - div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) / | |
898 | - rounded_pixel_clk; | |
898 | + div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) / rounded_pixel_clk; | |
899 | 899 | |
900 | 900 | ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1); |
901 | 901 | ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2); | ... | ... |
bootloader/u-boot_2015_04/drivers/video/mxc_ipuv3_fb.c
... | ... | @@ -259,7 +259,6 @@ static int mxcfb_set_par(struct fb_info *fbi) |
259 | 259 | sig_cfg.clkidle_en = 1; |
260 | 260 | |
261 | 261 | debug("pixclock = %lu Hz\n", PICOS2KHZ(fbi->var.pixclock) * 1000UL); |
262 | - printf("pixclock = %lu Hz\n", PICOS2KHZ(fbi->var.pixclock) * 1000UL); | |
263 | 262 | |
264 | 263 | if (ipu_init_sync_panel(mxc_fbi->ipu_di, |
265 | 264 | (PICOS2KHZ(fbi->var.pixclock)) * 1000UL, | ... | ... |
kernel/linux-imx6_3.14.28/arch/arm/boot/dts/imx6qdl-prime-oven.dtsi
... | ... | @@ -410,10 +410,10 @@ |
410 | 410 | display-timings { |
411 | 411 | native-mode = <&timing0>; |
412 | 412 | timing0: LDB-LP133WD2 { |
413 | - clock-frequency = <96870000>; /* 48870000 */ | |
413 | + clock-frequency = <92592000>; /* 48870000 96870000*/ | |
414 | 414 | hactive = <1600>; |
415 | 415 | vactive = <900>; |
416 | - hback-porch = <44>; | |
416 | + hback-porch = <54>; | |
417 | 417 | hfront-porch = <24>; |
418 | 418 | vback-porch = <7>; |
419 | 419 | vfront-porch = <2>; | ... | ... |