에프에이리눅스 / 1611_0007_prime_oven

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Commit e947c772f382f9b8f824a429bcfcc26330d89ec8

Authored by 장형기
1 parent 7f123cea46
Exists in master and in 2 other branches fhd, fhd-demo

lcd

Showing 6 changed files with 90 additions and 40 deletions   Show diff stats
bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/mx6s_prime_oven.c
  Diff comments   View file @e947c77
... ... @@ -33,6 +33,7 @@
33 33 #include <input.h>
34 34 #include <netdev.h>
35 35 #include <usb/ehci-fsl.h>
  36 +#include <pwm.h>
36 37  
37 38 DECLARE_GLOBAL_DATA_PTR;
38 39  
... ... @@ -392,7 +393,24 @@ static void enable_lvds(struct display_info_t const *dev)
392 393 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
393 394 writel(reg, &iomux->gpr[2]);
394 395  
  396 + /* backlights off until needed */
  397 + imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
  398 +
395 399 gpio_direction_output(IMX_GPIO_NR(6, 7), 1);
  400 +
  401 + /* enable backlight PWM 1 */
  402 + if (pwm_init(0, 0, 0))
  403 + goto error;
  404 + /* duty cycle 500ns, period: 3000ns */
  405 + if (pwm_config(0, 500, 3000))
  406 + goto error;
  407 + if (pwm_enable(0))
  408 + goto error;
  409 + return;
  410 +
  411 +error:
  412 + puts("error init pwm for backlight\n");
  413 + return;
396 414 }
397 415  
398 416 static void enable_lvds_jeida(struct display_info_t const *dev)
... ... @@ -404,7 +422,26 @@ static void enable_lvds_jeida(struct display_info_t const *dev)
404 422 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA;
405 423 writel(reg, &iomux->gpr[2]);
406 424  
407   - gpio_direction_output(IMX_GPIO_NR(6, 7), 1);
  425 + /* backlights off until needed */
  426 + imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
  427 +
  428 + gpio_direction_output(IMX_GPIO_NR(6, 7), 0);
  429 + mdelay(100);
  430 + gpio_set_value(IMX_GPIO_NR(6, 7), 1);
  431 +
  432 + /* enable backlight PWM 1 */
  433 + if (pwm_init(0, 0, 0))
  434 + goto error;
  435 + /* duty cycle 500ns, period: 3000ns */
  436 + if (pwm_config(0, 500, 3000))
  437 + goto error;
  438 + if (pwm_enable(0))
  439 + goto error;
  440 + return;
  441 +
  442 +error:
  443 + puts("error init pwm for backlight\n");
  444 + return;
408 445 }
409 446  
410 447 struct display_info_t const displays[] = {
... ... @@ -419,15 +456,19 @@ struct display_info_t const displays[] = {
419 456 .refresh = 60,
420 457 .xres = 1600,
421 458 .yres = 900,
422   - .pixclock = KHZ2PICOS(108000), // ((1000000000 / (1600+44+24+24) * 1000) / (900+7+2+3)) / 60 = 10800
  459 + .pixclock = 10800, // ((1000000000 / (1600+44+24+24) * 1000) / (900+7+2+3)) / 60 = 10800
  460 +// .pixclock = KHZ2PICOS(108000), // ((1000000000 / (1600+44+24+24) * 1000) / (900+7+2+3)) / 60 = 10800
423 461 .left_margin = 44, // hsync back porch
424 462 .right_margin = 24, // hsync front porch
425 463 .upper_margin = 7, // vsync back porch
426 464 .lower_margin = 2, // hsync fron porch
427 465 .hsync_len = 24,
428 466 .vsync_len = 3,
429   - .sync = 0,
430   - .vmode = FB_VMODE_NONINTERLACED
  467 +// .sync = 0,
  468 + .sync = FB_SYNC_HOR_HIGH_ACT |
  469 + FB_SYNC_VERT_HIGH_ACT |
  470 + FB_SYNC_EXT,
  471 + .vmode = FB_VMODE_NONINTERLACED
431 472 }
432 473 }
433 474 };
... ... @@ -445,50 +486,50 @@ static void setup_display(void)
445 486 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
446 487 int reg;
447 488  
448   - enable_ipu_clock();
449   - imx_setup_hdmi();
  489 + /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
  490 + reg = readl(&mxc_ccm->cscmr2);
  491 + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
  492 + writel(reg, &mxc_ccm->cscmr2);
  493 +
  494 + /* Set LDB_DI0, LDB_DI1 as clock source for IPU_DI0, IPU_DI1 */
  495 + reg = readl(&mxc_ccm->chsccdr);
  496 + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  497 + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
  498 + writel(reg, &mxc_ccm->chsccdr);
450 499  
451 500 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
452 501 reg = __raw_readl(&mxc_ccm->CCGR3);
453 502 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
454   - writel(reg, &mxc_ccm->CCGR3);
  503 + writel(reg, &mxc_ccm->CCGR3);
  504 +
  505 + enable_ipu_clock();
455 506  
456 507 /* set LDB0, LDB1 clk select to 011/011 */
457 508 reg = readl(&mxc_ccm->cs2cdr);
458 509 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
459   - reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
460   - |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
461   - writel(reg, &mxc_ccm->cs2cdr);
462   -
463   - reg = readl(&mxc_ccm->cscmr2);
464   - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
465   - writel(reg, &mxc_ccm->cscmr2);
466   -
467   - reg = readl(&mxc_ccm->chsccdr);
468   - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
469   - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
470   - writel(reg, &mxc_ccm->chsccdr);
  510 + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  511 + |(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  512 + writel(reg, &mxc_ccm->cs2cdr);
471 513  
472 514 // LVDS Ch0, Ch1 Enable
473 515 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
474   - |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  516 + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
475 517 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
476 518 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
477   - |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  519 + |IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
478 520 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
479   - |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  521 + |IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
480 522 |IOMUXC_GPR2_SPLIT_MODE_EN_MASK
481 523 |IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
482 524 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
483   - writel(reg, &iomux->gpr[2]);
  525 + writel(reg, &iomux->gpr[2]);
484 526  
485 527 reg = readl(&iomux->gpr[3]);
486   - reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
487   - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET | IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
488   - writel(reg, &iomux->gpr[3]);
489   -
490   - /* backlights off until needed */
491   - imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
  528 + reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | IOMUXC_GPR3_LVDS1_MUX_CTL_MASK))
  529 + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
  530 + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
  531 + writel(reg, &iomux->gpr[3]);
  532 +
492 533 }
493 534 #endif
494 535  
... ... @@ -589,12 +630,12 @@ static const struct boot_mode board_boot_modes[] = {
589 630  
590 631 int misc_init_r(void)
591 632 {
592   - // [FALINUX]
593   - setup_gpio();
  633 + setup_gpio();
594 634  
595 635 #ifdef CONFIG_CMD_BMODE
596 636 add_board_boot_modes(board_boot_modes);
597 637 #endif
598 638 setenv_hex("reset_cause", get_imx_reset_cause());
  639 +
599 640 return 0;
600 641 }
... ...
bootloader/u-boot_2015_04/drivers/net/fec_mxc.c
  Diff comments   View file @e947c77
... ... @@ -570,7 +570,9 @@ static int fec_open(struct eth_device *edev)
570 570 #ifdef FEC_QUIRK_ENET_MAC
571 571 {
572 572 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
573   - u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
  573 + u32 rcr = (readl(&fec->eth->r_cntrl) &
  574 + ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
  575 + FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
574 576 if (speed == _1000BASET)
575 577 ecr |= FEC_ECNTRL_SPEED;
576 578 else if (speed != _100BASET)
... ...
bootloader/u-boot_2015_04/drivers/video/mxc_ipuv3_fb.c
  Diff comments   View file @e947c77
... ... @@ -259,6 +259,7 @@ static int mxcfb_set_par(struct fb_info *fbi)
259 259 sig_cfg.clkidle_en = 1;
260 260  
261 261 debug("pixclock = %lu Hz\n", PICOS2KHZ(fbi->var.pixclock) * 1000UL);
  262 + printf("pixclock = %lu Hz\n", PICOS2KHZ(fbi->var.pixclock) * 1000UL);
262 263  
263 264 if (ipu_init_sync_panel(mxc_fbi->ipu_di,
264 265 (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
... ...
bootloader/u-boot_2015_04/include/common.h
  Diff comments   View file @e947c77
... ... @@ -88,6 +88,9 @@ typedef volatile unsigned char vu_char;
88 88 #define CONFIG_SYS_SUPPORT_64BIT_DATA
89 89 #endif
90 90  
  91 +
  92 +//#define DEBUG
  93 +
91 94 #ifdef DEBUG
92 95 #define _DEBUG 1
93 96 #else
... ...
bootloader/u-boot_2015_04/include/configs/mx6s_prime_oven.h
  Diff comments   View file @e947c77
... ... @@ -114,27 +114,30 @@
114 114 #define CONFIG_CMD_BMODE
115 115 #define CONFIG_CMD_SETEXPR
116 116  
117   -
118 117 /* Framebuffer and LCD */
119   -#if 0
  118 +#if 1
120 119 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
121   -#else
  120 +#endif
122 121 #define CONFIG_VIDEO
123 122 #define CONFIG_VIDEO_IPUV3
124 123 #define CONFIG_CFB_CONSOLE
125 124 #define CONFIG_VGA_AS_SINGLE_DEVICE
126 125 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
127   -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
128 126 #define CONFIG_VIDEO_BMP_RLE8
129 127 #define CONFIG_SPLASH_SCREEN
  128 +#define CONFIG_SPLASH_SCREEN_ALIGN
130 129 #define CONFIG_BMP_16BPP
131 130  
132 131 #define CONFIG_VIDEO_LOGO
133 132 #define CONFIG_VIDEO_BMP_LOGO
134   -#define CONFIG_IPUV3_CLK 260000000
135   -#define CONFIG_IMX_HDMI
  133 +#define CONFIG_IPUV3_CLK 198000000 // 260000000
136 134 #define CONFIG_IMX_VIDEO_SKIP
137   -#endif
  135 +
  136 +#define CONFIG_CMD_BMP
  137 +
  138 +#define CONFIG_PWM_IMX
  139 +#define CONFIG_IMX6_PWM_PER_CLK 66000000
  140 +
138 141  
139 142 /* allow to overwrite serial and ethaddr */
140 143 #define CONFIG_ENV_OVERWRITE
... ...
kernel/linux-imx6_3.14.28/arch/arm/boot/dts/imx6qdl-prime-oven.dtsi
  Diff comments   View file @e947c77
... ... @@ -399,7 +399,7 @@
399 399  
400 400 &ldb {
401 401 split-mode = <1>;
402   - status = "okay";
  402 + status = "okay";
403 403  
404 404 lvds-channel@0 {
405 405 fsl,data-mapping = "spwg";
... ...