From e947c772f382f9b8f824a429bcfcc26330d89ec8 Mon Sep 17 00:00:00 2001 From: kailink Date: Fri, 24 Feb 2017 22:28:25 +0900 Subject: [PATCH] lcd --- .../falinux/mx6s_prime_oven/mx6s_prime_oven.c | 103 ++++++++++++++------- bootloader/u-boot_2015_04/drivers/net/fec_mxc.c | 4 +- .../u-boot_2015_04/drivers/video/mxc_ipuv3_fb.c | 1 + bootloader/u-boot_2015_04/include/common.h | 3 + .../include/configs/mx6s_prime_oven.h | 17 ++-- .../arch/arm/boot/dts/imx6qdl-prime-oven.dtsi | 2 +- 6 files changed, 90 insertions(+), 40 deletions(-) diff --git a/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/mx6s_prime_oven.c b/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/mx6s_prime_oven.c index d630a67..c448295 100755 --- a/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/mx6s_prime_oven.c +++ b/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/mx6s_prime_oven.c @@ -33,6 +33,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -392,7 +393,24 @@ static void enable_lvds(struct display_info_t const *dev) reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; writel(reg, &iomux->gpr[2]); + /* backlights off until needed */ + imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); + gpio_direction_output(IMX_GPIO_NR(6, 7), 1); + + /* enable backlight PWM 1 */ + if (pwm_init(0, 0, 0)) + goto error; + /* duty cycle 500ns, period: 3000ns */ + if (pwm_config(0, 500, 3000)) + goto error; + if (pwm_enable(0)) + goto error; + return; + +error: + puts("error init pwm for backlight\n"); + return; } static void enable_lvds_jeida(struct display_info_t const *dev) @@ -404,7 +422,26 @@ static void enable_lvds_jeida(struct display_info_t const *dev) IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA; writel(reg, &iomux->gpr[2]); - gpio_direction_output(IMX_GPIO_NR(6, 7), 1); + /* backlights off until needed */ + imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); + + gpio_direction_output(IMX_GPIO_NR(6, 7), 0); + mdelay(100); + gpio_set_value(IMX_GPIO_NR(6, 7), 1); + + /* enable backlight PWM 1 */ + if (pwm_init(0, 0, 0)) + goto error; + /* duty cycle 500ns, period: 3000ns */ + if (pwm_config(0, 500, 3000)) + goto error; + if (pwm_enable(0)) + goto error; + return; + +error: + puts("error init pwm for backlight\n"); + return; } struct display_info_t const displays[] = { @@ -419,15 +456,19 @@ struct display_info_t const displays[] = { .refresh = 60, .xres = 1600, .yres = 900, - .pixclock = KHZ2PICOS(108000), // ((1000000000 / (1600+44+24+24) * 1000) / (900+7+2+3)) / 60 = 10800 + .pixclock = 10800, // ((1000000000 / (1600+44+24+24) * 1000) / (900+7+2+3)) / 60 = 10800 +// .pixclock = KHZ2PICOS(108000), // ((1000000000 / (1600+44+24+24) * 1000) / (900+7+2+3)) / 60 = 10800 .left_margin = 44, // hsync back porch .right_margin = 24, // hsync front porch .upper_margin = 7, // vsync back porch .lower_margin = 2, // hsync fron porch .hsync_len = 24, .vsync_len = 3, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED +// .sync = 0, + .sync = FB_SYNC_HOR_HIGH_ACT | + FB_SYNC_VERT_HIGH_ACT | + FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED } } }; @@ -445,50 +486,50 @@ static void setup_display(void) struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; int reg; - enable_ipu_clock(); - imx_setup_hdmi(); + /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */ + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + /* Set LDB_DI0, LDB_DI1 as clock source for IPU_DI0, IPU_DI1 */ + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ reg = __raw_readl(&mxc_ccm->CCGR3); reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; - writel(reg, &mxc_ccm->CCGR3); + writel(reg, &mxc_ccm->CCGR3); + + enable_ipu_clock(); /* set LDB0, LDB1 clk select to 011/011 */ reg = readl(&mxc_ccm->cs2cdr); reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - reg |= (3<cs2cdr); - - reg = readl(&mxc_ccm->cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; - writel(reg, &mxc_ccm->cscmr2); - - reg = readl(&mxc_ccm->chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); - writel(reg, &mxc_ccm->chsccdr); + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + |(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); // LVDS Ch0, Ch1 Enable reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES - |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG - |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG - |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |IOMUXC_GPR2_SPLIT_MODE_EN_MASK |IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; - writel(reg, &iomux->gpr[2]); + writel(reg, &iomux->gpr[2]); reg = readl(&iomux->gpr[3]); - reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET | IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); - writel(reg, &iomux->gpr[3]); - - /* backlights off until needed */ - imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); + reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | IOMUXC_GPR3_LVDS1_MUX_CTL_MASK)) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); + } #endif @@ -589,12 +630,12 @@ static const struct boot_mode board_boot_modes[] = { int misc_init_r(void) { - // [FALINUX] - setup_gpio(); + setup_gpio(); #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif setenv_hex("reset_cause", get_imx_reset_cause()); + return 0; } diff --git a/bootloader/u-boot_2015_04/drivers/net/fec_mxc.c b/bootloader/u-boot_2015_04/drivers/net/fec_mxc.c index 48cc5cf..ba2d550 100644 --- a/bootloader/u-boot_2015_04/drivers/net/fec_mxc.c +++ b/bootloader/u-boot_2015_04/drivers/net/fec_mxc.c @@ -570,7 +570,9 @@ static int fec_open(struct eth_device *edev) #ifdef FEC_QUIRK_ENET_MAC { u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; - u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; + u32 rcr = (readl(&fec->eth->r_cntrl) & + ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) | + FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE; if (speed == _1000BASET) ecr |= FEC_ECNTRL_SPEED; else if (speed != _100BASET) diff --git a/bootloader/u-boot_2015_04/drivers/video/mxc_ipuv3_fb.c b/bootloader/u-boot_2015_04/drivers/video/mxc_ipuv3_fb.c index 1fa9531..c9f4aff 100644 --- a/bootloader/u-boot_2015_04/drivers/video/mxc_ipuv3_fb.c +++ b/bootloader/u-boot_2015_04/drivers/video/mxc_ipuv3_fb.c @@ -259,6 +259,7 @@ static int mxcfb_set_par(struct fb_info *fbi) sig_cfg.clkidle_en = 1; debug("pixclock = %lu Hz\n", PICOS2KHZ(fbi->var.pixclock) * 1000UL); + printf("pixclock = %lu Hz\n", PICOS2KHZ(fbi->var.pixclock) * 1000UL); if (ipu_init_sync_panel(mxc_fbi->ipu_di, (PICOS2KHZ(fbi->var.pixclock)) * 1000UL, diff --git a/bootloader/u-boot_2015_04/include/common.h b/bootloader/u-boot_2015_04/include/common.h index 6df05b8..8db3990 100644 --- a/bootloader/u-boot_2015_04/include/common.h +++ b/bootloader/u-boot_2015_04/include/common.h @@ -88,6 +88,9 @@ typedef volatile unsigned char vu_char; #define CONFIG_SYS_SUPPORT_64BIT_DATA #endif + +//#define DEBUG + #ifdef DEBUG #define _DEBUG 1 #else diff --git a/bootloader/u-boot_2015_04/include/configs/mx6s_prime_oven.h b/bootloader/u-boot_2015_04/include/configs/mx6s_prime_oven.h index a7042bc..c52b04e 100755 --- a/bootloader/u-boot_2015_04/include/configs/mx6s_prime_oven.h +++ b/bootloader/u-boot_2015_04/include/configs/mx6s_prime_oven.h @@ -114,27 +114,30 @@ #define CONFIG_CMD_BMODE #define CONFIG_CMD_SETEXPR - /* Framebuffer and LCD */ -#if 0 +#if 1 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#else +#endif #define CONFIG_VIDEO #define CONFIG_VIDEO_IPUV3 #define CONFIG_CFB_CONSOLE #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN #define CONFIG_BMP_16BPP #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IPUV3_CLK 260000000 -#define CONFIG_IMX_HDMI +#define CONFIG_IPUV3_CLK 198000000 // 260000000 #define CONFIG_IMX_VIDEO_SKIP -#endif + +#define CONFIG_CMD_BMP + +#define CONFIG_PWM_IMX +#define CONFIG_IMX6_PWM_PER_CLK 66000000 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/kernel/linux-imx6_3.14.28/arch/arm/boot/dts/imx6qdl-prime-oven.dtsi b/kernel/linux-imx6_3.14.28/arch/arm/boot/dts/imx6qdl-prime-oven.dtsi index 2e9e71c..2b900db 100755 --- a/kernel/linux-imx6_3.14.28/arch/arm/boot/dts/imx6qdl-prime-oven.dtsi +++ b/kernel/linux-imx6_3.14.28/arch/arm/boot/dts/imx6qdl-prime-oven.dtsi @@ -399,7 +399,7 @@ &ldb { split-mode = <1>; - status = "okay"; + status = "okay"; lvds-channel@0 { fsl,data-mapping = "spwg"; -- 2.1.4