에프에이리눅스 / 1611_0007_prime_oven

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Commit e5a0c50f8d154291e3c7ae396568f165ee0ac646

Authored by 장형기
1 parent ffaebe8c64
Exists in master and in 2 other branches fhd, fhd-demo

pin mux 수정

Showing 8 changed files with 199 additions and 341 deletions   Show diff stats
bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/800mhz_2x256mx16.cfg 100644 → 100755
  Diff comments   View file @e5a0c50
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bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/Kconfig 100644 → 100755
  Diff comments   View file @e5a0c50
File mode changed
bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/Makefile 100644 → 100755
  Diff comments   View file @e5a0c50
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bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/clocks.cfg
  Diff comments   View file @e5a0c50
@@ -19,7 +19,7 @@ @@ -19,7 +19,7 @@
19 DATA 4, CCM_CCGR0, 0x00C03F3F 19 DATA 4, CCM_CCGR0, 0x00C03F3F
20 DATA 4, CCM_CCGR1, 0x0030FC03 20 DATA 4, CCM_CCGR1, 0x0030FC03
21 DATA 4, CCM_CCGR2, 0x0FFFC000 21 DATA 4, CCM_CCGR2, 0x0FFFC000
22 -DATA 4, CCM_CCGR3, 0x3FF00000 22 +DATA 4, CCM_CCGR3, 0x3FF0F000
23 DATA 4, CCM_CCGR4, 0x00FFF300 23 DATA 4, CCM_CCGR4, 0x00FFF300
24 DATA 4, CCM_CCGR5, 0x0FFC00C3 24 DATA 4, CCM_CCGR5, 0x0FFC00C3
25 DATA 4, CCM_CCGR6, 0x000003FF 25 DATA 4, CCM_CCGR6, 0x000003FF
bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/ddr-setup.cfg 100644 → 100755
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bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/mx6s_prime_oven.c
  Diff comments   View file @e5a0c50
@@ -36,65 +36,61 @@ @@ -36,65 +36,61 @@
36 36
37 DECLARE_GLOBAL_DATA_PTR; 37 DECLARE_GLOBAL_DATA_PTR;
38 38
39 -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \  
40 - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \  
41 - PAD_CTL_SRE_FAST | PAD_CTL_HYS) 39 +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  40 + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  41 + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42 42
43 -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \  
44 - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \  
45 - PAD_CTL_SRE_FAST | PAD_CTL_HYS) 43 +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  44 + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  45 + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46 46
47 -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \  
48 - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 47 +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  48 + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
49 49
50 -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \  
51 - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 50 +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  51 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
52 52
53 -#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \  
54 - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 53 +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  54 + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  55 + PAD_CTL_ODE | PAD_CTL_SRE_FAST)
55 56
56 -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \  
57 - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \  
58 - PAD_CTL_ODE | PAD_CTL_SRE_FAST) 57 +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
59 58
60 -#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \  
61 - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \  
62 - PAD_CTL_SRE_SLOW)  
63 -  
64 -#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \  
65 - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \  
66 - PAD_CTL_HYS | PAD_CTL_SRE_SLOW)  
67 -  
68 -#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)  
69 59
70 int dram_init(void) 60 int dram_init(void)
71 { 61 {
72 gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); 62 gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
73 -  
74 return 0; 63 return 0;
75 } 64 }
76 65
  66 +// Console
77 static iomux_v3_cfg_t const uart1_pads[] = { 67 static iomux_v3_cfg_t const uart1_pads[] = {
78 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 68 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
79 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 69 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
80 }; 70 };
81 71
  72 +// TTL232
82 static iomux_v3_cfg_t const uart2_pads[] = { 73 static iomux_v3_cfg_t const uart2_pads[] = {
83 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 74 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
84 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 75 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
85 }; 76 };
86 77
87 -static iomux_v3_cfg_t const uart23_pads[] = { 78 +// RS485 Ch1
  79 +static iomux_v3_cfg_t const uart3_pads[] = {
88 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 80 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
89 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 81 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
90 - MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),  
91 - MX6_PAD_EIM_D30__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 82 +};
  83 +
  84 +// RS485 Ch2
  85 +static iomux_v3_cfg_t const uart4_pads[] = {
  86 + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  87 + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
92 }; 88 };
93 89
94 90
95 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 91 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
96 92
97 -/* I2C1 SGTL5000, Ext-I2C#0 */ 93 +/* I2C1 : SGTL5000 */
98 static struct i2c_pads_info i2c_pad_info0 = { 94 static struct i2c_pads_info i2c_pad_info0 = {
99 .scl = { 95 .scl = {
100 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, 96 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
@@ -108,7 +104,7 @@ static struct i2c_pads_info i2c_pad_info0 = { @@ -108,7 +104,7 @@ static struct i2c_pads_info i2c_pad_info0 = {
108 } 104 }
109 }; 105 };
110 106
111 -/* I2C2 PMCI, DS1339(RTC), Mac address, touch, HDMI */ 107 +/* I2C2 : PMCI, DS1339(RTC), Mac address, touch */
112 static struct i2c_pads_info i2c_pad_info1 = { 108 static struct i2c_pads_info i2c_pad_info1 = {
113 .scl = { 109 .scl = {
114 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, 110 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
@@ -122,7 +118,7 @@ static struct i2c_pads_info i2c_pad_info1 = { @@ -122,7 +118,7 @@ static struct i2c_pads_info i2c_pad_info1 = {
122 } 118 }
123 }; 119 };
124 120
125 -/* I2C3 Ext-I2C#1 */ 121 +/* I2C3 : Reserved */
126 static struct i2c_pads_info i2c_pad_info2 = { 122 static struct i2c_pads_info i2c_pad_info2 = {
127 .scl = { 123 .scl = {
128 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, 124 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
@@ -133,20 +129,9 @@ static struct i2c_pads_info i2c_pad_info2 = { @@ -133,20 +129,9 @@ static struct i2c_pads_info i2c_pad_info2 = {
133 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, 129 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
134 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, 130 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
135 .gp = IMX_GPIO_NR(1, 6) 131 .gp = IMX_GPIO_NR(1, 6)
136 - } 132 + }
137 }; 133 };
138 134
139 -// Wifi  
140 -static iomux_v3_cfg_t const usdhc2_pads[] = {  
141 - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),  
142 - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),  
143 - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),  
144 - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),  
145 - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),  
146 - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),  
147 - MX6_PAD_SD3_DAT7__GPIO6_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */  
148 - MX6_PAD_SD3_DAT6__GPIO6_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */  
149 -};  
150 135
151 // Micro-SD 136 // Micro-SD
152 static iomux_v3_cfg_t const usdhc3_pads[] = { 137 static iomux_v3_cfg_t const usdhc3_pads[] = {
@@ -176,15 +161,41 @@ static iomux_v3_cfg_t const usdhc4_pads[] = { @@ -176,15 +161,41 @@ static iomux_v3_cfg_t const usdhc4_pads[] = {
176 static iomux_v3_cfg_t const usb_pads[] = { 161 static iomux_v3_cfg_t const usb_pads[] = {
177 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB1_DRVVBUS 162 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB1_DRVVBUS
178 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB2_DRVVBUS 163 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB2_DRVVBUS
179 - MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB4_DRVVBUS  
180 }; 164 };
181 165
182 static void setup_iomux_uart(void) 166 static void setup_iomux_uart(void)
183 { 167 {
184 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 168 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
185 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 169 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  170 + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
  171 + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  172 +}
  173 +
  174 +#ifdef CONFIG_MXC_SPI
  175 +int board_spi_cs_gpio(unsigned bus, unsigned cs)
  176 +{
  177 + switch (bus){
  178 + case 0 :
  179 + if(cs == 1) return IMX_GPIO_NR(3, 19);
  180 + else return -1;
  181 + default : return -1;
  182 + }
186 } 183 }
187 184
  185 +static iomux_v3_cfg_t const ecspi1_pads[] = {
  186 + /* SPI1 */
  187 + MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* SS1 */
  188 + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), /* MISO */
  189 + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), /* MOSI */
  190 + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), /* SLCK */
  191 +};
  192 +
  193 +static void setup_spi(void)
  194 +{
  195 + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  196 +}
  197 +#endif
  198 +
188 #ifdef CONFIG_USB_EHCI_MX6 199 #ifdef CONFIG_USB_EHCI_MX6
189 int board_ehci_hcd_init(int port) 200 int board_ehci_hcd_init(int port)
190 { 201 {
@@ -193,11 +204,9 @@ int board_ehci_hcd_init(int port) @@ -193,11 +204,9 @@ int board_ehci_hcd_init(int port)
193 /* Reset USB Power */ 204 /* Reset USB Power */
194 gpio_direction_output(IMX_GPIO_NR(2, 0), 0); 205 gpio_direction_output(IMX_GPIO_NR(2, 0), 0);
195 gpio_direction_output(IMX_GPIO_NR(2, 1), 0); 206 gpio_direction_output(IMX_GPIO_NR(2, 1), 0);
196 - gpio_direction_output(IMX_GPIO_NR(2, 2), 0);  
197 mdelay(2); 207 mdelay(2);
198 gpio_set_value(IMX_GPIO_NR(2, 0), 1); 208 gpio_set_value(IMX_GPIO_NR(2, 0), 1);
199 gpio_set_value(IMX_GPIO_NR(2, 1), 1); 209 gpio_set_value(IMX_GPIO_NR(2, 1), 1);
200 - gpio_set_value(IMX_GPIO_NR(2, 2), 1);  
201 210
202 return 0; 211 return 0;
203 } 212 }
@@ -268,53 +277,25 @@ int board_mmc_init(bd_t *bis) @@ -268,53 +277,25 @@ int board_mmc_init(bd_t *bis)
268 } 277 }
269 #endif 278 #endif
270 279
271 -#ifdef CONFIG_MXC_SPI  
272 -int board_spi_cs_gpio(unsigned bus, unsigned cs)  
273 -{  
274 - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;  
275 -}  
276 -  
277 -static iomux_v3_cfg_t const ecspi1_pads[] = {  
278 - /* SS1 */  
279 - MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),  
280 - MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),  
281 - MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),  
282 - MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),  
283 -};  
284 -  
285 -static iomux_v3_cfg_t const ecspi2_pads[] = {  
286 - /* SS1 */  
287 - MX6_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),  
288 - MX6_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),  
289 - MX6_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),  
290 - MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),  
291 -};  
292 -  
293 -static void setup_spi(void)  
294 -{  
295 - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));  
296 - imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));  
297 -}  
298 -#endif  
299 280
300 static iomux_v3_cfg_t const enet_pads[] = { 281 static iomux_v3_cfg_t const enet_pads[] = {
301 - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),  
302 - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),  
303 - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),  
304 - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),  
305 - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),  
306 - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),  
307 - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),  
308 - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),  
309 - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),  
310 - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),  
311 - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),  
312 - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),  
313 - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),  
314 - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),  
315 - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 282 + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  283 + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  284 + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  285 + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  286 + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  287 + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  288 + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  289 + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  290 + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  291 + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  292 + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  293 + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  294 + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  295 + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  296 + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
316 /* AR8031 PHY Reset */ 297 /* AR8031 PHY Reset */
317 - MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), 298 + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
318 }; 299 };
319 300
320 static void setup_iomux_enet(void) 301 static void setup_iomux_enet(void)
@@ -396,129 +377,60 @@ int board_eth_init(bd_t *bis) @@ -396,129 +377,60 @@ int board_eth_init(bd_t *bis)
396 #if defined(CONFIG_VIDEO_IPUV3) 377 #if defined(CONFIG_VIDEO_IPUV3)
397 378
398 static iomux_v3_cfg_t const backlight_pads[] = { 379 static iomux_v3_cfg_t const backlight_pads[] = {
399 - /* Backlight on RGB connector: J15 */  
400 - MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),  
401 -#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)  
402 -  
403 - /* Backlight on LVDS connector: J6 */  
404 - MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),  
405 -#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) 380 + /* Backlight power enable */
  381 + MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), // LCD_PWR_EN
  382 + /* Backlight brightness */
  383 + MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), // LCD_PWM1
406 }; 384 };
407 385
408 -static iomux_v3_cfg_t const rgb_pads[] = {  
409 - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,  
410 - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,  
411 - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,  
412 - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,  
413 - MX6_PAD_DI0_PIN4__GPIO4_IO20,  
414 - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,  
415 - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,  
416 - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,  
417 - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,  
418 - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,  
419 - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,  
420 - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,  
421 - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,  
422 - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,  
423 - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,  
424 - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,  
425 - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,  
426 - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,  
427 - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,  
428 - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,  
429 - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,  
430 - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,  
431 - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,  
432 - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,  
433 - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,  
434 - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,  
435 - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,  
436 - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,  
437 - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,  
438 -};  
439 -  
440 -static void do_enable_hdmi(struct display_info_t const *dev)  
441 -{  
442 - imx_enable_hdmi_phy();  
443 -}  
444 -  
445 -static int detect_i2c(struct display_info_t const *dev)  
446 -{  
447 - return ((0 == i2c_set_bus_num(dev->bus))  
448 - &&  
449 - (0 == i2c_probe(dev->addr)));  
450 -}  
451 - 386 +// Dual LVDS
452 static void enable_lvds(struct display_info_t const *dev) 387 static void enable_lvds(struct display_info_t const *dev)
453 { 388 {
454 - struct iomuxc *iomux = (struct iomuxc *)  
455 - IOMUXC_BASE_ADDR; 389 + struct iomuxc *iomux = (struct iomuxc *) IOMUXC_BASE_ADDR;
456 u32 reg = readl(&iomux->gpr[2]); 390 u32 reg = readl(&iomux->gpr[2]);
457 - reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; 391 +
  392 + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
458 writel(reg, &iomux->gpr[2]); 393 writel(reg, &iomux->gpr[2]);
459 394
460 - gpio_direction_output(IMX_GPIO_NR(1, 4), 1); 395 + gpio_direction_output(IMX_GPIO_NR(6, 7), 1);
461 } 396 }
462 397
463 static void enable_lvds_jeida(struct display_info_t const *dev) 398 static void enable_lvds_jeida(struct display_info_t const *dev)
464 { 399 {
465 - struct iomuxc *iomux = (struct iomuxc *)  
466 - IOMUXC_BASE_ADDR; 400 + struct iomuxc *iomux = (struct iomuxc *) IOMUXC_BASE_ADDR;
467 u32 reg = readl(&iomux->gpr[2]); 401 u32 reg = readl(&iomux->gpr[2]);
468 - reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT  
469 - |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;  
470 - writel(reg, &iomux->gpr[2]);  
471 402
472 - gpio_direction_output(LVDS_BACKLIGHT_GP, 1);  
473 -} 403 + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA |
  404 + IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA;
  405 + writel(reg, &iomux->gpr[2]);
474 406
475 -static void enable_rgb(struct display_info_t const *dev)  
476 -{  
477 - imx_iomux_v3_setup_multiple_pads( rgb_pads, ARRAY_SIZE(rgb_pads));  
478 - gpio_direction_output(RGB_BACKLIGHT_GP, 1); 407 + gpio_direction_output(IMX_GPIO_NR(6, 7), 1);
479 } 408 }
480 409
481 -struct display_info_t const displays[] = { {  
482 - .bus = -1,  
483 - .addr = 0,  
484 - .pixfmt = IPU_PIX_FMT_RGB24,  
485 - .detect = detect_hdmi,  
486 - .enable = do_enable_hdmi,  
487 - .mode = {  
488 - .name = "HDMI",  
489 - .refresh = 60,  
490 - .xres = 1920,  
491 - .yres = 1080,  
492 - .pixclock = 15385,  
493 - .left_margin = 220,  
494 - .right_margin = 40,  
495 - .upper_margin = 21,  
496 - .lower_margin = 7,  
497 - .hsync_len = 60,  
498 - .vsync_len = 10,  
499 - .sync = FB_SYNC_EXT,  
500 - .vmode = FB_VMODE_NONINTERLACED  
501 - } }, {  
502 - .bus = 0,  
503 - .addr = 0,  
504 - .pixfmt = IPU_PIX_FMT_RGB24,  
505 - .detect = 0,  
506 - .enable = enable_rgb,  
507 - .mode = {  
508 - .name = "LDB-G156BGE",  
509 - .refresh = 60,  
510 - .xres = 1366,  
511 - .yres = 768,  
512 - .pixclock = 20831, // 1000000000 / (1366+130+60+4) * 1000 / (768+32+3+3) / 60 = 24831  
513 - .left_margin = 130, // hsync back porch  
514 - .right_margin = 60, // hsync front porch  
515 - .upper_margin = 32, // vsync back porch  
516 - .lower_margin = 3, // hsync fron porch  
517 - .hsync_len = 4,  
518 - .vsync_len = 3,  
519 - .sync = 0,  
520 - .vmode = FB_VMODE_NONINTERLACED  
521 -} } }; 410 +struct display_info_t const displays[] = {
  411 + {
  412 + .bus = -1,
  413 + .addr = 0,
  414 + .pixfmt = IPU_PIX_FMT_RGB24,
  415 + .detect = NULL,
  416 + .enable = enable_lvds,
  417 + .mode = {
  418 + .name = "LDB-LP133WD2", // 1600x900x6bit (48.87MHz)
  419 + .refresh = 60,
  420 + .xres = 1600,
  421 + .yres = 900,
  422 + .pixclock = KHZ2PICOS(108000), // ((1000000000 / (1600+44+24+24) * 1000) / (900+7+2+3)) / 60 = 10800
  423 + .left_margin = 44, // hsync back porch
  424 + .right_margin = 24, // hsync front porch
  425 + .upper_margin = 7, // vsync back porch
  426 + .lower_margin = 2, // hsync fron porch
  427 + .hsync_len = 24,
  428 + .vsync_len = 3,
  429 + .sync = 0,
  430 + .vmode = FB_VMODE_NONINTERLACED
  431 + }
  432 + }
  433 +};
522 434
523 size_t display_count = ARRAY_SIZE(displays); 435 size_t display_count = ARRAY_SIZE(displays);
524 436
@@ -536,108 +448,85 @@ static void setup_display(void) @@ -536,108 +448,85 @@ static void setup_display(void)
536 enable_ipu_clock(); 448 enable_ipu_clock();
537 imx_setup_hdmi(); 449 imx_setup_hdmi();
538 450
539 - /* Turn on LDB0,IPU,IPU DI0 clocks */  
540 - reg = __raw_readl(&mxc_ccm->CCGR3);  
541 - reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; // | MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK; 451 + /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
  452 + reg = __raw_readl(&mxc_ccm->CCGR3);
  453 + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
542 writel(reg, &mxc_ccm->CCGR3); 454 writel(reg, &mxc_ccm->CCGR3);
543 455
544 /* set LDB0, LDB1 clk select to 011/011 */ 456 /* set LDB0, LDB1 clk select to 011/011 */
545 - reg = readl(&mxc_ccm->cs2cdr);  
546 - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK  
547 - |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);  
548 - reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 457 + reg = readl(&mxc_ccm->cs2cdr);
  458 + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  459 + reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
549 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 460 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
550 writel(reg, &mxc_ccm->cs2cdr); 461 writel(reg, &mxc_ccm->cs2cdr);
551 462
552 - reg = readl(&mxc_ccm->cscmr2);  
553 - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 463 + reg = readl(&mxc_ccm->cscmr2);
  464 + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
554 writel(reg, &mxc_ccm->cscmr2); 465 writel(reg, &mxc_ccm->cscmr2);
555 466
556 - reg = readl(&mxc_ccm->chsccdr);  
557 - reg |= (CHSCCDR_CLK_SEL_LDB_DI0  
558 - <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 467 + reg = readl(&mxc_ccm->chsccdr);
  468 + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  469 + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
559 writel(reg, &mxc_ccm->chsccdr); 470 writel(reg, &mxc_ccm->chsccdr);
560 471
561 - // LVDS CH0 Enable, CH1 Disable 472 + // LVDS Ch0, Ch1 Enable
562 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 473 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
563 - | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH  
564 - | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW  
565 - | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG  
566 - | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT  
567 - | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG  
568 - | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT  
569 - | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED  
570 - | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 474 + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  475 + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  476 + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  477 + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  478 + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  479 + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  480 + |IOMUXC_GPR2_SPLIT_MODE_EN_MASK
  481 + |IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
  482 + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
571 writel(reg, &iomux->gpr[2]); 483 writel(reg, &iomux->gpr[2]);
572 484
573 reg = readl(&iomux->gpr[3]); 485 reg = readl(&iomux->gpr[3]);
574 - reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK  
575 - | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))  
576 - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0  
577 - << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);  
578 - 486 + reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  487 + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET | IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
  488 + writel(reg, &iomux->gpr[3]);
  489 +
579 /* backlights off until needed */ 490 /* backlights off until needed */
580 - imx_iomux_v3_setup_multiple_pads(backlight_pads,  
581 - ARRAY_SIZE(backlight_pads));  
582 - gpio_direction_input(LVDS_BACKLIGHT_GP);  
583 - gpio_direction_input(RGB_BACKLIGHT_GP); 491 + imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
584 } 492 }
585 #endif 493 #endif
586 494
587 495
588 static iomux_v3_cfg_t const init_pads[] = { 496 static iomux_v3_cfg_t const init_pads[] = {
589 - MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), // DEBUG_LCD1  
590 - MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), // DEBUG_LCD2 497 + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), // DEBUG_LED1
  498 + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), // DEBUG_LED2
591 499
592 - NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM), // SGTL500_sys_mclk 500 + MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB1_DRVVBUS
  501 + MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB2_DRVVBUS
593 502
594 - MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB1_DRVVBUS  
595 - MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB2_DRVVBUS  
596 - MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB4_DRVVBUS  
597 -  
598 - MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), // SDIO_WIFI_nRST  
599 - MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), // SDIO_WIFI_PDN  
600 - MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), // LCD_PWR_EN  
601 - MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), // LCD_PWM1  
602 - MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), // PCIE_RST#  
603 - MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), // PCIE_WAKE  
604 - MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), // TOUCH_INT# 503 + MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), // TOUCH_INT#
  504 +
  505 + NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM), // SGTL500_sys_mclk
605 }; 506 };
606 507
  508 +
607 #define DBG_CPU_RUN_GP IMX_GPIO_NR(1, 2) 509 #define DBG_CPU_RUN_GP IMX_GPIO_NR(1, 2)
608 #define DBG_CPU_ERROR_GP IMX_GPIO_NR(1, 4) 510 #define DBG_CPU_ERROR_GP IMX_GPIO_NR(1, 4)
609 -#define SDIO_WIFI_RESET_GP IMX_GPIO_NR(6, 7)  
610 -#define SDIO_WIFI_PDN_GP IMX_GPIO_NR(6, 8)  
611 -#define PCIE_RESET_GP IMX_GPIO_NR(6, 11)  
612 -#define USB_CH1_PWN_EN_GP IMX_GPIO_NR(2, 0)  
613 -#define USB_CH2_PWN_EN_GP IMX_GPIO_NR(2, 1)  
614 -#define USB_CH4_PWN_EN_GP IMX_GPIO_NR(2, 2) 511 +#define USB_CH1_PWR_EN_GP IMX_GPIO_NR(2, 0)
  512 +#define USB_CH2_PWR_EN_GP IMX_GPIO_NR(2, 1)
615 513
616 static void setup_gpio(void) 514 static void setup_gpio(void)
617 { 515 {
618 - gpio_direction_output(DBG_CPU_RUN_GP, 1); 516 + // DEBUG LED1, LED2
  517 + gpio_direction_output(DBG_CPU_RUN_GP, 1);
619 gpio_direction_output(DBG_CPU_ERROR_GP, 0); 518 gpio_direction_output(DBG_CPU_ERROR_GP, 0);
620 udelay(200000); 519 udelay(200000);
621 gpio_set_value(DBG_CPU_RUN_GP, 0); 520 gpio_set_value(DBG_CPU_RUN_GP, 0);
622 gpio_set_value(DBG_CPU_ERROR_GP, 1); 521 gpio_set_value(DBG_CPU_ERROR_GP, 1);
623 udelay(20000); 522 udelay(20000);
624 -  
625 - gpio_direction_output(SDIO_WIFI_RESET_GP, 0);  
626 - gpio_direction_output(SDIO_WIFI_PDN_GP, 0);  
627 - gpio_direction_output(PCIE_RESET_GP, 0);  
628 - udelay(50000);  
629 - gpio_set_value(SDIO_WIFI_RESET_GP, 1);  
630 - gpio_set_value(SDIO_WIFI_PDN_GP, 1);  
631 - gpio_set_value(PCIE_RESET_GP, 1);  
632 - udelay(20000);  
633 523
634 - gpio_direction_output(USB_CH1_PWN_EN_GP, 0);  
635 - gpio_direction_output(USB_CH2_PWN_EN_GP, 0);  
636 - gpio_direction_output(USB_CH4_PWN_EN_GP, 0); 524 + // USB Power Control
  525 + gpio_direction_output(USB_CH1_PWR_EN_GP, 0);
  526 + gpio_direction_output(USB_CH2_PWR_EN_GP, 0);
637 udelay(50000); 527 udelay(50000);
638 - gpio_set_value(USB_CH1_PWN_EN_GP, 1);  
639 - gpio_set_value(USB_CH2_PWN_EN_GP, 1);  
640 - gpio_set_value(USB_CH4_PWN_EN_GP, 1); 528 + gpio_set_value(USB_CH1_PWR_EN_GP, 1);
  529 + gpio_set_value(USB_CH2_PWR_EN_GP, 1);
641 } 530 }
642 531
643 int board_early_init_f(void) 532 int board_early_init_f(void)
@@ -646,7 +535,6 @@ int board_early_init_f(void) @@ -646,7 +535,6 @@ int board_early_init_f(void)
646 535
647 imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads)); 536 imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
648 537
649 -  
650 #if defined(CONFIG_VIDEO_IPUV3) 538 #if defined(CONFIG_VIDEO_IPUV3)
651 setup_display(); 539 setup_display();
652 #endif 540 #endif
@@ -666,9 +554,7 @@ int board_init(void) @@ -666,9 +554,7 @@ int board_init(void)
666 { 554 {
667 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 555 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
668 556
669 - clrsetbits_le32(&iomuxc_regs->gpr[1],  
670 - IOMUXC_GPR1_OTG_ID_MASK,  
671 - IOMUXC_GPR1_OTG_ID_GPIO1); 557 + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_OTG_ID_MASK, IOMUXC_GPR1_OTG_ID_GPIO1);
672 558
673 /* address of boot parameters */ 559 /* address of boot parameters */
674 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 560 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
@@ -676,16 +562,11 @@ int board_init(void) @@ -676,16 +562,11 @@ int board_init(void)
676 #ifdef CONFIG_MXC_SPI 562 #ifdef CONFIG_MXC_SPI
677 setup_spi(); 563 setup_spi();
678 #endif 564 #endif
  565 +
679 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 566 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
680 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 567 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
681 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 568 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
682 569
683 -#ifdef CONFIG_CMD_SATA  
684 - setup_sata();  
685 -#endif  
686 -  
687 -  
688 -  
689 return 0; 570 return 0;
690 } 571 }
691 572
@@ -708,7 +589,7 @@ static const struct boot_mode board_boot_modes[] = { @@ -708,7 +589,7 @@ static const struct boot_mode board_boot_modes[] = {
708 589
709 int misc_init_r(void) 590 int misc_init_r(void)
710 { 591 {
711 -// [FALINUX] 592 + // [FALINUX]
712 setup_gpio(); 593 setup_gpio();
713 594
714 #ifdef CONFIG_CMD_BMODE 595 #ifdef CONFIG_CMD_BMODE
bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/mx6s_prime_oven1g.cfg 100644 → 100755
  Diff comments   View file @e5a0c50
File mode changed
bootloader/u-boot_2015_04/include/configs/mx6s_prime_oven.h
  Diff comments   View file @e5a0c50
@@ -47,17 +47,18 @@ @@ -47,17 +47,18 @@
47 #endif 47 #endif
48 48
49 #define CONFIG_MXC_UART 49 #define CONFIG_MXC_UART
50 -#define CONFIG_MXC_UART_BASE UART1_BASE 50 +#define CONFIG_MXC_UART_BASE UART1_BASE
  51 +
51 52
52 #define CONFIG_CMD_SF 53 #define CONFIG_CMD_SF
53 #ifdef CONFIG_CMD_SF 54 #ifdef CONFIG_CMD_SF
54 #define CONFIG_SPI_FLASH 55 #define CONFIG_SPI_FLASH
55 #define CONFIG_SPI_FLASH_SST 56 #define CONFIG_SPI_FLASH_SST
56 #define CONFIG_MXC_SPI 57 #define CONFIG_MXC_SPI
57 -#define CONFIG_SF_DEFAULT_BUS 0  
58 -#define CONFIG_SF_DEFAULT_CS 0  
59 -#define CONFIG_SF_DEFAULT_SPEED 25000000  
60 -#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 58 +#define CONFIG_SF_DEFAULT_BUS 0
  59 +#define CONFIG_SF_DEFAULT_CS 1
  60 +#define CONFIG_SF_DEFAULT_SPEED 25000000
  61 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
61 #endif 62 #endif
62 63
63 /* I2C Configs */ 64 /* I2C Configs */
@@ -70,8 +71,8 @@ @@ -70,8 +71,8 @@
70 /* MMC Configs */ 71 /* MMC Configs */
71 #define CONFIG_FSL_ESDHC 72 #define CONFIG_FSL_ESDHC
72 #define CONFIG_FSL_USDHC 73 #define CONFIG_FSL_USDHC
73 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0  
74 -#define CONFIG_SYS_FSL_USDHC_NUM 2 74 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
  75 +#define CONFIG_SYS_FSL_USDHC_NUM 2
75 76
76 #define CONFIG_MMC 77 #define CONFIG_MMC
77 #define CONFIG_CMD_MMC 78 #define CONFIG_CMD_MMC
@@ -83,22 +84,6 @@ @@ -83,22 +84,6 @@
83 #define CONFIG_CMD_FAT 84 #define CONFIG_CMD_FAT
84 #define CONFIG_DOS_PARTITION 85 #define CONFIG_DOS_PARTITION
85 86
86 -#ifdef CONFIG_MX6Q  
87 -#define CONFIG_CMD_SATA  
88 -#endif  
89 -  
90 -/*  
91 - * SATA Configs  
92 - */  
93 -#ifdef CONFIG_CMD_SATA  
94 -#define CONFIG_DWC_AHSATA  
95 -#define CONFIG_SYS_SATA_MAX_DEVICE 1  
96 -#define CONFIG_DWC_AHSATA_PORT_ID 0  
97 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR  
98 -#define CONFIG_LBA48  
99 -#define CONFIG_LIBATA  
100 -#endif  
101 -  
102 #define CONFIG_CMD_PING 87 #define CONFIG_CMD_PING
103 #define CONFIG_CMD_DHCP 88 #define CONFIG_CMD_DHCP
104 #define CONFIG_CMD_MII 89 #define CONFIG_CMD_MII
@@ -120,8 +105,8 @@ @@ -120,8 +105,8 @@
120 #define CONFIG_USB_STORAGE 105 #define CONFIG_USB_STORAGE
121 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 106 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
122 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 107 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
123 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)  
124 -#define CONFIG_MXC_USB_FLAGS 0 108 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  109 +#define CONFIG_MXC_USB_FLAGS 0
125 #define CONFIG_USB_KEYBOARD 110 #define CONFIG_USB_KEYBOARD
126 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP 111 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
127 112
@@ -146,42 +131,42 @@ @@ -146,42 +131,42 @@
146 131
147 #define CONFIG_VIDEO_LOGO 132 #define CONFIG_VIDEO_LOGO
148 #define CONFIG_VIDEO_BMP_LOGO 133 #define CONFIG_VIDEO_BMP_LOGO
149 -#define CONFIG_IPUV3_CLK 260000000 134 +#define CONFIG_IPUV3_CLK 260000000
150 #define CONFIG_IMX_HDMI 135 #define CONFIG_IMX_HDMI
151 #define CONFIG_IMX_VIDEO_SKIP 136 #define CONFIG_IMX_VIDEO_SKIP
152 #endif 137 #endif
153 138
154 /* allow to overwrite serial and ethaddr */ 139 /* allow to overwrite serial and ethaddr */
155 #define CONFIG_ENV_OVERWRITE 140 #define CONFIG_ENV_OVERWRITE
156 -#define CONFIG_CONS_INDEX 1  
157 -#define CONFIG_BAUDRATE 115200 141 +#define CONFIG_CONS_INDEX 1
  142 +#define CONFIG_BAUDRATE 115200
158 143
159 /* Command definition */ 144 /* Command definition */
160 #include <config_cmd_default.h> 145 #include <config_cmd_default.h>
161 146
162 #undef CONFIG_CMD_IMLS 147 #undef CONFIG_CMD_IMLS
163 148
164 -#define CONFIG_BOOTDELAY 1 149 +#define CONFIG_BOOTDELAY 1
165 150
166 -#define CONFIG_PREBOOT "" 151 +#define CONFIG_PREBOOT ""
167 152
168 -#define CONFIG_LOADADDR 0x12000000  
169 -#define CONFIG_SYS_TEXT_BASE 0x17800000 153 +#define CONFIG_LOADADDR 0x12000000
  154 +#define CONFIG_SYS_TEXT_BASE 0x17800000
170 155
171 #ifdef CONFIG_CMD_SATA 156 #ifdef CONFIG_CMD_SATA
172 -#define CONFIG_DRIVE_SATA "sata " 157 +#define CONFIG_DRIVE_SATA "sata "
173 #else 158 #else
174 #define CONFIG_DRIVE_SATA 159 #define CONFIG_DRIVE_SATA
175 #endif 160 #endif
176 161
177 #ifdef CONFIG_CMD_MMC 162 #ifdef CONFIG_CMD_MMC
178 -#define CONFIG_DRIVE_MMC "mmc " 163 +#define CONFIG_DRIVE_MMC "mmc "
179 #else 164 #else
180 #define CONFIG_DRIVE_MMC 165 #define CONFIG_DRIVE_MMC
181 #endif 166 #endif
182 167
183 #ifdef CONFIG_USB_STORAGE 168 #ifdef CONFIG_USB_STORAGE
184 -#define CONFIG_DRIVE_USB "usb " 169 +#define CONFIG_DRIVE_USB "usb "
185 #else 170 #else
186 #define CONFIG_DRIVE_USB 171 #define CONFIG_DRIVE_USB
187 #endif 172 #endif
@@ -191,15 +176,16 @@ @@ -191,15 +176,16 @@
191 176
192 /* mmcdev=0 : eMMC mmcdev=1 : SD/MMC Card */ 177 /* mmcdev=0 : eMMC mmcdev=1 : SD/MMC Card */
193 #define CONFIG_EXTRA_ENV_SETTINGS \ 178 #define CONFIG_EXTRA_ENV_SETTINGS \
  179 + "autoexec=/app/service/run.sh\0" \
194 "console=ttymxc0\0" \ 180 "console=ttymxc0\0" \
195 "fdt_high=0xffffffff\0" \ 181 "fdt_high=0xffffffff\0" \
196 "initrd_high=0xffffffff\0" \ 182 "initrd_high=0xffffffff\0" \
197 "loadaddr=0x12000000\0" \ 183 "loadaddr=0x12000000\0" \
198 "boot_fdt=try\0" \ 184 "boot_fdt=try\0" \
199 "bootdelay=1\0" \ 185 "bootdelay=1\0" \
200 - "bootargs=console=ttymxc0,115200 root=/dev/ram0 rw --no-log initrd=0x1E000000,32M ramdisk=65536 video=${video_lvds} ${video_hdmi} ${video_vmalloc} ${arg_option}\0" \  
201 - "bootargs_ram=setenv bootargs console=ttymxc0,115200 root=/dev/ram0 rw --no-log initrd=0x1E000000,32M ramdisk=65536 ${video_lvds} ${video_hdmi} ${video_vmalloc} ${arg_option} \0" \  
202 - "bootargs_mmc=setenv bootargs console=ttymxc0,115200 root=/dev/mmcblk3p2 rw --no-log rootfstype=ext4 rootdelay=5 rootwait ${video_lvds} ${video_hdmi} ${video_vmalloc} ${arg_option}\0" \ 186 + "bootargs=console=ttymxc0,115200 root=/dev/ram0 rw --no-log initrd=0x1E000000,32M ramdisk=65536 video=${video_lvds} ${video_vmalloc} ${arg_option} autosh=${autoexec}\0" \
  187 + "bootargs_ram=setenv bootargs console=ttymxc0,115200 root=/dev/ram0 rw --no-log initrd=0x1E000000,32M ramdisk=65536 ${video_lvds} ${video_vmalloc} ${arg_option} autosh=${autoexec}\0" \
  188 + "bootargs_mmc=setenv bootargs console=ttymxc0,115200 root=/dev/mmcblk3p2 rw --no-log rootfstype=ext4 rootdelay=5 rootwait ${video_lvds} ${video_vmalloc} ${arg_option} autosh=${autoexec}\0" \
203 "ethaddr=00:FA:15:12:02:02\0" \ 189 "ethaddr=00:FA:15:12:02:02\0" \
204 "eth1addr=00:FA:15:12:02:04\0" \ 190 "eth1addr=00:FA:15:12:02:04\0" \
205 "serverip=192.168.10.131\0" \ 191 "serverip=192.168.10.131\0" \
@@ -207,19 +193,19 @@ @@ -207,19 +193,19 @@
207 "netmask=255.255.0.0\0" \ 193 "netmask=255.255.0.0\0" \
208 "gatewayip=192.168.10.1\0" \ 194 "gatewayip=192.168.10.1\0" \
209 "ip_dyn=yes\0" \ 195 "ip_dyn=yes\0" \
210 - "video_lvds=video=mxcfb0:dev=ldb,LDB-G156BGE,if=RGB24\0" \  
211 - "video_hdmi=video=mxcfb1:dev=hdmi,1920x1080@60,if=RGB24\0" \  
212 - "video_vmalloc=fbmem=28M,28M fbcon=28M,28M vmalloc=400M\0" \  
213 - "arg_option=fec.disable_giga=1\0" \ 196 + "video_lvds=video=mxcfb0:dev=ldb,LDB-LP133WD2,if=RGB24 ldb=spl0\0" \
  197 + "video_vmalloc=fbmem=192M vmalloc=400M\0" \
  198 + "arg_option=loglevel=7\0" \
214 "mmcdev=0\0" \ 199 "mmcdev=0\0" \
215 - "uboot_file=u-boot.imx6_cmf\0" \  
216 - "dtb_file=imx6dl-cmf.dtb\0" \  
217 - "kernel_file=uImage.imx6_cmf\0" \  
218 - "ramdisk_file=ramdisk.imx6_cmf-2.0-64M.gz\0" \  
219 - "uboot=tftpboot 0x12000000 ${uboot_file}; mmc dev ${mmcdev}; mmc write 0x12000000 2 500; if ext4ls mmc ${mmcdev}:1 boot; then ext4writ mmc ${mmcdev}:1 0x12000000 /boot/${uboot_file} ${filesize}; fi;\0" \  
220 - "kernel=tftpboot 0x12000000 ${kernel_file}; mmc dev ${mmcdev}; mmc write 0x12000000 1000 4000; if ext4ls mmc ${mmcdev}:1 boot; then ext4write mmc ${mmcdev}:1 0x12000000 /boot/${kernel_file} ${filesize}; fi;\0" \  
221 - "dtb=tftpboot 0x11F00000 ${dtb_file}; mmc dev ${mmcdev}; mmc write 0x11F00000 A00 100; if ext4ls mmc ${mmcdev}:1 boot; then ext4write mmc ${mmcdev}:1 0x11F00000 /boot/${dtb_file} ${filesize}; fi;\0" \  
222 - "ramdisk=tftpboot 0x1E000000 ${ramdisk_file}; mmc dev ${mmcdev}; mmc write 0x1E000000 7000 10000; if ext4ls mmc ${mmcdev}:1 boot; then ext4write mmc ${mmcdev}:1 0x1E000000 /boot/${ramdisk_file} ${filesize}; fi;\0" \ 200 + "tftpbase=prime-oven\0" \
  201 + "uboot_file=u-boot.imx\0" \
  202 + "dtb_file=imx6sl-prime-oven.dtb\0" \
  203 + "kernel_file=uImage\0" \
  204 + "ramdisk_file=ramdisk.imx6-2.0-64M.gz\0" \
  205 + "uboot=tftpboot 0x12000000 ${tftpbase}/${uboot_file}; mmc dev ${mmcdev}; mmc write 0x12000000 2 500; if ext4ls mmc ${mmcdev}:1 boot; then ext4writ mmc ${mmcdev}:1 0x12000000 /boot/${uboot_file} ${filesize}; fi;\0" \
  206 + "kernel=tftpboot 0x12000000 ${tftpbase}/${kernel_file}; mmc dev ${mmcdev}; mmc write 0x12000000 1000 4000; if ext4ls mmc ${mmcdev}:1 boot; then ext4write mmc ${mmcdev}:1 0x12000000 /boot/${kernel_file} ${filesize}; fi;\0" \
  207 + "dtb=tftpboot 0x11F00000 ${tftpbase}/${dtb_file}; mmc dev ${mmcdev}; mmc write 0x11F00000 A00 100; if ext4ls mmc ${mmcdev}:1 boot; then ext4write mmc ${mmcdev}:1 0x11F00000 /boot/${dtb_file} ${filesize}; fi;\0" \
  208 + "ramdisk=tftpboot 0x1E000000 ${tftpbase}/${ramdisk_file}; mmc dev ${mmcdev}; mmc write 0x1E000000 7000 10000; if ext4ls mmc ${mmcdev}:1 boot; then ext4write mmc ${mmcdev}:1 0x1E000000 /boot/${ramdisk_file} ${filesize}; fi;\0" \
223 "bootram=mmc dev ${mmcdev}; mmcinfo; mmc read 0x11F00000 A00 100; mmc read 0x12000000 1000 4000; mmc read 0x1E000000 7000 10000; bootm 0x12000000 - 0x11F00000\0" \ 209 "bootram=mmc dev ${mmcdev}; mmcinfo; mmc read 0x11F00000 A00 100; mmc read 0x12000000 1000 4000; mmc read 0x1E000000 7000 10000; bootm 0x12000000 - 0x11F00000\0" \
224 "bootload= echo ; echo Loading a bootable image ...; mmc dev ${mmcdev}; " \ 210 "bootload= echo ; echo Loading a bootable image ...; mmc dev ${mmcdev}; " \
225 "if ext4load mmc ${mmcdev}:1 0x11F00000 /boot/${dtb_file}; then " \ 211 "if ext4load mmc ${mmcdev}:1 0x11F00000 /boot/${dtb_file}; then " \
@@ -253,7 +239,7 @@ @@ -253,7 +239,7 @@
253 /* Miscellaneous configurable options */ 239 /* Miscellaneous configurable options */
254 #define CONFIG_SYS_LONGHELP 240 #define CONFIG_SYS_LONGHELP
255 #define CONFIG_SYS_HUSH_PARSER 241 #define CONFIG_SYS_HUSH_PARSER
256 -#define CONFIG_SYS_PROMPT "CELL v1 > " 242 +#define CONFIG_SYS_PROMPT "prime > "
257 #define CONFIG_AUTO_COMPLETE 243 #define CONFIG_AUTO_COMPLETE
258 #define CONFIG_SYS_CBSIZE 1024 244 #define CONFIG_SYS_CBSIZE 1024
259 #define CONFIG_SYS_MAXARGS 48 245 #define CONFIG_SYS_MAXARGS 48
@@ -275,10 +261,8 @@ @@ -275,10 +261,8 @@
275 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 261 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
276 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 262 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
277 263
278 -#define CONFIG_SYS_INIT_SP_OFFSET \  
279 - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)  
280 -#define CONFIG_SYS_INIT_SP_ADDR \  
281 - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 264 +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  265 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
282 266
283 /* FLASH and environment organization */ 267 /* FLASH and environment organization */
284 #define CONFIG_SYS_NO_FLASH 268 #define CONFIG_SYS_NO_FLASH
@@ -288,15 +272,8 @@ @@ -288,15 +272,8 @@
288 #define CONFIG_ENV_IS_IN_MMC 272 #define CONFIG_ENV_IS_IN_MMC
289 273
290 #if defined(CONFIG_ENV_IS_IN_MMC) 274 #if defined(CONFIG_ENV_IS_IN_MMC)
291 -#define CONFIG_ENV_OFFSET (768 * 1024)  
292 -#define CONFIG_SYS_MMC_ENV_DEV 0  
293 -#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)  
294 -#define CONFIG_ENV_OFFSET (768 * 1024)  
295 -#define CONFIG_ENV_SECT_SIZE (8 * 1024)  
296 -#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS  
297 -#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS  
298 -#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE  
299 -#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 275 +#define CONFIG_ENV_OFFSET (768 * 1024)
  276 +#define CONFIG_SYS_MMC_ENV_DEV 0
300 #endif 277 #endif
301 278
302 #define CONFIG_OF_LIBFDT 279 #define CONFIG_OF_LIBFDT
@@ -344,7 +321,7 @@ @@ -344,7 +321,7 @@
344 321
345 #define CONFIG_CMD_FASTBOOT 322 #define CONFIG_CMD_FASTBOOT
346 #define CONFIG_ANDROID_BOOT_IMAGE 323 #define CONFIG_ANDROID_BOOT_IMAGE
347 -#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR  
348 -#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 324 +#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
  325 +#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000
349 326
350 #endif /* __CONFIG_PRIME_OVEN_H */ 327 #endif /* __CONFIG_PRIME_OVEN_H */