diff --git a/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/800mhz_2x256mx16.cfg b/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/800mhz_2x256mx16.cfg old mode 100644 new mode 100755 diff --git a/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/Kconfig b/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/Kconfig old mode 100644 new mode 100755 diff --git a/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/Makefile b/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/Makefile old mode 100644 new mode 100755 diff --git a/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/clocks.cfg b/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/clocks.cfg old mode 100644 new mode 100755 index 64056e3..9ad21e4 --- a/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/clocks.cfg +++ b/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/clocks.cfg @@ -19,7 +19,7 @@ DATA 4, CCM_CCGR0, 0x00C03F3F DATA 4, CCM_CCGR1, 0x0030FC03 DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR3, 0x3FF0F000 DATA 4, CCM_CCGR4, 0x00FFF300 DATA 4, CCM_CCGR5, 0x0FFC00C3 DATA 4, CCM_CCGR6, 0x000003FF diff --git a/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/ddr-setup.cfg b/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/ddr-setup.cfg old mode 100644 new mode 100755 diff --git a/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/mx6s_prime_oven.c b/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/mx6s_prime_oven.c old mode 100644 new mode 100755 index b3bdd3c..d630a67 --- a/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/mx6s_prime_oven.c +++ b/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/mx6s_prime_oven.c @@ -36,65 +36,61 @@ DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) -#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) -#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_SRE_SLOW) - -#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_HYS | PAD_CTL_SRE_SLOW) - -#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) int dram_init(void) { gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); - return 0; } +// Console static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; +// TTL232 static iomux_v3_cfg_t const uart2_pads[] = { MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -static iomux_v3_cfg_t const uart23_pads[] = { +// RS485 Ch1 +static iomux_v3_cfg_t const uart3_pads[] = { MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D30__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +// RS485 Ch2 +static iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 SGTL5000, Ext-I2C#0 */ +/* I2C1 : SGTL5000 */ static struct i2c_pads_info i2c_pad_info0 = { .scl = { .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, @@ -108,7 +104,7 @@ static struct i2c_pads_info i2c_pad_info0 = { } }; -/* I2C2 PMCI, DS1339(RTC), Mac address, touch, HDMI */ +/* I2C2 : PMCI, DS1339(RTC), Mac address, touch */ static struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, @@ -122,7 +118,7 @@ static struct i2c_pads_info i2c_pad_info1 = { } }; -/* I2C3 Ext-I2C#1 */ +/* I2C3 : Reserved */ static struct i2c_pads_info i2c_pad_info2 = { .scl = { .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, @@ -133,20 +129,9 @@ static struct i2c_pads_info i2c_pad_info2 = { .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, .gp = IMX_GPIO_NR(1, 6) - } + } }; -// Wifi -static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__GPIO6_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ - MX6_PAD_SD3_DAT6__GPIO6_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ -}; // Micro-SD static iomux_v3_cfg_t const usdhc3_pads[] = { @@ -176,15 +161,41 @@ static iomux_v3_cfg_t const usdhc4_pads[] = { static iomux_v3_cfg_t const usb_pads[] = { MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB1_DRVVBUS MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB2_DRVVBUS - MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB4_DRVVBUS }; static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); +} + +#ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + switch (bus){ + case 0 : + if(cs == 1) return IMX_GPIO_NR(3, 19); + else return -1; + default : return -1; + } } +static iomux_v3_cfg_t const ecspi1_pads[] = { + /* SPI1 */ + MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* SS1 */ + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), /* MISO */ + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), /* MOSI */ + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), /* SLCK */ +}; + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); +} +#endif + #ifdef CONFIG_USB_EHCI_MX6 int board_ehci_hcd_init(int port) { @@ -193,11 +204,9 @@ int board_ehci_hcd_init(int port) /* Reset USB Power */ gpio_direction_output(IMX_GPIO_NR(2, 0), 0); gpio_direction_output(IMX_GPIO_NR(2, 1), 0); - gpio_direction_output(IMX_GPIO_NR(2, 2), 0); mdelay(2); gpio_set_value(IMX_GPIO_NR(2, 0), 1); gpio_set_value(IMX_GPIO_NR(2, 1), 1); - gpio_set_value(IMX_GPIO_NR(2, 2), 1); return 0; } @@ -268,53 +277,25 @@ int board_mmc_init(bd_t *bis) } #endif -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1; -} - -static iomux_v3_cfg_t const ecspi1_pads[] = { - /* SS1 */ - MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const ecspi2_pads[] = { - /* SS1 */ - MX6_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_spi(void) -{ - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); - imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); -} -#endif static iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), /* AR8031 PHY Reset */ - MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void setup_iomux_enet(void) @@ -396,129 +377,60 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_VIDEO_IPUV3) static iomux_v3_cfg_t const backlight_pads[] = { - /* Backlight on RGB connector: J15 */ - MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), -#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) - - /* Backlight on LVDS connector: J6 */ - MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), -#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) + /* Backlight power enable */ + MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), // LCD_PWR_EN + /* Backlight brightness */ + MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), // LCD_PWM1 }; -static iomux_v3_cfg_t const rgb_pads[] = { - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, - MX6_PAD_DI0_PIN4__GPIO4_IO20, - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, -}; - -static void do_enable_hdmi(struct display_info_t const *dev) -{ - imx_enable_hdmi_phy(); -} - -static int detect_i2c(struct display_info_t const *dev) -{ - return ((0 == i2c_set_bus_num(dev->bus)) - && - (0 == i2c_probe(dev->addr))); -} - +// Dual LVDS static void enable_lvds(struct display_info_t const *dev) { - struct iomuxc *iomux = (struct iomuxc *) - IOMUXC_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *) IOMUXC_BASE_ADDR; u32 reg = readl(&iomux->gpr[2]); - reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; writel(reg, &iomux->gpr[2]); - gpio_direction_output(IMX_GPIO_NR(1, 4), 1); + gpio_direction_output(IMX_GPIO_NR(6, 7), 1); } static void enable_lvds_jeida(struct display_info_t const *dev) { - struct iomuxc *iomux = (struct iomuxc *) - IOMUXC_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *) IOMUXC_BASE_ADDR; u32 reg = readl(&iomux->gpr[2]); - reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT - |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA; - writel(reg, &iomux->gpr[2]); - gpio_direction_output(LVDS_BACKLIGHT_GP, 1); -} + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA | + IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA; + writel(reg, &iomux->gpr[2]); -static void enable_rgb(struct display_info_t const *dev) -{ - imx_iomux_v3_setup_multiple_pads( rgb_pads, ARRAY_SIZE(rgb_pads)); - gpio_direction_output(RGB_BACKLIGHT_GP, 1); + gpio_direction_output(IMX_GPIO_NR(6, 7), 1); } -struct display_info_t const displays[] = { { - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = do_enable_hdmi, - .mode = { - .name = "HDMI", - .refresh = 60, - .xres = 1920, - .yres = 1080, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED - } }, { - .bus = 0, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = 0, - .enable = enable_rgb, - .mode = { - .name = "LDB-G156BGE", - .refresh = 60, - .xres = 1366, - .yres = 768, - .pixclock = 20831, // 1000000000 / (1366+130+60+4) * 1000 / (768+32+3+3) / 60 = 24831 - .left_margin = 130, // hsync back porch - .right_margin = 60, // hsync front porch - .upper_margin = 32, // vsync back porch - .lower_margin = 3, // hsync fron porch - .hsync_len = 4, - .vsync_len = 3, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED -} } }; +struct display_info_t const displays[] = { + { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "LDB-LP133WD2", // 1600x900x6bit (48.87MHz) + .refresh = 60, + .xres = 1600, + .yres = 900, + .pixclock = KHZ2PICOS(108000), // ((1000000000 / (1600+44+24+24) * 1000) / (900+7+2+3)) / 60 = 10800 + .left_margin = 44, // hsync back porch + .right_margin = 24, // hsync front porch + .upper_margin = 7, // vsync back porch + .lower_margin = 2, // hsync fron porch + .hsync_len = 24, + .vsync_len = 3, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED + } + } +}; size_t display_count = ARRAY_SIZE(displays); @@ -536,108 +448,85 @@ static void setup_display(void) enable_ipu_clock(); imx_setup_hdmi(); - /* Turn on LDB0,IPU,IPU DI0 clocks */ - reg = __raw_readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; // | MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK; + /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; writel(reg, &mxc_ccm->CCGR3); /* set LDB0, LDB1 clk select to 011/011 */ - reg = readl(&mxc_ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK - |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - reg |= (3<cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3<cs2cdr); - reg = readl(&mxc_ccm->cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; writel(reg, &mxc_ccm->cscmr2); - reg = readl(&mxc_ccm->chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - <chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); writel(reg, &mxc_ccm->chsccdr); - // LVDS CH0 Enable, CH1 Disable + // LVDS Ch0, Ch1 Enable reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES - | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH - | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW - | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG - | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT - | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG - | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT - | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED - | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_SPLIT_MODE_EN_MASK + |IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; writel(reg, &iomux->gpr[2]); reg = readl(&iomux->gpr[3]); - reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK - | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 - << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); - + reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET | IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); + /* backlights off until needed */ - imx_iomux_v3_setup_multiple_pads(backlight_pads, - ARRAY_SIZE(backlight_pads)); - gpio_direction_input(LVDS_BACKLIGHT_GP); - gpio_direction_input(RGB_BACKLIGHT_GP); + imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); } #endif static iomux_v3_cfg_t const init_pads[] = { - MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), // DEBUG_LCD1 - MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), // DEBUG_LCD2 + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), // DEBUG_LED1 + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), // DEBUG_LED2 - NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM), // SGTL500_sys_mclk + MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB1_DRVVBUS + MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB2_DRVVBUS - MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB1_DRVVBUS - MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB2_DRVVBUS - MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), // USB4_DRVVBUS - - MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), // SDIO_WIFI_nRST - MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), // SDIO_WIFI_PDN - MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), // LCD_PWR_EN - MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), // LCD_PWM1 - MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), // PCIE_RST# - MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), // PCIE_WAKE - MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), // TOUCH_INT# + MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), // TOUCH_INT# + + NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM), // SGTL500_sys_mclk }; + #define DBG_CPU_RUN_GP IMX_GPIO_NR(1, 2) #define DBG_CPU_ERROR_GP IMX_GPIO_NR(1, 4) -#define SDIO_WIFI_RESET_GP IMX_GPIO_NR(6, 7) -#define SDIO_WIFI_PDN_GP IMX_GPIO_NR(6, 8) -#define PCIE_RESET_GP IMX_GPIO_NR(6, 11) -#define USB_CH1_PWN_EN_GP IMX_GPIO_NR(2, 0) -#define USB_CH2_PWN_EN_GP IMX_GPIO_NR(2, 1) -#define USB_CH4_PWN_EN_GP IMX_GPIO_NR(2, 2) +#define USB_CH1_PWR_EN_GP IMX_GPIO_NR(2, 0) +#define USB_CH2_PWR_EN_GP IMX_GPIO_NR(2, 1) static void setup_gpio(void) { - gpio_direction_output(DBG_CPU_RUN_GP, 1); + // DEBUG LED1, LED2 + gpio_direction_output(DBG_CPU_RUN_GP, 1); gpio_direction_output(DBG_CPU_ERROR_GP, 0); udelay(200000); gpio_set_value(DBG_CPU_RUN_GP, 0); gpio_set_value(DBG_CPU_ERROR_GP, 1); udelay(20000); - - gpio_direction_output(SDIO_WIFI_RESET_GP, 0); - gpio_direction_output(SDIO_WIFI_PDN_GP, 0); - gpio_direction_output(PCIE_RESET_GP, 0); - udelay(50000); - gpio_set_value(SDIO_WIFI_RESET_GP, 1); - gpio_set_value(SDIO_WIFI_PDN_GP, 1); - gpio_set_value(PCIE_RESET_GP, 1); - udelay(20000); - gpio_direction_output(USB_CH1_PWN_EN_GP, 0); - gpio_direction_output(USB_CH2_PWN_EN_GP, 0); - gpio_direction_output(USB_CH4_PWN_EN_GP, 0); + // USB Power Control + gpio_direction_output(USB_CH1_PWR_EN_GP, 0); + gpio_direction_output(USB_CH2_PWR_EN_GP, 0); udelay(50000); - gpio_set_value(USB_CH1_PWN_EN_GP, 1); - gpio_set_value(USB_CH2_PWN_EN_GP, 1); - gpio_set_value(USB_CH4_PWN_EN_GP, 1); + gpio_set_value(USB_CH1_PWR_EN_GP, 1); + gpio_set_value(USB_CH2_PWR_EN_GP, 1); } int board_early_init_f(void) @@ -646,7 +535,6 @@ int board_early_init_f(void) imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads)); - #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif @@ -666,9 +554,7 @@ int board_init(void) { struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - clrsetbits_le32(&iomuxc_regs->gpr[1], - IOMUXC_GPR1_OTG_ID_MASK, - IOMUXC_GPR1_OTG_ID_GPIO1); + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_OTG_ID_MASK, IOMUXC_GPR1_OTG_ID_GPIO1); /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; @@ -676,16 +562,11 @@ int board_init(void) #ifdef CONFIG_MXC_SPI setup_spi(); #endif + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); -#ifdef CONFIG_CMD_SATA - setup_sata(); -#endif - - - return 0; } @@ -708,7 +589,7 @@ static const struct boot_mode board_boot_modes[] = { int misc_init_r(void) { -// [FALINUX] + // [FALINUX] setup_gpio(); #ifdef CONFIG_CMD_BMODE diff --git a/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/mx6s_prime_oven1g.cfg b/bootloader/u-boot_2015_04/board/falinux/mx6s_prime_oven/mx6s_prime_oven1g.cfg old mode 100644 new mode 100755 diff --git a/bootloader/u-boot_2015_04/include/configs/mx6s_prime_oven.h b/bootloader/u-boot_2015_04/include/configs/mx6s_prime_oven.h old mode 100644 new mode 100755 index 3f0460c..96fad82 --- a/bootloader/u-boot_2015_04/include/configs/mx6s_prime_oven.h +++ b/bootloader/u-boot_2015_04/include/configs/mx6s_prime_oven.h @@ -47,17 +47,18 @@ #endif #define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_MXC_UART_BASE UART1_BASE + #define CONFIG_CMD_SF #ifdef CONFIG_CMD_SF #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_SST #define CONFIG_MXC_SPI -#define CONFIG_SF_DEFAULT_BUS 0 -#define CONFIG_SF_DEFAULT_CS 0 -#define CONFIG_SF_DEFAULT_SPEED 25000000 -#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 1 +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) #endif /* I2C Configs */ @@ -70,8 +71,8 @@ /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_MMC #define CONFIG_CMD_MMC @@ -83,22 +84,6 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION -#ifdef CONFIG_MX6Q -#define CONFIG_CMD_SATA -#endif - -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#define CONFIG_LIBATA -#endif - #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII @@ -120,8 +105,8 @@ #define CONFIG_USB_STORAGE #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_KEYBOARD #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP @@ -146,42 +131,42 @@ #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_IPUV3_CLK 260000000 #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP #endif /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 /* Command definition */ #include #undef CONFIG_CMD_IMLS -#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTDELAY 1 -#define CONFIG_PREBOOT "" +#define CONFIG_PREBOOT "" -#define CONFIG_LOADADDR 0x12000000 -#define CONFIG_SYS_TEXT_BASE 0x17800000 +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 #ifdef CONFIG_CMD_SATA -#define CONFIG_DRIVE_SATA "sata " +#define CONFIG_DRIVE_SATA "sata " #else #define CONFIG_DRIVE_SATA #endif #ifdef CONFIG_CMD_MMC -#define CONFIG_DRIVE_MMC "mmc " +#define CONFIG_DRIVE_MMC "mmc " #else #define CONFIG_DRIVE_MMC #endif #ifdef CONFIG_USB_STORAGE -#define CONFIG_DRIVE_USB "usb " +#define CONFIG_DRIVE_USB "usb " #else #define CONFIG_DRIVE_USB #endif @@ -191,15 +176,16 @@ /* mmcdev=0 : eMMC mmcdev=1 : SD/MMC Card */ #define CONFIG_EXTRA_ENV_SETTINGS \ + "autoexec=/app/service/run.sh\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "loadaddr=0x12000000\0" \ "boot_fdt=try\0" \ "bootdelay=1\0" \ - "bootargs=console=ttymxc0,115200 root=/dev/ram0 rw --no-log initrd=0x1E000000,32M ramdisk=65536 video=${video_lvds} ${video_hdmi} ${video_vmalloc} ${arg_option}\0" \ - "bootargs_ram=setenv bootargs console=ttymxc0,115200 root=/dev/ram0 rw --no-log initrd=0x1E000000,32M ramdisk=65536 ${video_lvds} ${video_hdmi} ${video_vmalloc} ${arg_option} \0" \ - "bootargs_mmc=setenv bootargs console=ttymxc0,115200 root=/dev/mmcblk3p2 rw --no-log rootfstype=ext4 rootdelay=5 rootwait ${video_lvds} ${video_hdmi} ${video_vmalloc} ${arg_option}\0" \ + "bootargs=console=ttymxc0,115200 root=/dev/ram0 rw --no-log initrd=0x1E000000,32M ramdisk=65536 video=${video_lvds} ${video_vmalloc} ${arg_option} autosh=${autoexec}\0" \ + "bootargs_ram=setenv bootargs console=ttymxc0,115200 root=/dev/ram0 rw --no-log initrd=0x1E000000,32M ramdisk=65536 ${video_lvds} ${video_vmalloc} ${arg_option} autosh=${autoexec}\0" \ + "bootargs_mmc=setenv bootargs console=ttymxc0,115200 root=/dev/mmcblk3p2 rw --no-log rootfstype=ext4 rootdelay=5 rootwait ${video_lvds} ${video_vmalloc} ${arg_option} autosh=${autoexec}\0" \ "ethaddr=00:FA:15:12:02:02\0" \ "eth1addr=00:FA:15:12:02:04\0" \ "serverip=192.168.10.131\0" \ @@ -207,19 +193,19 @@ "netmask=255.255.0.0\0" \ "gatewayip=192.168.10.1\0" \ "ip_dyn=yes\0" \ - "video_lvds=video=mxcfb0:dev=ldb,LDB-G156BGE,if=RGB24\0" \ - "video_hdmi=video=mxcfb1:dev=hdmi,1920x1080@60,if=RGB24\0" \ - "video_vmalloc=fbmem=28M,28M fbcon=28M,28M vmalloc=400M\0" \ - "arg_option=fec.disable_giga=1\0" \ + "video_lvds=video=mxcfb0:dev=ldb,LDB-LP133WD2,if=RGB24 ldb=spl0\0" \ + "video_vmalloc=fbmem=192M vmalloc=400M\0" \ + "arg_option=loglevel=7\0" \ "mmcdev=0\0" \ - "uboot_file=u-boot.imx6_cmf\0" \ - "dtb_file=imx6dl-cmf.dtb\0" \ - "kernel_file=uImage.imx6_cmf\0" \ - "ramdisk_file=ramdisk.imx6_cmf-2.0-64M.gz\0" \ - "uboot=tftpboot 0x12000000 ${uboot_file}; mmc dev ${mmcdev}; mmc write 0x12000000 2 500; if ext4ls mmc ${mmcdev}:1 boot; then ext4writ mmc ${mmcdev}:1 0x12000000 /boot/${uboot_file} ${filesize}; fi;\0" \ - "kernel=tftpboot 0x12000000 ${kernel_file}; mmc dev ${mmcdev}; mmc write 0x12000000 1000 4000; if ext4ls mmc ${mmcdev}:1 boot; then ext4write mmc ${mmcdev}:1 0x12000000 /boot/${kernel_file} ${filesize}; fi;\0" \ - "dtb=tftpboot 0x11F00000 ${dtb_file}; mmc dev ${mmcdev}; mmc write 0x11F00000 A00 100; if ext4ls mmc ${mmcdev}:1 boot; then ext4write mmc ${mmcdev}:1 0x11F00000 /boot/${dtb_file} ${filesize}; fi;\0" \ - "ramdisk=tftpboot 0x1E000000 ${ramdisk_file}; mmc dev ${mmcdev}; mmc write 0x1E000000 7000 10000; if ext4ls mmc ${mmcdev}:1 boot; then ext4write mmc ${mmcdev}:1 0x1E000000 /boot/${ramdisk_file} ${filesize}; fi;\0" \ + "tftpbase=prime-oven\0" \ + "uboot_file=u-boot.imx\0" \ + "dtb_file=imx6sl-prime-oven.dtb\0" \ + "kernel_file=uImage\0" \ + "ramdisk_file=ramdisk.imx6-2.0-64M.gz\0" \ + "uboot=tftpboot 0x12000000 ${tftpbase}/${uboot_file}; mmc dev ${mmcdev}; mmc write 0x12000000 2 500; if ext4ls mmc ${mmcdev}:1 boot; then ext4writ mmc ${mmcdev}:1 0x12000000 /boot/${uboot_file} ${filesize}; fi;\0" \ + "kernel=tftpboot 0x12000000 ${tftpbase}/${kernel_file}; mmc dev ${mmcdev}; mmc write 0x12000000 1000 4000; if ext4ls mmc ${mmcdev}:1 boot; then ext4write mmc ${mmcdev}:1 0x12000000 /boot/${kernel_file} ${filesize}; fi;\0" \ + "dtb=tftpboot 0x11F00000 ${tftpbase}/${dtb_file}; mmc dev ${mmcdev}; mmc write 0x11F00000 A00 100; if ext4ls mmc ${mmcdev}:1 boot; then ext4write mmc ${mmcdev}:1 0x11F00000 /boot/${dtb_file} ${filesize}; fi;\0" \ + "ramdisk=tftpboot 0x1E000000 ${tftpbase}/${ramdisk_file}; mmc dev ${mmcdev}; mmc write 0x1E000000 7000 10000; if ext4ls mmc ${mmcdev}:1 boot; then ext4write mmc ${mmcdev}:1 0x1E000000 /boot/${ramdisk_file} ${filesize}; fi;\0" \ "bootram=mmc dev ${mmcdev}; mmcinfo; mmc read 0x11F00000 A00 100; mmc read 0x12000000 1000 4000; mmc read 0x1E000000 7000 10000; bootm 0x12000000 - 0x11F00000\0" \ "bootload= echo ; echo Loading a bootable image ...; mmc dev ${mmcdev}; " \ "if ext4load mmc ${mmcdev}:1 0x11F00000 /boot/${dtb_file}; then " \ @@ -253,7 +239,7 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "CELL v1 > " +#define CONFIG_SYS_PROMPT "prime > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MAXARGS 48 @@ -275,10 +261,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH @@ -288,15 +272,8 @@ #define CONFIG_ENV_IS_IN_MMC #if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (768 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) -#define CONFIG_ENV_OFFSET (768 * 1024) -#define CONFIG_ENV_SECT_SIZE (8 * 1024) -#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS -#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS -#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE -#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 #endif #define CONFIG_OF_LIBFDT @@ -344,7 +321,7 @@ #define CONFIG_CMD_FASTBOOT #define CONFIG_ANDROID_BOOT_IMAGE -#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 +#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 #endif /* __CONFIG_PRIME_OVEN_H */