Commit 35b968d1b1c096e5eb16c15736055bd661e0ba25
1 parent
067c0565d5
Exists in
master
and in
2 other branches
= Debug 코드 추가
Showing
1 changed file
with
277 additions
and
0 deletions
Show diff stats
kernel/linux-imx6_3.14.28/sound/soc/codecs/sgtl5000.c
@@ -31,6 +31,16 @@ | @@ -31,6 +31,16 @@ | ||
31 | 31 | ||
32 | #include "sgtl5000.h" | 32 | #include "sgtl5000.h" |
33 | 33 | ||
34 | +#define DEBUG_PROC 0 | ||
35 | +#define DEBUG 0 | ||
36 | + | ||
37 | +#if DEBUG_PROC | ||
38 | +#include <linux/proc_fs.h> | ||
39 | +#include <linux/seq_file.h> | ||
40 | +static struct proc_dir_entry *debug_proc_entry; | ||
41 | +struct snd_soc_codec *debug_codec = NULL; | ||
42 | +#endif | ||
43 | + | ||
34 | #define SGTL5000_DAP_REG_OFFSET 0x0100 | 44 | #define SGTL5000_DAP_REG_OFFSET 0x0100 |
35 | #define SGTL5000_MAX_REG_OFFSET 0x013A | 45 | #define SGTL5000_MAX_REG_OFFSET 0x013A |
36 | 46 | ||
@@ -76,6 +86,220 @@ static const struct reg_default sgtl5000_reg_defaults[] = { | @@ -76,6 +86,220 @@ static const struct reg_default sgtl5000_reg_defaults[] = { | ||
76 | { SGTL5000_DAP_AVC_DECAY, 0x0050 }, | 86 | { SGTL5000_DAP_AVC_DECAY, 0x0050 }, |
77 | }; | 87 | }; |
78 | 88 | ||
89 | +#if DEBUG_PROC | ||
90 | +char *uintToBinary(unsigned int i) { | ||
91 | + static char s[16 + 1] = { '0', }; | ||
92 | + int count = 16; | ||
93 | + | ||
94 | + do { | ||
95 | + s[--count] = '0' + (char) (i & 1); | ||
96 | + i = i >> 1; | ||
97 | + } while (count); | ||
98 | + | ||
99 | + return s; | ||
100 | +} | ||
101 | + | ||
102 | +static int dump_list[] = { | ||
103 | + SGTL5000_CHIP_ID, | ||
104 | + SGTL5000_CHIP_DIG_POWER, | ||
105 | + SGTL5000_CHIP_CLK_CTRL, | ||
106 | + SGTL5000_CHIP_I2S_CTRL, | ||
107 | + SGTL5000_CHIP_SSS_CTRL, | ||
108 | + SGTL5000_CHIP_ADCDAC_CTRL, | ||
109 | + SGTL5000_CHIP_DAC_VOL, | ||
110 | + SGTL5000_CHIP_PAD_STRENGTH, | ||
111 | + SGTL5000_CHIP_ANA_ADC_CTRL, | ||
112 | + SGTL5000_CHIP_ANA_HP_CTRL, | ||
113 | + SGTL5000_CHIP_ANA_CTRL, | ||
114 | + SGTL5000_CHIP_LINREG_CTRL, | ||
115 | + SGTL5000_CHIP_REF_CTRL, | ||
116 | + SGTL5000_CHIP_MIC_CTRL, | ||
117 | + SGTL5000_CHIP_LINE_OUT_CTRL, | ||
118 | + SGTL5000_CHIP_LINE_OUT_VOL, | ||
119 | + SGTL5000_CHIP_ANA_POWER, | ||
120 | + SGTL5000_CHIP_PLL_CTRL, | ||
121 | + SGTL5000_CHIP_CLK_TOP_CTRL, | ||
122 | + SGTL5000_CHIP_ANA_STATUS, | ||
123 | + SGTL5000_CHIP_SHORT_CTRL, | ||
124 | + SGTL5000_CHIP_ANA_TEST2, | ||
125 | + SGTL5000_DAP_CTRL, | ||
126 | + SGTL5000_DAP_PEQ, | ||
127 | + SGTL5000_DAP_BASS_ENHANCE, | ||
128 | + SGTL5000_DAP_BASS_ENHANCE_CTRL, | ||
129 | + SGTL5000_DAP_AUDIO_EQ, | ||
130 | + SGTL5000_DAP_SURROUND, | ||
131 | + SGTL5000_DAP_FLT_COEF_ACCESS, | ||
132 | + SGTL5000_DAP_COEF_WR_B0_MSB, | ||
133 | + SGTL5000_DAP_COEF_WR_B0_LSB, | ||
134 | + SGTL5000_DAP_EQ_BASS_BAND0, | ||
135 | + SGTL5000_DAP_EQ_BASS_BAND1, | ||
136 | + SGTL5000_DAP_EQ_BASS_BAND2, | ||
137 | + SGTL5000_DAP_EQ_BASS_BAND3, | ||
138 | + SGTL5000_DAP_EQ_BASS_BAND4, | ||
139 | + SGTL5000_DAP_MAIN_CHAN, | ||
140 | + SGTL5000_DAP_MIX_CHAN, | ||
141 | + SGTL5000_DAP_AVC_CTRL, | ||
142 | + SGTL5000_DAP_AVC_THRESHOLD, | ||
143 | + SGTL5000_DAP_AVC_ATTACK, | ||
144 | + SGTL5000_DAP_AVC_DECAY, | ||
145 | + SGTL5000_DAP_COEF_WR_B1_MSB, | ||
146 | + SGTL5000_DAP_COEF_WR_B1_LSB, | ||
147 | + SGTL5000_DAP_COEF_WR_B2_MSB, | ||
148 | + SGTL5000_DAP_COEF_WR_B2_LSB, | ||
149 | + SGTL5000_DAP_COEF_WR_A1_MSB, | ||
150 | + SGTL5000_DAP_COEF_WR_A1_LSB, | ||
151 | + SGTL5000_DAP_COEF_WR_A2_MSB, | ||
152 | + SGTL5000_DAP_COEF_WR_A2_LSB, | ||
153 | +}; | ||
154 | + | ||
155 | +static char *dump_reg_name[] = { | ||
156 | + "SGTL5000_CHIP_ID ", | ||
157 | + "SGTL5000_CHIP_DIG_POWER ", | ||
158 | + "SGTL5000_CHIP_CLK_CTRL ", | ||
159 | + "SGTL5000_CHIP_I2S_CTRL ", | ||
160 | + "SGTL5000_CHIP_SSS_CTRL ", | ||
161 | + "SGTL5000_CHIP_ADCDAC_CTRL ", | ||
162 | + "SGTL5000_CHIP_DAC_VOL ", | ||
163 | + "SGTL5000_CHIP_PAD_STRENGTH ", | ||
164 | + "SGTL5000_CHIP_ANA_ADC_CTRL ", | ||
165 | + "SGTL5000_CHIP_ANA_HP_CTRL ", | ||
166 | + "SGTL5000_CHIP_ANA_CTRL ", | ||
167 | + "SGTL5000_CHIP_LINREG_CTRL ", | ||
168 | + "SGTL5000_CHIP_REF_CTRL ", | ||
169 | + "SGTL5000_CHIP_MIC_CTRL ", | ||
170 | + "SGTL5000_CHIP_LINE_OUT_CTRL ", | ||
171 | + "SGTL5000_CHIP_LINE_OUT_VOL ", | ||
172 | + "SGTL5000_CHIP_ANA_POWER ", | ||
173 | + "SGTL5000_CHIP_PLL_CTRL ", | ||
174 | + "SGTL5000_CHIP_CLK_TOP_CTRL ", | ||
175 | + "SGTL5000_CHIP_ANA_STATUS ", | ||
176 | + "SGTL5000_CHIP_SHORT_CTRL ", | ||
177 | + "SGTL5000_CHIP_ANA_TEST2 ", | ||
178 | + "SGTL5000_DAP_CTRL ", | ||
179 | + "SGTL5000_DAP_PEQ ", | ||
180 | + "SGTL5000_DAP_BASS_ENHANCE ", | ||
181 | + "SGTL5000_DAP_BASS_ENHANCE_CTRL", | ||
182 | + "SGTL5000_DAP_AUDIO_EQ ", | ||
183 | + "SGTL5000_DAP_SURROUND ", | ||
184 | + "SGTL5000_DAP_FLT_COEF_ACCESS ", | ||
185 | + "SGTL5000_DAP_COEF_WR_B0_MSB ", | ||
186 | + "SGTL5000_DAP_COEF_WR_B0_LSB ", | ||
187 | + "SGTL5000_DAP_EQ_BASS_BAND0 ", | ||
188 | + "SGTL5000_DAP_EQ_BASS_BAND1 ", | ||
189 | + "SGTL5000_DAP_EQ_BASS_BAND2 ", | ||
190 | + "SGTL5000_DAP_EQ_BASS_BAND3 ", | ||
191 | + "SGTL5000_DAP_EQ_BASS_BAND4 ", | ||
192 | + "SGTL5000_DAP_MAIN_CHAN ", | ||
193 | + "SGTL5000_DAP_MIX_CHAN ", | ||
194 | + "SGTL5000_DAP_AVC_CTRL ", | ||
195 | + "SGTL5000_DAP_AVC_THRESHOLD ", | ||
196 | + "SGTL5000_DAP_AVC_ATTACK ", | ||
197 | + "SGTL5000_DAP_AVC_DECAY ", | ||
198 | + "SGTL5000_DAP_COEF_WR_B1_MSB ", | ||
199 | + "SGTL5000_DAP_COEF_WR_B1_LSB ", | ||
200 | + "SGTL5000_DAP_COEF_WR_B2_MSB ", | ||
201 | + "SGTL5000_DAP_COEF_WR_B2_LSB ", | ||
202 | + "SGTL5000_DAP_COEF_WR_A1_MSB ", | ||
203 | + "SGTL5000_DAP_COEF_WR_A1_LSB ", | ||
204 | + "SGTL5000_DAP_COEF_WR_A2_MSB ", | ||
205 | + "SGTL5000_DAP_COEF_WR_A2_LSB ", | ||
206 | +}; | ||
207 | + | ||
208 | +#endif | ||
209 | + | ||
210 | +#if DEBUG | ||
211 | +static void dump_reg(struct snd_soc_codec *codec) | ||
212 | +{ | ||
213 | + unsigned int i, reg; | ||
214 | + char *bin=NULL; | ||
215 | + | ||
216 | + printk("========================= Dump Register =========================\n"); | ||
217 | + printk("======[ Address] : ( Value ) [ Binary ] [ Register Name ]\n"); | ||
218 | + for (i = 0; i < ARRAY_SIZE(dump_list); i++) { | ||
219 | + reg = snd_soc_read(codec, dump_list[i]); | ||
220 | + bin = uintToBinary(reg); | ||
221 | +// printk("Dump: [ 0x%04X ] : ( 0x%04X ) - [ %s ]\n", dump_list[i], reg, dump_reg_name[i]); | ||
222 | + printk("Dump: [ 0x%04X ] : ( 0x%04X ) - [ %s ] [ %s ]\n", dump_list[i], reg, bin, dump_reg_name[i]); | ||
223 | +// printk(KERN_DEBUG "d r %04x, v %04x\n", dump_list[i], reg); | ||
224 | + } | ||
225 | + printk("========================= Dump Register =========================\n"); | ||
226 | +} | ||
227 | + | ||
228 | +static void simple_dump_reg(struct snd_soc_codec *codec) | ||
229 | +{ | ||
230 | + int i; | ||
231 | + int arrval[60]; | ||
232 | + | ||
233 | + arrval[0] = snd_soc_read(codec, SGTL5000_CHIP_ID ); | ||
234 | + arrval[1] = snd_soc_read(codec, SGTL5000_CHIP_DIG_POWER ); | ||
235 | + arrval[2] = snd_soc_read(codec, SGTL5000_CHIP_CLK_CTRL ); | ||
236 | + arrval[3] = snd_soc_read(codec, SGTL5000_CHIP_I2S_CTRL ); | ||
237 | + arrval[4] = snd_soc_read(codec, SGTL5000_CHIP_SSS_CTRL ); | ||
238 | + arrval[5] = snd_soc_read(codec, SGTL5000_CHIP_ADCDAC_CTRL ); | ||
239 | + arrval[6] = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL ); | ||
240 | + arrval[7] = snd_soc_read(codec, SGTL5000_CHIP_PAD_STRENGTH ); | ||
241 | + arrval[8] = snd_soc_read(codec, SGTL5000_CHIP_ANA_ADC_CTRL ); | ||
242 | + arrval[9] = snd_soc_read(codec, SGTL5000_CHIP_ANA_HP_CTRL ); | ||
243 | + arrval[10] = snd_soc_read(codec, SGTL5000_CHIP_ANA_CTRL ); | ||
244 | + arrval[11] = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL ); | ||
245 | + arrval[12] = snd_soc_read(codec, SGTL5000_CHIP_REF_CTRL ); | ||
246 | + arrval[13] = snd_soc_read(codec, SGTL5000_CHIP_MIC_CTRL ); | ||
247 | + arrval[14] = snd_soc_read(codec, SGTL5000_CHIP_LINE_OUT_CTRL ); | ||
248 | + arrval[15] = snd_soc_read(codec, SGTL5000_CHIP_LINE_OUT_VOL ); | ||
249 | + arrval[16] = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER ); | ||
250 | + arrval[17] = snd_soc_read(codec, SGTL5000_CHIP_PLL_CTRL ); | ||
251 | + arrval[18] = snd_soc_read(codec, SGTL5000_CHIP_CLK_TOP_CTRL ); | ||
252 | + arrval[19] = snd_soc_read(codec, SGTL5000_CHIP_ANA_STATUS ); | ||
253 | + arrval[20] = snd_soc_read(codec, SGTL5000_CHIP_SHORT_CTRL ); | ||
254 | + arrval[21] = snd_soc_read(codec, SGTL5000_CHIP_ANA_TEST2 ); | ||
255 | + arrval[22] = snd_soc_read(codec, SGTL5000_DAP_CTRL ); | ||
256 | + arrval[23] = snd_soc_read(codec, SGTL5000_DAP_PEQ ); | ||
257 | + arrval[24] = snd_soc_read(codec, SGTL5000_DAP_BASS_ENHANCE ); | ||
258 | + arrval[25] = snd_soc_read(codec, SGTL5000_DAP_BASS_ENHANCE_CTRL); | ||
259 | + arrval[26] = snd_soc_read(codec, SGTL5000_DAP_AUDIO_EQ ); | ||
260 | + arrval[27] = snd_soc_read(codec, SGTL5000_DAP_SURROUND ); | ||
261 | + arrval[28] = snd_soc_read(codec, SGTL5000_DAP_FLT_COEF_ACCESS); | ||
262 | + arrval[29] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_B0_MSB ); | ||
263 | + arrval[30] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_B0_LSB ); | ||
264 | + arrval[31] = snd_soc_read(codec, SGTL5000_DAP_EQ_BASS_BAND0 ); | ||
265 | + arrval[32] = snd_soc_read(codec, SGTL5000_DAP_EQ_BASS_BAND1 ); | ||
266 | + arrval[33] = snd_soc_read(codec, SGTL5000_DAP_EQ_BASS_BAND2 ); | ||
267 | + arrval[34] = snd_soc_read(codec, SGTL5000_DAP_EQ_BASS_BAND3 ); | ||
268 | + arrval[35] = snd_soc_read(codec, SGTL5000_DAP_EQ_BASS_BAND4 ); | ||
269 | + arrval[36] = snd_soc_read(codec, SGTL5000_DAP_MAIN_CHAN ); | ||
270 | + arrval[37] = snd_soc_read(codec, SGTL5000_DAP_MIX_CHAN ); | ||
271 | + arrval[38] = snd_soc_read(codec, SGTL5000_DAP_AVC_CTRL ); | ||
272 | + arrval[39] = snd_soc_read(codec, SGTL5000_DAP_AVC_THRESHOLD ); | ||
273 | + arrval[40] = snd_soc_read(codec, SGTL5000_DAP_AVC_ATTACK ); | ||
274 | + arrval[41] = snd_soc_read(codec, SGTL5000_DAP_AVC_DECAY ); | ||
275 | + arrval[42] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_B1_MSB ); | ||
276 | + arrval[43] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_B1_LSB ); | ||
277 | + arrval[44] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_B2_MSB ); | ||
278 | + arrval[45] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_B2_LSB ); | ||
279 | + arrval[46] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_A1_MSB ); | ||
280 | + arrval[47] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_A1_LSB ); | ||
281 | + arrval[48] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_A2_MSB ); | ||
282 | + arrval[49] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_A2_LSB ); | ||
283 | + | ||
284 | + for(i=0; i<50; i++) | ||
285 | + { | ||
286 | + if(i%8 == 0) | ||
287 | + printk("\n"); | ||
288 | + printk("%04X ",arrval[i]); | ||
289 | + } | ||
290 | + printk("\n"); | ||
291 | +} | ||
292 | + | ||
293 | +#else | ||
294 | +static void dump_reg(struct snd_soc_codec *codec) | ||
295 | +{ | ||
296 | +} | ||
297 | + | ||
298 | +static void simple_dump_reg(struct snd_soc_codec *codec) | ||
299 | +{ | ||
300 | +} | ||
301 | +#endif | ||
302 | + | ||
79 | /* regulator supplies for sgtl5000, VDDD is an optional external supply */ | 303 | /* regulator supplies for sgtl5000, VDDD is an optional external supply */ |
80 | enum sgtl5000_regulator_supplies { | 304 | enum sgtl5000_regulator_supplies { |
81 | VDDA, | 305 | VDDA, |
@@ -1334,11 +1558,60 @@ err_ldo_remove: | @@ -1334,11 +1558,60 @@ err_ldo_remove: | ||
1334 | 1558 | ||
1335 | } | 1559 | } |
1336 | 1560 | ||
1561 | +#if DEBUG_PROC | ||
1562 | +static ssize_t debug_proc_write(struct file *file, const char __user *buf, | ||
1563 | + size_t count, loff_t *ppos) | ||
1564 | +{ | ||
1565 | + int i, len; | ||
1566 | + char buffer[256]; | ||
1567 | + | ||
1568 | + for(i=0;i<count-1;i++) | ||
1569 | + buffer[i] = buf[i]; | ||
1570 | + | ||
1571 | + buffer[i] = '\0'; | ||
1572 | + | ||
1573 | + // TODO: Debug Code | ||
1574 | + if( buffer[0] == 'd' ) | ||
1575 | + { | ||
1576 | + dump_reg(debug_codec); | ||
1577 | + } | ||
1578 | + else if( buffer[0] == 's' ) | ||
1579 | + { | ||
1580 | + simple_dump_reg(debug_codec); | ||
1581 | + } | ||
1582 | + | ||
1583 | + len = count; | ||
1584 | + return len; | ||
1585 | +} | ||
1586 | + | ||
1587 | +static int debug_proc_show(struct seq_file *m, void *v) | ||
1588 | +{ | ||
1589 | + return 0; | ||
1590 | +} | ||
1591 | + | ||
1592 | +static int debug_proc_open(struct inode *inode, struct file *file) | ||
1593 | +{ | ||
1594 | + return single_open(file, debug_proc_show, NULL); | ||
1595 | +} | ||
1596 | + | ||
1597 | +static struct file_operations debug_proc_ops = { | ||
1598 | + .owner = THIS_MODULE, | ||
1599 | + .open = debug_proc_open, | ||
1600 | + .read = seq_read, | ||
1601 | + .write = debug_proc_write, | ||
1602 | +}; | ||
1603 | +#endif | ||
1604 | + | ||
1337 | static int sgtl5000_probe(struct snd_soc_codec *codec) | 1605 | static int sgtl5000_probe(struct snd_soc_codec *codec) |
1338 | { | 1606 | { |
1339 | int ret; | 1607 | int ret; |
1340 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); | 1608 | struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); |
1341 | 1609 | ||
1610 | +#if DEBUG_PROC | ||
1611 | + printk("LINE[%04d]: func(%s)\n",__LINE__,__func__); | ||
1612 | + debug_proc_entry = proc_create("debug_snd_proc", S_IRUGO | S_IFREG, NULL, &debug_proc_ops); | ||
1613 | +#endif | ||
1614 | + | ||
1342 | /* setup i2c data ops */ | 1615 | /* setup i2c data ops */ |
1343 | codec->control_data = sgtl5000->regmap; | 1616 | codec->control_data = sgtl5000->regmap; |
1344 | ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP); | 1617 | ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP); |
@@ -1347,6 +1620,10 @@ static int sgtl5000_probe(struct snd_soc_codec *codec) | @@ -1347,6 +1620,10 @@ static int sgtl5000_probe(struct snd_soc_codec *codec) | ||
1347 | return ret; | 1620 | return ret; |
1348 | } | 1621 | } |
1349 | 1622 | ||
1623 | +#if DEBUG_PROC | ||
1624 | + debug_codec = codec; | ||
1625 | +#endif | ||
1626 | + | ||
1350 | ret = sgtl5000_enable_regulators(codec); | 1627 | ret = sgtl5000_enable_regulators(codec); |
1351 | if (ret) | 1628 | if (ret) |
1352 | return ret; | 1629 | return ret; |