From 35b968d1b1c096e5eb16c15736055bd661e0ba25 Mon Sep 17 00:00:00 2001
From: larche <larche@falinux.com>
Date: Mon, 26 Jun 2017 11:03:23 +0900
Subject: [PATCH] =?UTF-8?q?=3D=20Debug=20=EC=BD=94=EB=93=9C=20=EC=B6=94?=
=?UTF-8?q?=EA=B0=80?=
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---
.../linux-imx6_3.14.28/sound/soc/codecs/sgtl5000.c | 277 +++++++++++++++++++++
1 file changed, 277 insertions(+)
diff --git a/kernel/linux-imx6_3.14.28/sound/soc/codecs/sgtl5000.c b/kernel/linux-imx6_3.14.28/sound/soc/codecs/sgtl5000.c
index e994d7d..b746a82 100644
--- a/kernel/linux-imx6_3.14.28/sound/soc/codecs/sgtl5000.c
+++ b/kernel/linux-imx6_3.14.28/sound/soc/codecs/sgtl5000.c
@@ -31,6 +31,16 @@
#include "sgtl5000.h"
+#define DEBUG_PROC 0
+#define DEBUG 0
+
+#if DEBUG_PROC
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+static struct proc_dir_entry *debug_proc_entry;
+struct snd_soc_codec *debug_codec = NULL;
+#endif
+
#define SGTL5000_DAP_REG_OFFSET 0x0100
#define SGTL5000_MAX_REG_OFFSET 0x013A
@@ -76,6 +86,220 @@ static const struct reg_default sgtl5000_reg_defaults[] = {
{ SGTL5000_DAP_AVC_DECAY, 0x0050 },
};
+#if DEBUG_PROC
+char *uintToBinary(unsigned int i) {
+ static char s[16 + 1] = { '0', };
+ int count = 16;
+
+ do {
+ s[--count] = '0' + (char) (i & 1);
+ i = i >> 1;
+ } while (count);
+
+ return s;
+}
+
+static int dump_list[] = {
+ SGTL5000_CHIP_ID,
+ SGTL5000_CHIP_DIG_POWER,
+ SGTL5000_CHIP_CLK_CTRL,
+ SGTL5000_CHIP_I2S_CTRL,
+ SGTL5000_CHIP_SSS_CTRL,
+ SGTL5000_CHIP_ADCDAC_CTRL,
+ SGTL5000_CHIP_DAC_VOL,
+ SGTL5000_CHIP_PAD_STRENGTH,
+ SGTL5000_CHIP_ANA_ADC_CTRL,
+ SGTL5000_CHIP_ANA_HP_CTRL,
+ SGTL5000_CHIP_ANA_CTRL,
+ SGTL5000_CHIP_LINREG_CTRL,
+ SGTL5000_CHIP_REF_CTRL,
+ SGTL5000_CHIP_MIC_CTRL,
+ SGTL5000_CHIP_LINE_OUT_CTRL,
+ SGTL5000_CHIP_LINE_OUT_VOL,
+ SGTL5000_CHIP_ANA_POWER,
+ SGTL5000_CHIP_PLL_CTRL,
+ SGTL5000_CHIP_CLK_TOP_CTRL,
+ SGTL5000_CHIP_ANA_STATUS,
+ SGTL5000_CHIP_SHORT_CTRL,
+ SGTL5000_CHIP_ANA_TEST2,
+ SGTL5000_DAP_CTRL,
+ SGTL5000_DAP_PEQ,
+ SGTL5000_DAP_BASS_ENHANCE,
+ SGTL5000_DAP_BASS_ENHANCE_CTRL,
+ SGTL5000_DAP_AUDIO_EQ,
+ SGTL5000_DAP_SURROUND,
+ SGTL5000_DAP_FLT_COEF_ACCESS,
+ SGTL5000_DAP_COEF_WR_B0_MSB,
+ SGTL5000_DAP_COEF_WR_B0_LSB,
+ SGTL5000_DAP_EQ_BASS_BAND0,
+ SGTL5000_DAP_EQ_BASS_BAND1,
+ SGTL5000_DAP_EQ_BASS_BAND2,
+ SGTL5000_DAP_EQ_BASS_BAND3,
+ SGTL5000_DAP_EQ_BASS_BAND4,
+ SGTL5000_DAP_MAIN_CHAN,
+ SGTL5000_DAP_MIX_CHAN,
+ SGTL5000_DAP_AVC_CTRL,
+ SGTL5000_DAP_AVC_THRESHOLD,
+ SGTL5000_DAP_AVC_ATTACK,
+ SGTL5000_DAP_AVC_DECAY,
+ SGTL5000_DAP_COEF_WR_B1_MSB,
+ SGTL5000_DAP_COEF_WR_B1_LSB,
+ SGTL5000_DAP_COEF_WR_B2_MSB,
+ SGTL5000_DAP_COEF_WR_B2_LSB,
+ SGTL5000_DAP_COEF_WR_A1_MSB,
+ SGTL5000_DAP_COEF_WR_A1_LSB,
+ SGTL5000_DAP_COEF_WR_A2_MSB,
+ SGTL5000_DAP_COEF_WR_A2_LSB,
+};
+
+static char *dump_reg_name[] = {
+ "SGTL5000_CHIP_ID ",
+ "SGTL5000_CHIP_DIG_POWER ",
+ "SGTL5000_CHIP_CLK_CTRL ",
+ "SGTL5000_CHIP_I2S_CTRL ",
+ "SGTL5000_CHIP_SSS_CTRL ",
+ "SGTL5000_CHIP_ADCDAC_CTRL ",
+ "SGTL5000_CHIP_DAC_VOL ",
+ "SGTL5000_CHIP_PAD_STRENGTH ",
+ "SGTL5000_CHIP_ANA_ADC_CTRL ",
+ "SGTL5000_CHIP_ANA_HP_CTRL ",
+ "SGTL5000_CHIP_ANA_CTRL ",
+ "SGTL5000_CHIP_LINREG_CTRL ",
+ "SGTL5000_CHIP_REF_CTRL ",
+ "SGTL5000_CHIP_MIC_CTRL ",
+ "SGTL5000_CHIP_LINE_OUT_CTRL ",
+ "SGTL5000_CHIP_LINE_OUT_VOL ",
+ "SGTL5000_CHIP_ANA_POWER ",
+ "SGTL5000_CHIP_PLL_CTRL ",
+ "SGTL5000_CHIP_CLK_TOP_CTRL ",
+ "SGTL5000_CHIP_ANA_STATUS ",
+ "SGTL5000_CHIP_SHORT_CTRL ",
+ "SGTL5000_CHIP_ANA_TEST2 ",
+ "SGTL5000_DAP_CTRL ",
+ "SGTL5000_DAP_PEQ ",
+ "SGTL5000_DAP_BASS_ENHANCE ",
+ "SGTL5000_DAP_BASS_ENHANCE_CTRL",
+ "SGTL5000_DAP_AUDIO_EQ ",
+ "SGTL5000_DAP_SURROUND ",
+ "SGTL5000_DAP_FLT_COEF_ACCESS ",
+ "SGTL5000_DAP_COEF_WR_B0_MSB ",
+ "SGTL5000_DAP_COEF_WR_B0_LSB ",
+ "SGTL5000_DAP_EQ_BASS_BAND0 ",
+ "SGTL5000_DAP_EQ_BASS_BAND1 ",
+ "SGTL5000_DAP_EQ_BASS_BAND2 ",
+ "SGTL5000_DAP_EQ_BASS_BAND3 ",
+ "SGTL5000_DAP_EQ_BASS_BAND4 ",
+ "SGTL5000_DAP_MAIN_CHAN ",
+ "SGTL5000_DAP_MIX_CHAN ",
+ "SGTL5000_DAP_AVC_CTRL ",
+ "SGTL5000_DAP_AVC_THRESHOLD ",
+ "SGTL5000_DAP_AVC_ATTACK ",
+ "SGTL5000_DAP_AVC_DECAY ",
+ "SGTL5000_DAP_COEF_WR_B1_MSB ",
+ "SGTL5000_DAP_COEF_WR_B1_LSB ",
+ "SGTL5000_DAP_COEF_WR_B2_MSB ",
+ "SGTL5000_DAP_COEF_WR_B2_LSB ",
+ "SGTL5000_DAP_COEF_WR_A1_MSB ",
+ "SGTL5000_DAP_COEF_WR_A1_LSB ",
+ "SGTL5000_DAP_COEF_WR_A2_MSB ",
+ "SGTL5000_DAP_COEF_WR_A2_LSB ",
+};
+
+#endif
+
+#if DEBUG
+static void dump_reg(struct snd_soc_codec *codec)
+{
+ unsigned int i, reg;
+ char *bin=NULL;
+
+ printk("========================= Dump Register =========================\n");
+ printk("======[ Address] : ( Value ) [ Binary ] [ Register Name ]\n");
+ for (i = 0; i < ARRAY_SIZE(dump_list); i++) {
+ reg = snd_soc_read(codec, dump_list[i]);
+ bin = uintToBinary(reg);
+// printk("Dump: [ 0x%04X ] : ( 0x%04X ) - [ %s ]\n", dump_list[i], reg, dump_reg_name[i]);
+ printk("Dump: [ 0x%04X ] : ( 0x%04X ) - [ %s ] [ %s ]\n", dump_list[i], reg, bin, dump_reg_name[i]);
+// printk(KERN_DEBUG "d r %04x, v %04x\n", dump_list[i], reg);
+ }
+ printk("========================= Dump Register =========================\n");
+}
+
+static void simple_dump_reg(struct snd_soc_codec *codec)
+{
+ int i;
+ int arrval[60];
+
+ arrval[0] = snd_soc_read(codec, SGTL5000_CHIP_ID );
+ arrval[1] = snd_soc_read(codec, SGTL5000_CHIP_DIG_POWER );
+ arrval[2] = snd_soc_read(codec, SGTL5000_CHIP_CLK_CTRL );
+ arrval[3] = snd_soc_read(codec, SGTL5000_CHIP_I2S_CTRL );
+ arrval[4] = snd_soc_read(codec, SGTL5000_CHIP_SSS_CTRL );
+ arrval[5] = snd_soc_read(codec, SGTL5000_CHIP_ADCDAC_CTRL );
+ arrval[6] = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL );
+ arrval[7] = snd_soc_read(codec, SGTL5000_CHIP_PAD_STRENGTH );
+ arrval[8] = snd_soc_read(codec, SGTL5000_CHIP_ANA_ADC_CTRL );
+ arrval[9] = snd_soc_read(codec, SGTL5000_CHIP_ANA_HP_CTRL );
+ arrval[10] = snd_soc_read(codec, SGTL5000_CHIP_ANA_CTRL );
+ arrval[11] = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL );
+ arrval[12] = snd_soc_read(codec, SGTL5000_CHIP_REF_CTRL );
+ arrval[13] = snd_soc_read(codec, SGTL5000_CHIP_MIC_CTRL );
+ arrval[14] = snd_soc_read(codec, SGTL5000_CHIP_LINE_OUT_CTRL );
+ arrval[15] = snd_soc_read(codec, SGTL5000_CHIP_LINE_OUT_VOL );
+ arrval[16] = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER );
+ arrval[17] = snd_soc_read(codec, SGTL5000_CHIP_PLL_CTRL );
+ arrval[18] = snd_soc_read(codec, SGTL5000_CHIP_CLK_TOP_CTRL );
+ arrval[19] = snd_soc_read(codec, SGTL5000_CHIP_ANA_STATUS );
+ arrval[20] = snd_soc_read(codec, SGTL5000_CHIP_SHORT_CTRL );
+ arrval[21] = snd_soc_read(codec, SGTL5000_CHIP_ANA_TEST2 );
+ arrval[22] = snd_soc_read(codec, SGTL5000_DAP_CTRL );
+ arrval[23] = snd_soc_read(codec, SGTL5000_DAP_PEQ );
+ arrval[24] = snd_soc_read(codec, SGTL5000_DAP_BASS_ENHANCE );
+ arrval[25] = snd_soc_read(codec, SGTL5000_DAP_BASS_ENHANCE_CTRL);
+ arrval[26] = snd_soc_read(codec, SGTL5000_DAP_AUDIO_EQ );
+ arrval[27] = snd_soc_read(codec, SGTL5000_DAP_SURROUND );
+ arrval[28] = snd_soc_read(codec, SGTL5000_DAP_FLT_COEF_ACCESS);
+ arrval[29] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_B0_MSB );
+ arrval[30] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_B0_LSB );
+ arrval[31] = snd_soc_read(codec, SGTL5000_DAP_EQ_BASS_BAND0 );
+ arrval[32] = snd_soc_read(codec, SGTL5000_DAP_EQ_BASS_BAND1 );
+ arrval[33] = snd_soc_read(codec, SGTL5000_DAP_EQ_BASS_BAND2 );
+ arrval[34] = snd_soc_read(codec, SGTL5000_DAP_EQ_BASS_BAND3 );
+ arrval[35] = snd_soc_read(codec, SGTL5000_DAP_EQ_BASS_BAND4 );
+ arrval[36] = snd_soc_read(codec, SGTL5000_DAP_MAIN_CHAN );
+ arrval[37] = snd_soc_read(codec, SGTL5000_DAP_MIX_CHAN );
+ arrval[38] = snd_soc_read(codec, SGTL5000_DAP_AVC_CTRL );
+ arrval[39] = snd_soc_read(codec, SGTL5000_DAP_AVC_THRESHOLD );
+ arrval[40] = snd_soc_read(codec, SGTL5000_DAP_AVC_ATTACK );
+ arrval[41] = snd_soc_read(codec, SGTL5000_DAP_AVC_DECAY );
+ arrval[42] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_B1_MSB );
+ arrval[43] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_B1_LSB );
+ arrval[44] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_B2_MSB );
+ arrval[45] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_B2_LSB );
+ arrval[46] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_A1_MSB );
+ arrval[47] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_A1_LSB );
+ arrval[48] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_A2_MSB );
+ arrval[49] = snd_soc_read(codec, SGTL5000_DAP_COEF_WR_A2_LSB );
+
+ for(i=0; i<50; i++)
+ {
+ if(i%8 == 0)
+ printk("\n");
+ printk("%04X ",arrval[i]);
+ }
+ printk("\n");
+}
+
+#else
+static void dump_reg(struct snd_soc_codec *codec)
+{
+}
+
+static void simple_dump_reg(struct snd_soc_codec *codec)
+{
+}
+#endif
+
/* regulator supplies for sgtl5000, VDDD is an optional external supply */
enum sgtl5000_regulator_supplies {
VDDA,
@@ -1334,11 +1558,60 @@ err_ldo_remove:
}
+#if DEBUG_PROC
+static ssize_t debug_proc_write(struct file *file, const char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ int i, len;
+ char buffer[256];
+
+ for(i=0;i<count-1;i++)
+ buffer[i] = buf[i];
+
+ buffer[i] = '\0';
+
+ // TODO: Debug Code
+ if( buffer[0] == 'd' )
+ {
+ dump_reg(debug_codec);
+ }
+ else if( buffer[0] == 's' )
+ {
+ simple_dump_reg(debug_codec);
+ }
+
+ len = count;
+ return len;
+}
+
+static int debug_proc_show(struct seq_file *m, void *v)
+{
+ return 0;
+}
+
+static int debug_proc_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, debug_proc_show, NULL);
+}
+
+static struct file_operations debug_proc_ops = {
+ .owner = THIS_MODULE,
+ .open = debug_proc_open,
+ .read = seq_read,
+ .write = debug_proc_write,
+};
+#endif
+
static int sgtl5000_probe(struct snd_soc_codec *codec)
{
int ret;
struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
+#if DEBUG_PROC
+ printk("LINE[%04d]: func(%s)\n",__LINE__,__func__);
+ debug_proc_entry = proc_create("debug_snd_proc", S_IRUGO | S_IFREG, NULL, &debug_proc_ops);
+#endif
+
/* setup i2c data ops */
codec->control_data = sgtl5000->regmap;
ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
@@ -1347,6 +1620,10 @@ static int sgtl5000_probe(struct snd_soc_codec *codec)
return ret;
}
+#if DEBUG_PROC
+ debug_codec = codec;
+#endif
+
ret = sgtl5000_enable_regulators(codec);
if (ret)
return ret;
--
2.1.4