에프에이리눅스 / fullcycle-jenkins-joy

drxj_map.h 990 KB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598 4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682 4683 4684 4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930 4931 4932 4933 4934 4935 4936 4937 4938 4939 4940 4941 4942 4943 4944 4945 4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971 4972 4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983 4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026 5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 5062 5063 5064 5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101 5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116 5117 5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139 5140 5141 5142 5143 5144 5145 5146 5147 5148 5149 5150 5151 5152 5153 5154 5155 5156 5157 5158 5159 5160 5161 5162 5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194 5195 5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216 5217 5218 5219 5220 5221 5222 5223 5224 5225 5226 5227 5228 5229 5230 5231 5232 5233 5234 5235 5236 5237 5238 5239 5240 5241 5242 5243 5244 5245 5246 5247 5248 5249 5250 5251 5252 5253 5254 5255 5256 5257 5258 5259 5260 5261 5262 5263 5264 5265 5266 5267 5268 5269 5270 5271 5272 5273 5274 5275 5276 5277 5278 5279 5280 5281 5282 5283 5284 5285 5286 5287 5288 5289 5290 5291 5292 5293 5294 5295 5296 5297 5298 5299 5300 5301 5302 5303 5304 5305 5306 5307 5308 5309 5310 5311 5312 5313 5314 5315 5316 5317 5318 5319 5320 5321 5322 5323 5324 5325 5326 5327 5328 5329 5330 5331 5332 5333 5334 5335 5336 5337 5338 5339 5340 5341 5342 5343 5344 5345 5346 5347 5348 5349 5350 5351 5352 5353 5354 5355 5356 5357 5358 5359 5360 5361 5362 5363 5364 5365 5366 5367 5368 5369 5370 5371 5372 5373 5374 5375 5376 5377 5378 5379 5380 5381 5382 5383 5384 5385 5386 5387 5388 5389 5390 5391 5392 5393 5394 5395 5396 5397 5398 5399 5400 5401 5402 5403 5404 5405 5406 5407 5408 5409 5410 5411 5412 5413 5414 5415 5416 5417 5418 5419 5420 5421 5422 5423 5424 5425 5426 5427 5428 5429 5430 5431 5432 5433 5434 5435 5436 5437 5438 5439 5440 5441 5442 5443 5444 5445 5446 5447 5448 5449 5450 5451 5452 5453 5454 5455 5456 5457 5458 5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469 5470 5471 5472 5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491 5492 5493 5494 5495 5496 5497 5498 5499 5500 5501 5502 5503 5504 5505 5506 5507 5508 5509 5510 5511 5512 5513 5514 5515 5516 5517 5518 5519 5520 5521 5522 5523 5524 5525 5526 5527 5528 5529 5530 5531 5532 5533 5534 5535 5536 5537 5538 5539 5540 5541 5542 5543 5544 5545 5546 5547 5548 5549 5550 5551 5552 5553 5554 5555 5556 5557 5558 5559 5560 5561 5562 5563 5564 5565 5566 5567 5568 5569 5570 5571 5572 5573 5574 5575 5576 5577 5578 5579 5580 5581 5582 5583 5584 5585 5586 5587 5588 5589 5590 5591 5592 5593 5594 5595 5596 5597 5598 5599 5600 5601 5602 5603 5604 5605 5606 5607 5608 5609 5610 5611 5612 5613 5614 5615 5616 5617 5618 5619 5620 5621 5622 5623 5624 5625 5626 5627 5628 5629 5630 5631 5632 5633 5634 5635 5636 5637 5638 5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652 5653 5654 5655 5656 5657 5658 5659 5660 5661 5662 5663 5664 5665 5666 5667 5668 5669 5670 5671 5672 5673 5674 5675 5676 5677 5678 5679 5680 5681 5682 5683 5684 5685 5686 5687 5688 5689 5690 5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701 5702 5703 5704 5705 5706 5707 5708 5709 5710 5711 5712 5713 5714 5715 5716 5717 5718 5719 5720 5721 5722 5723 5724 5725 5726 5727 5728 5729 5730 5731 5732 5733 5734 5735 5736 5737 5738 5739 5740 5741 5742 5743 5744 5745 5746 5747 5748 5749 5750 5751 5752 5753 5754 5755 5756 5757 5758 5759 5760 5761 5762 5763 5764 5765 5766 5767 5768 5769 5770 5771 5772 5773 5774 5775 5776 5777 5778 5779 5780 5781 5782 5783 5784 5785 5786 5787 5788 5789 5790 5791 5792 5793 5794 5795 5796 5797 5798 5799 5800 5801 5802 5803 5804 5805 5806 5807 5808 5809 5810 5811 5812 5813 5814 5815 5816 5817 5818 5819 5820 5821 5822 5823 5824 5825 5826 5827 5828 5829 5830 5831 5832 5833 5834 5835 5836 5837 5838 5839 5840 5841 5842 5843 5844 5845 5846 5847 5848 5849 5850 5851 5852 5853 5854 5855 5856 5857 5858 5859 5860 5861 5862 5863 5864 5865 5866 5867 5868 5869 5870 5871 5872 5873 5874 5875 5876 5877 5878 5879 5880 5881 5882 5883 5884 5885 5886 5887 5888 5889 5890 5891 5892 5893 5894 5895 5896 5897 5898 5899 5900 5901 5902 5903 5904 5905 5906 5907 5908 5909 5910 5911 5912 5913 5914 5915 5916 5917 5918 5919 5920 5921 5922 5923 5924 5925 5926 5927 5928 5929 5930 5931 5932 5933 5934 5935 5936 5937 5938 5939 5940 5941 5942 5943 5944 5945 5946 5947 5948 5949 5950 5951 5952 5953 5954 5955 5956 5957 5958 5959 5960 5961 5962 5963 5964 5965 5966 5967 5968 5969 5970 5971 5972 5973 5974 5975 5976 5977 5978 5979 5980 5981 5982 5983 5984 5985 5986 5987 5988 5989 5990 5991 5992 5993 5994 5995 5996 5997 5998 5999 6000 6001 6002 6003 6004 6005 6006 6007 6008 6009 6010 6011 6012 6013 6014 6015 6016 6017 6018 6019 6020 6021 6022 6023 6024 6025 6026 6027 6028 6029 6030 6031 6032 6033 6034 6035 6036 6037 6038 6039 6040 6041 6042 6043 6044 6045 6046 6047 6048 6049 6050 6051 6052 6053 6054 6055 6056 6057 6058 6059 6060 6061 6062 6063 6064 6065 6066 6067 6068 6069 6070 6071 6072 6073 6074 6075 6076 6077 6078 6079 6080 6081 6082 6083 6084 6085 6086 6087 6088 6089 6090 6091 6092 6093 6094 6095 6096 6097 6098 6099 6100 6101 6102 6103 6104 6105 6106 6107 6108 6109 6110 6111 6112 6113 6114 6115 6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128 6129 6130 6131 6132 6133 6134 6135 6136 6137 6138 6139 6140 6141 6142 6143 6144 6145 6146 6147 6148 6149 6150 6151 6152 6153 6154 6155 6156 6157 6158 6159 6160 6161 6162 6163 6164 6165 6166 6167 6168 6169 6170 6171 6172 6173 6174 6175 6176 6177 6178 6179 6180 6181 6182 6183 6184 6185 6186 6187 6188 6189 6190 6191 6192 6193 6194 6195 6196 6197 6198 6199 6200 6201 6202 6203 6204 6205 6206 6207 6208 6209 6210 6211 6212 6213 6214 6215 6216 6217 6218 6219 6220 6221 6222 6223 6224 6225 6226 6227 6228 6229 6230 6231 6232 6233 6234 6235 6236 6237 6238 6239 6240 6241 6242 6243 6244 6245 6246 6247 6248 6249 6250 6251 6252 6253 6254 6255 6256 6257 6258 6259 6260 6261 6262 6263 6264 6265 6266 6267 6268 6269 6270 6271 6272 6273 6274 6275 6276 6277 6278 6279 6280 6281 6282 6283 6284 6285 6286 6287 6288 6289 6290 6291 6292 6293 6294 6295 6296 6297 6298 6299 6300 6301 6302 6303 6304 6305 6306 6307 6308 6309 6310 6311 6312 6313 6314 6315 6316 6317 6318 6319 6320 6321 6322 6323 6324 6325 6326 6327 6328 6329 6330 6331 6332 6333 6334 6335 6336 6337 6338 6339 6340 6341 6342 6343 6344 6345 6346 6347 6348 6349 6350 6351 6352 6353 6354 6355 6356 6357 6358 6359 6360 6361 6362 6363 6364 6365 6366 6367 6368 6369 6370 6371 6372 6373 6374 6375 6376 6377 6378 6379 6380 6381 6382 6383 6384 6385 6386 6387 6388 6389 6390 6391 6392 6393 6394 6395 6396 6397 6398 6399 6400 6401 6402 6403 6404 6405 6406 6407 6408 6409 6410 6411 6412 6413 6414 6415 6416 6417 6418 6419 6420 6421 6422 6423 6424 6425 6426 6427 6428 6429 6430 6431 6432 6433 6434 6435 6436 6437 6438 6439 6440 6441 6442 6443 6444 6445 6446 6447 6448 6449 6450 6451 6452 6453 6454 6455 6456 6457 6458 6459 6460 6461 6462 6463 6464 6465 6466 6467 6468 6469 6470 6471 6472 6473 6474 6475 6476 6477 6478 6479 6480 6481 6482 6483 6484 6485 6486 6487 6488 6489 6490 6491 6492 6493 6494 6495 6496 6497 6498 6499 6500 6501 6502 6503 6504 6505 6506 6507 6508 6509 6510 6511 6512 6513 6514 6515 6516 6517 6518 6519 6520 6521 6522 6523 6524 6525 6526 6527 6528 6529 6530 6531 6532 6533 6534 6535 6536 6537 6538 6539 6540 6541 6542 6543 6544 6545 6546 6547 6548 6549 6550 6551 6552 6553 6554 6555 6556 6557 6558 6559 6560 6561 6562 6563 6564 6565 6566 6567 6568 6569 6570 6571 6572 6573 6574 6575 6576 6577 6578 6579 6580 6581 6582 6583 6584 6585 6586 6587 6588 6589 6590 6591 6592 6593 6594 6595 6596 6597 6598 6599 6600 6601 6602 6603 6604 6605 6606 6607 6608 6609 6610 6611 6612 6613 6614 6615 6616 6617 6618 6619 6620 6621 6622 6623 6624 6625 6626 6627 6628 6629 6630 6631 6632 6633 6634 6635 6636 6637 6638 6639 6640 6641 6642 6643 6644 6645 6646 6647 6648 6649 6650 6651 6652 6653 6654 6655 6656 6657 6658 6659 6660 6661 6662 6663 6664 6665 6666 6667 6668 6669 6670 6671 6672 6673 6674 6675 6676 6677 6678 6679 6680 6681 6682 6683 6684 6685 6686 6687 6688 6689 6690 6691 6692 6693 6694 6695 6696 6697 6698 6699 6700 6701 6702 6703 6704 6705 6706 6707 6708 6709 6710 6711 6712 6713 6714 6715 6716 6717 6718 6719 6720 6721 6722 6723 6724 6725 6726 6727 6728 6729 6730 6731 6732 6733 6734 6735 6736 6737 6738 6739 6740 6741 6742 6743 6744 6745 6746 6747 6748 6749 6750 6751 6752 6753 6754 6755 6756 6757 6758 6759 6760 6761 6762 6763 6764 6765 6766 6767 6768 6769 6770 6771 6772 6773 6774 6775 6776 6777 6778 6779 6780 6781 6782 6783 6784 6785 6786 6787 6788 6789 6790 6791 6792 6793 6794 6795 6796 6797 6798 6799 6800 6801 6802 6803 6804 6805 6806 6807 6808 6809 6810 6811 6812 6813 6814 6815 6816 6817 6818 6819 6820 6821 6822 6823 6824 6825 6826 6827 6828 6829 6830 6831 6832 6833 6834 6835 6836 6837 6838 6839 6840 6841 6842 6843 6844 6845 6846 6847 6848 6849 6850 6851 6852 6853 6854 6855 6856 6857 6858 6859 6860 6861 6862 6863 6864 6865 6866 6867 6868 6869 6870 6871 6872 6873 6874 6875 6876 6877 6878 6879 6880 6881 6882 6883 6884 6885 6886 6887 6888 6889 6890 6891 6892 6893 6894 6895 6896 6897 6898 6899 6900 6901 6902 6903 6904 6905 6906 6907 6908 6909 6910 6911 6912 6913 6914 6915 6916 6917 6918 6919 6920 6921 6922 6923 6924 6925 6926 6927 6928 6929 6930 6931 6932 6933 6934 6935 6936 6937 6938 6939 6940 6941 6942 6943 6944 6945 6946 6947 6948 6949 6950 6951 6952 6953 6954 6955 6956 6957 6958 6959 6960 6961 6962 6963 6964 6965 6966 6967 6968 6969 6970 6971 6972 6973 6974 6975 6976 6977 6978 6979 6980 6981 6982 6983 6984 6985 6986 6987 6988 6989 6990 6991 6992 6993 6994 6995 6996 6997 6998 6999 7000 7001 7002 7003 7004 7005 7006 7007 7008 7009 7010 7011 7012 7013 7014 7015 7016 7017 7018 7019 7020 7021 7022 7023 7024 7025 7026 7027 7028 7029 7030 7031 7032 7033 7034 7035 7036 7037 7038 7039 7040 7041 7042 7043 7044 7045 7046 7047 7048 7049 7050 7051 7052 7053 7054 7055 7056 7057 7058 7059 7060 7061 7062 7063 7064 7065 7066 7067 7068 7069 7070 7071 7072 7073 7074 7075 7076 7077 7078 7079 7080 7081 7082 7083 7084 7085 7086 7087 7088 7089 7090 7091 7092 7093 7094 7095 7096 7097 7098 7099 7100 7101 7102 7103 7104 7105 7106 7107 7108 7109 7110 7111 7112 7113 7114 7115 7116 7117 7118 7119 7120 7121 7122 7123 7124 7125 7126 7127 7128 7129 7130 7131 7132 7133 7134 7135 7136 7137 7138 7139 7140 7141 7142 7143 7144 7145 7146 7147 7148 7149 7150 7151 7152 7153 7154 7155 7156 7157 7158 7159 7160 7161 7162 7163 7164 7165 7166 7167 7168 7169 7170 7171 7172 7173 7174 7175 7176 7177 7178 7179 7180 7181 7182 7183 7184 7185 7186 7187 7188 7189 7190 7191 7192 7193 7194 7195 7196 7197 7198 7199 7200 7201 7202 7203 7204 7205 7206 7207 7208 7209 7210 7211 7212 7213 7214 7215 7216 7217 7218 7219 7220 7221 7222 7223 7224 7225 7226 7227 7228 7229 7230 7231 7232 7233 7234 7235 7236 7237 7238 7239 7240 7241 7242 7243 7244 7245 7246 7247 7248 7249 7250 7251 7252 7253 7254 7255 7256 7257 7258 7259 7260 7261 7262 7263 7264 7265 7266 7267 7268 7269 7270 7271 7272 7273 7274 7275 7276 7277 7278 7279 7280 7281 7282 7283 7284 7285 7286 7287 7288 7289 7290 7291 7292 7293 7294 7295 7296 7297 7298 7299 7300 7301 7302 7303 7304 7305 7306 7307 7308 7309 7310 7311 7312 7313 7314 7315 7316 7317 7318 7319 7320 7321 7322 7323 7324 7325 7326 7327 7328 7329 7330 7331 7332 7333 7334 7335 7336 7337 7338 7339 7340 7341 7342 7343 7344 7345 7346 7347 7348 7349 7350 7351 7352 7353 7354 7355 7356 7357 7358 7359 7360 7361 7362 7363 7364 7365 7366 7367 7368 7369 7370 7371 7372 7373 7374 7375 7376 7377 7378 7379 7380 7381 7382 7383 7384 7385 7386 7387 7388 7389 7390 7391 7392 7393 7394 7395 7396 7397 7398 7399 7400 7401 7402 7403 7404 7405 7406 7407 7408 7409 7410 7411 7412 7413 7414 7415 7416 7417 7418 7419 7420 7421 7422 7423 7424 7425 7426 7427 7428 7429 7430 7431 7432 7433 7434 7435 7436 7437 7438 7439 7440 7441 7442 7443 7444 7445 7446 7447 7448 7449 7450 7451 7452 7453 7454 7455 7456 7457 7458 7459 7460 7461 7462 7463 7464 7465 7466 7467 7468 7469 7470 7471 7472 7473 7474 7475 7476 7477 7478 7479 7480 7481 7482 7483 7484 7485 7486 7487 7488 7489 7490 7491 7492 7493 7494 7495 7496 7497 7498 7499 7500 7501 7502 7503 7504 7505 7506 7507 7508 7509 7510 7511 7512 7513 7514 7515 7516 7517 7518 7519 7520 7521 7522 7523 7524 7525 7526 7527 7528 7529 7530 7531 7532 7533 7534 7535 7536 7537 7538 7539 7540 7541 7542 7543 7544 7545 7546 7547 7548 7549 7550 7551 7552 7553 7554 7555 7556 7557 7558 7559 7560 7561 7562 7563 7564 7565 7566 7567 7568 7569 7570 7571 7572 7573 7574 7575 7576 7577 7578 7579 7580 7581 7582 7583 7584 7585 7586 7587 7588 7589 7590 7591 7592 7593 7594 7595 7596 7597 7598 7599 7600 7601 7602 7603 7604 7605 7606 7607 7608 7609 7610 7611 7612 7613 7614 7615 7616 7617 7618 7619 7620 7621 7622 7623 7624 7625 7626 7627 7628 7629 7630 7631 7632 7633 7634 7635 7636 7637 7638 7639 7640 7641 7642 7643 7644 7645 7646 7647 7648 7649 7650 7651 7652 7653 7654 7655 7656 7657 7658 7659 7660 7661 7662 7663 7664 7665 7666 7667 7668 7669 7670 7671 7672 7673 7674 7675 7676 7677 7678 7679 7680 7681 7682 7683 7684 7685 7686 7687 7688 7689 7690 7691 7692 7693 7694 7695 7696 7697 7698 7699 7700 7701 7702 7703 7704 7705 7706 7707 7708 7709 7710 7711 7712 7713 7714 7715 7716 7717 7718 7719 7720 7721 7722 7723 7724 7725 7726 7727 7728 7729 7730 7731 7732 7733 7734 7735 7736 7737 7738 7739 7740 7741 7742 7743 7744 7745 7746 7747 7748 7749 7750 7751 7752 7753 7754 7755 7756 7757 7758 7759 7760 7761 7762 7763 7764 7765 7766 7767 7768 7769 7770 7771 7772 7773 7774 7775 7776 7777 7778 7779 7780 7781 7782 7783 7784 7785 7786 7787 7788 7789 7790 7791 7792 7793 7794 7795 7796 7797 7798 7799 7800 7801 7802 7803 7804 7805 7806 7807 7808 7809 7810 7811 7812 7813 7814 7815 7816 7817 7818 7819 7820 7821 7822 7823 7824 7825 7826 7827 7828 7829 7830 7831 7832 7833 7834 7835 7836 7837 7838 7839 7840 7841 7842 7843 7844 7845 7846 7847 7848 7849 7850 7851 7852 7853 7854 7855 7856 7857 7858 7859 7860 7861 7862 7863 7864 7865 7866 7867 7868 7869 7870 7871 7872 7873 7874 7875 7876 7877 7878 7879 7880 7881 7882 7883 7884 7885 7886 7887 7888 7889 7890 7891 7892 7893 7894 7895 7896 7897 7898 7899 7900 7901 7902 7903 7904 7905 7906 7907 7908 7909 7910 7911 7912 7913 7914 7915 7916 7917 7918 7919 7920 7921 7922 7923 7924 7925 7926 7927 7928 7929 7930 7931 7932 7933 7934 7935 7936 7937 7938 7939 7940 7941 7942 7943 7944 7945 7946 7947 7948 7949 7950 7951 7952 7953 7954 7955 7956 7957 7958 7959 7960 7961 7962 7963 7964 7965 7966 7967 7968 7969 7970 7971 7972 7973 7974 7975 7976 7977 7978 7979 7980 7981 7982 7983 7984 7985 7986 7987 7988 7989 7990 7991 7992 7993 7994 7995 7996 7997 7998 7999 8000 8001 8002 8003 8004 8005 8006 8007 8008 8009 8010 8011 8012 8013 8014 8015 8016 8017 8018 8019 8020 8021 8022 8023 8024 8025 8026 8027 8028 8029 8030 8031 8032 8033 8034 8035 8036 8037 8038 8039 8040 8041 8042 8043 8044 8045 8046 8047 8048 8049 8050 8051 8052 8053 8054 8055 8056 8057 8058 8059 8060 8061 8062 8063 8064 8065 8066 8067 8068 8069 8070 8071 8072 8073 8074 8075 8076 8077 8078 8079 8080 8081 8082 8083 8084 8085 8086 8087 8088 8089 8090 8091 8092 8093 8094 8095 8096 8097 8098 8099 8100 8101 8102 8103 8104 8105 8106 8107 8108 8109 8110 8111 8112 8113 8114 8115 8116 8117 8118 8119 8120 8121 8122 8123 8124 8125 8126 8127 8128 8129 8130 8131 8132 8133 8134 8135 8136 8137 8138 8139 8140 8141 8142 8143 8144 8145 8146 8147 8148 8149 8150 8151 8152 8153 8154 8155 8156 8157 8158 8159 8160 8161 8162 8163 8164 8165 8166 8167 8168 8169 8170 8171 8172 8173 8174 8175 8176 8177 8178 8179 8180 8181 8182 8183 8184 8185 8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199 8200 8201 8202 8203 8204 8205 8206 8207 8208 8209 8210 8211 8212 8213 8214 8215 8216 8217 8218 8219 8220 8221 8222 8223 8224 8225 8226 8227 8228 8229 8230 8231 8232 8233 8234 8235 8236 8237 8238 8239 8240 8241 8242 8243 8244 8245 8246 8247 8248 8249 8250 8251 8252 8253 8254 8255 8256 8257 8258 8259 8260 8261 8262 8263 8264 8265 8266 8267 8268 8269 8270 8271 8272 8273 8274 8275 8276 8277 8278 8279 8280 8281 8282 8283 8284 8285 8286 8287 8288 8289 8290 8291 8292 8293 8294 8295 8296 8297 8298 8299 8300 8301 8302 8303 8304 8305 8306 8307 8308 8309 8310 8311 8312 8313 8314 8315 8316 8317 8318 8319 8320 8321 8322 8323 8324 8325 8326 8327 8328 8329 8330 8331 8332 8333 8334 8335 8336 8337 8338 8339 8340 8341 8342 8343 8344 8345 8346 8347 8348 8349 8350 8351 8352 8353 8354 8355 8356 8357 8358 8359 8360 8361 8362 8363 8364 8365 8366 8367 8368 8369 8370 8371 8372 8373 8374 8375 8376 8377 8378 8379 8380 8381 8382 8383 8384 8385 8386 8387 8388 8389 8390 8391 8392 8393 8394 8395 8396 8397 8398 8399 8400 8401 8402 8403 8404 8405 8406 8407 8408 8409 8410 8411 8412 8413 8414 8415 8416 8417 8418 8419 8420 8421 8422 8423 8424 8425 8426 8427 8428 8429 8430 8431 8432 8433 8434 8435 8436 8437 8438 8439 8440 8441 8442 8443 8444 8445 8446 8447 8448 8449 8450 8451 8452 8453 8454 8455 8456 8457 8458 8459 8460 8461 8462 8463 8464 8465 8466 8467 8468 8469 8470 8471 8472 8473 8474 8475 8476 8477 8478 8479 8480 8481 8482 8483 8484 8485 8486 8487 8488 8489 8490 8491 8492 8493 8494 8495 8496 8497 8498 8499 8500 8501 8502 8503 8504 8505 8506 8507 8508 8509 8510 8511 8512 8513 8514 8515 8516 8517 8518 8519 8520 8521 8522 8523 8524 8525 8526 8527 8528 8529 8530 8531 8532 8533 8534 8535 8536 8537 8538 8539 8540 8541 8542 8543 8544 8545 8546 8547 8548 8549 8550 8551 8552 8553 8554 8555 8556 8557 8558 8559 8560 8561 8562 8563 8564 8565 8566 8567 8568 8569 8570 8571 8572 8573 8574 8575 8576 8577 8578 8579 8580 8581 8582 8583 8584 8585 8586 8587 8588 8589 8590 8591 8592 8593 8594 8595 8596 8597 8598 8599 8600 8601 8602 8603 8604 8605 8606 8607 8608 8609 8610 8611 8612 8613 8614 8615 8616 8617 8618 8619 8620 8621 8622 8623 8624 8625 8626 8627 8628 8629 8630 8631 8632 8633 8634 8635 8636 8637 8638 8639 8640 8641 8642 8643 8644 8645 8646 8647 8648 8649 8650 8651 8652 8653 8654 8655 8656 8657 8658 8659 8660 8661 8662 8663 8664 8665 8666 8667 8668 8669 8670 8671 8672 8673 8674 8675 8676 8677 8678 8679 8680 8681 8682 8683 8684 8685 8686 8687 8688 8689 8690 8691 8692 8693 8694 8695 8696 8697 8698 8699 8700 8701 8702 8703 8704 8705 8706 8707 8708 8709 8710 8711 8712 8713 8714 8715 8716 8717 8718 8719 8720 8721 8722 8723 8724 8725 8726 8727 8728 8729 8730 8731 8732 8733 8734 8735 8736 8737 8738 8739 8740 8741 8742 8743 8744 8745 8746 8747 8748 8749 8750 8751 8752 8753 8754 8755 8756 8757 8758 8759 8760 8761 8762 8763 8764 8765 8766 8767 8768 8769 8770 8771 8772 8773 8774 8775 8776 8777 8778 8779 8780 8781 8782 8783 8784 8785 8786 8787 8788 8789 8790 8791 8792 8793 8794 8795 8796 8797 8798 8799 8800 8801 8802 8803 8804 8805 8806 8807 8808 8809 8810 8811 8812 8813 8814 8815 8816 8817 8818 8819 8820 8821 8822 8823 8824 8825 8826 8827 8828 8829 8830 8831 8832 8833 8834 8835 8836 8837 8838 8839 8840 8841 8842 8843 8844 8845 8846 8847 8848 8849 8850 8851 8852 8853 8854 8855 8856 8857 8858 8859 8860 8861 8862 8863 8864 8865 8866 8867 8868 8869 8870 8871 8872 8873 8874 8875 8876 8877 8878 8879 8880 8881 8882 8883 8884 8885 8886 8887 8888 8889 8890 8891 8892 8893 8894 8895 8896 8897 8898 8899 8900 8901 8902 8903 8904 8905 8906 8907 8908 8909 8910 8911 8912 8913 8914 8915 8916 8917 8918 8919 8920 8921 8922 8923 8924 8925 8926 8927 8928 8929 8930 8931 8932 8933 8934 8935 8936 8937 8938 8939 8940 8941 8942 8943 8944 8945 8946 8947 8948 8949 8950 8951 8952 8953 8954 8955 8956 8957 8958 8959 8960 8961 8962 8963 8964 8965 8966 8967 8968 8969 8970 8971 8972 8973 8974 8975 8976 8977 8978 8979 8980 8981 8982 8983 8984 8985 8986 8987 8988 8989 8990 8991 8992 8993 8994 8995 8996 8997 8998 8999 9000 9001 9002 9003 9004 9005 9006 9007 9008 9009 9010 9011 9012 9013 9014 9015 9016 9017 9018 9019 9020 9021 9022 9023 9024 9025 9026 9027 9028 9029 9030 9031 9032 9033 9034 9035 9036 9037 9038 9039 9040 9041 9042 9043 9044 9045 9046 9047 9048 9049 9050 9051 9052 9053 9054 9055 9056 9057 9058 9059 9060 9061 9062 9063 9064 9065 9066 9067 9068 9069 9070 9071 9072 9073 9074 9075 9076 9077 9078 9079 9080 9081 9082 9083 9084 9085 9086 9087 9088 9089 9090 9091 9092 9093 9094 9095 9096 9097 9098 9099 9100 9101 9102 9103 9104 9105 9106 9107 9108 9109 9110 9111 9112 9113 9114 9115 9116 9117 9118 9119 9120 9121 9122 9123 9124 9125 9126 9127 9128 9129 9130 9131 9132 9133 9134 9135 9136 9137 9138 9139 9140 9141 9142 9143 9144 9145 9146 9147 9148 9149 9150 9151 9152 9153 9154 9155 9156 9157 9158 9159 9160 9161 9162 9163 9164 9165 9166 9167 9168 9169 9170 9171 9172 9173 9174 9175 9176 9177 9178 9179 9180 9181 9182 9183 9184 9185 9186 9187 9188 9189 9190 9191 9192 9193 9194 9195 9196 9197 9198 9199 9200 9201 9202 9203 9204 9205 9206 9207 9208 9209 9210 9211 9212 9213 9214 9215 9216 9217 9218 9219 9220 9221 9222 9223 9224 9225 9226 9227 9228 9229 9230 9231 9232 9233 9234 9235 9236 9237 9238 9239 9240 9241 9242 9243 9244 9245 9246 9247 9248 9249 9250 9251 9252 9253 9254 9255 9256 9257 9258 9259 9260 9261 9262 9263 9264 9265 9266 9267 9268 9269 9270 9271 9272 9273 9274 9275 9276 9277 9278 9279 9280 9281 9282 9283 9284 9285 9286 9287 9288 9289 9290 9291 9292 9293 9294 9295 9296 9297 9298 9299 9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 9310 9311 9312 9313 9314 9315 9316 9317 9318 9319 9320 9321 9322 9323 9324 9325 9326 9327 9328 9329 9330 9331 9332 9333 9334 9335 9336 9337 9338 9339 9340 9341 9342 9343 9344 9345 9346 9347 9348 9349 9350 9351 9352 9353 9354 9355 9356 9357 9358 9359 9360 9361 9362 9363 9364 9365 9366 9367 9368 9369 9370 9371 9372 9373 9374 9375 9376 9377 9378 9379 9380 9381 9382 9383 9384 9385 9386 9387 9388 9389 9390 9391 9392 9393 9394 9395 9396 9397 9398 9399 9400 9401 9402 9403 9404 9405 9406 9407 9408 9409 9410 9411 9412 9413 9414 9415 9416 9417 9418 9419 9420 9421 9422 9423 9424 9425 9426 9427 9428 9429 9430 9431 9432 9433 9434 9435 9436 9437 9438 9439 9440 9441 9442 9443 9444 9445 9446 9447 9448 9449 9450 9451 9452 9453 9454 9455 9456 9457 9458 9459 9460 9461 9462 9463 9464 9465 9466 9467 9468 9469 9470 9471 9472 9473 9474 9475 9476 9477 9478 9479 9480 9481 9482 9483 9484 9485 9486 9487 9488 9489 9490 9491 9492 9493 9494 9495 9496 9497 9498 9499 9500 9501 9502 9503 9504 9505 9506 9507 9508 9509 9510 9511 9512 9513 9514 9515 9516 9517 9518 9519 9520 9521 9522 9523 9524 9525 9526 9527 9528 9529 9530 9531 9532 9533 9534 9535 9536 9537 9538 9539 9540 9541 9542 9543 9544 9545 9546 9547 9548 9549 9550 9551 9552 9553 9554 9555 9556 9557 9558 9559 9560 9561 9562 9563 9564 9565 9566 9567 9568 9569 9570 9571 9572 9573 9574 9575 9576 9577 9578 9579 9580 9581 9582 9583 9584 9585 9586 9587 9588 9589 9590 9591 9592 9593 9594 9595 9596 9597 9598 9599 9600 9601 9602 9603 9604 9605 9606 9607 9608 9609 9610 9611 9612 9613 9614 9615 9616 9617 9618 9619 9620 9621 9622 9623 9624 9625 9626 9627 9628 9629 9630 9631 9632 9633 9634 9635 9636 9637 9638 9639 9640 9641 9642 9643 9644 9645 9646 9647 9648 9649 9650 9651 9652 9653 9654 9655 9656 9657 9658 9659 9660 9661 9662 9663 9664 9665 9666 9667 9668 9669 9670 9671 9672 9673 9674 9675 9676 9677 9678 9679 9680 9681 9682 9683 9684 9685 9686 9687 9688 9689 9690 9691 9692 9693 9694 9695 9696 9697 9698 9699 9700 9701 9702 9703 9704 9705 9706 9707 9708 9709 9710 9711 9712 9713 9714 9715 9716 9717 9718 9719 9720 9721 9722 9723 9724 9725 9726 9727 9728 9729 9730 9731 9732 9733 9734 9735 9736 9737 9738 9739 9740 9741 9742 9743 9744 9745 9746 9747 9748 9749 9750 9751 9752 9753 9754 9755 9756 9757 9758 9759 9760 9761 9762 9763 9764 9765 9766 9767 9768 9769 9770 9771 9772 9773 9774 9775 9776 9777 9778 9779 9780 9781 9782 9783 9784 9785 9786 9787 9788 9789 9790 9791 9792 9793 9794 9795 9796 9797 9798 9799 9800 9801 9802 9803 9804 9805 9806 9807 9808 9809 9810 9811 9812 9813 9814 9815 9816 9817 9818 9819 9820 9821 9822 9823 9824 9825 9826 9827 9828 9829 9830 9831 9832 9833 9834 9835 9836 9837 9838 9839 9840 9841 9842 9843 9844 9845 9846 9847 9848 9849 9850 9851 9852 9853 9854 9855 9856 9857 9858 9859 9860 9861 9862 9863 9864 9865 9866 9867 9868 9869 9870 9871 9872 9873 9874 9875 9876 9877 9878 9879 9880 9881 9882 9883 9884 9885 9886 9887 9888 9889 9890 9891 9892 9893 9894 9895 9896 9897 9898 9899 9900 9901 9902 9903 9904 9905 9906 9907 9908 9909 9910 9911 9912 9913 9914 9915 9916 9917 9918 9919 9920 9921 9922 9923 9924 9925 9926 9927 9928 9929 9930 9931 9932 9933 9934 9935 9936 9937 9938 9939 9940 9941 9942 9943 9944 9945 9946 9947 9948 9949 9950 9951 9952 9953 9954 9955 9956 9957 9958 9959 9960 9961 9962 9963 9964 9965 9966 9967 9968 9969 9970 9971 9972 9973 9974 9975 9976 9977 9978 9979 9980 9981 9982 9983 9984 9985 9986 9987 9988 9989 9990 9991 9992 9993 9994 9995 9996 9997 9998 9999 10000 10001 10002 10003 10004 10005 10006 10007 10008 10009 10010 10011 10012 10013 10014 10015 10016 10017 10018 10019 10020 10021 10022 10023 10024 10025 10026 10027 10028 10029 10030 10031 10032 10033 10034 10035 10036 10037 10038 10039 10040 10041 10042 10043 10044 10045 10046 10047 10048 10049 10050 10051 10052 10053 10054 10055 10056 10057 10058 10059 10060 10061 10062 10063 10064 10065 10066 10067 10068 10069 10070 10071 10072 10073 10074 10075 10076 10077 10078 10079 10080 10081 10082 10083 10084 10085 10086 10087 10088 10089 10090 10091 10092 10093 10094 10095 10096 10097 10098 10099 10100 10101 10102 10103 10104 10105 10106 10107 10108 10109 10110 10111 10112 10113 10114 10115 10116 10117 10118 10119 10120 10121 10122 10123 10124 10125 10126 10127 10128 10129 10130 10131 10132 10133 10134 10135 10136 10137 10138 10139 10140 10141 10142 10143 10144 10145 10146 10147 10148 10149 10150 10151 10152 10153 10154 10155 10156 10157 10158 10159 10160 10161 10162 10163 10164 10165 10166 10167 10168 10169 10170 10171 10172 10173 10174 10175 10176 10177 10178 10179 10180 10181 10182 10183 10184 10185 10186 10187 10188 10189 10190 10191 10192 10193 10194 10195 10196 10197 10198 10199 10200 10201 10202 10203 10204 10205 10206 10207 10208 10209 10210 10211 10212 10213 10214 10215 10216 10217 10218 10219 10220 10221 10222 10223 10224 10225 10226 10227 10228 10229 10230 10231 10232 10233 10234 10235 10236 10237 10238 10239 10240 10241 10242 10243 10244 10245 10246 10247 10248 10249 10250 10251 10252 10253 10254 10255 10256 10257 10258 10259 10260 10261 10262 10263 10264 10265 10266 10267 10268 10269 10270 10271 10272 10273 10274 10275 10276 10277 10278 10279 10280 10281 10282 10283 10284 10285 10286 10287 10288 10289 10290 10291 10292 10293 10294 10295 10296 10297 10298 10299 10300 10301 10302 10303 10304 10305 10306 10307 10308 10309 10310 10311 10312 10313 10314 10315 10316 10317 10318 10319 10320 10321 10322 10323 10324 10325 10326 10327 10328 10329 10330 10331 10332 10333 10334 10335 10336 10337 10338 10339 10340 10341 10342 10343 10344 10345 10346 10347 10348 10349 10350 10351 10352 10353 10354 10355 10356 10357 10358 10359 10360 10361 10362 10363 10364 10365 10366 10367 10368 10369 10370 10371 10372 10373 10374 10375 10376 10377 10378 10379 10380 10381 10382 10383 10384 10385 10386 10387 10388 10389 10390 10391 10392 10393 10394 10395 10396 10397 10398 10399 10400 10401 10402 10403 10404 10405 10406 10407 10408 10409 10410 10411 10412 10413 10414 10415 10416 10417 10418 10419 10420 10421 10422 10423 10424 10425 10426 10427 10428 10429 10430 10431 10432 10433 10434 10435 10436 10437 10438 10439 10440 10441 10442 10443 10444 10445 10446 10447 10448 10449 10450 10451 10452 10453 10454 10455 10456 10457 10458 10459 10460 10461 10462 10463 10464 10465 10466 10467 10468 10469 10470 10471 10472 10473 10474 10475 10476 10477 10478 10479 10480 10481 10482 10483 10484 10485 10486 10487 10488 10489 10490 10491 10492 10493 10494 10495 10496 10497 10498 10499 10500 10501 10502 10503 10504 10505 10506 10507 10508 10509 10510 10511 10512 10513 10514 10515 10516 10517 10518 10519 10520 10521 10522 10523 10524 10525 10526 10527 10528 10529 10530 10531 10532 10533 10534 10535 10536 10537 10538 10539 10540 10541 10542 10543 10544 10545 10546 10547 10548 10549 10550 10551 10552 10553 10554 10555 10556 10557 10558 10559 10560 10561 10562 10563 10564 10565 10566 10567 10568 10569 10570 10571 10572 10573 10574 10575 10576 10577 10578 10579 10580 10581 10582 10583 10584 10585 10586 10587 10588 10589 10590 10591 10592 10593 10594 10595 10596 10597 10598 10599 10600 10601 10602 10603 10604 10605 10606 10607 10608 10609 10610 10611 10612 10613 10614 10615 10616 10617 10618 10619 10620 10621 10622 10623 10624 10625 10626 10627 10628 10629 10630 10631 10632 10633 10634 10635 10636 10637 10638 10639 10640 10641 10642 10643 10644 10645 10646 10647 10648 10649 10650 10651 10652 10653 10654 10655 10656 10657 10658 10659 10660 10661 10662 10663 10664 10665 10666 10667 10668 10669 10670 10671 10672 10673 10674 10675 10676 10677 10678 10679 10680 10681 10682 10683 10684 10685 10686 10687 10688 10689 10690 10691 10692 10693 10694 10695 10696 10697 10698 10699 10700 10701 10702 10703 10704 10705 10706 10707 10708 10709 10710 10711 10712 10713 10714 10715 10716 10717 10718 10719 10720 10721 10722 10723 10724 10725 10726 10727 10728 10729 10730 10731 10732 10733 10734 10735 10736 10737 10738 10739 10740 10741 10742 10743 10744 10745 10746 10747 10748 10749 10750 10751 10752 10753 10754 10755 10756 10757 10758 10759 10760 10761 10762 10763 10764 10765 10766 10767 10768 10769 10770 10771 10772 10773 10774 10775 10776 10777 10778 10779 10780 10781 10782 10783 10784 10785 10786 10787 10788 10789 10790 10791 10792 10793 10794 10795 10796 10797 10798 10799 10800 10801 10802 10803 10804 10805 10806 10807 10808 10809 10810 10811 10812 10813 10814 10815 10816 10817 10818 10819 10820 10821 10822 10823 10824 10825 10826 10827 10828 10829 10830 10831 10832 10833 10834 10835 10836 10837 10838 10839 10840 10841 10842 10843 10844 10845 10846 10847 10848 10849 10850 10851 10852 10853 10854 10855 10856 10857 10858 10859 10860 10861 10862 10863 10864 10865 10866 10867 10868 10869 10870 10871 10872 10873 10874 10875 10876 10877 10878 10879 10880 10881 10882 10883 10884 10885 10886 10887 10888 10889 10890 10891 10892 10893 10894 10895 10896 10897 10898 10899 10900 10901 10902 10903 10904 10905 10906 10907 10908 10909 10910 10911 10912 10913 10914 10915 10916 10917 10918 10919 10920 10921 10922 10923 10924 10925 10926 10927 10928 10929 10930 10931 10932 10933 10934 10935 10936 10937 10938 10939 10940 10941 10942 10943 10944 10945 10946 10947 10948 10949 10950 10951 10952 10953 10954 10955 10956 10957 10958 10959 10960 10961 10962 10963 10964 10965 10966 10967 10968 10969 10970 10971 10972 10973 10974 10975 10976 10977 10978 10979 10980 10981 10982 10983 10984 10985 10986 10987 10988 10989 10990 10991 10992 10993 10994 10995 10996 10997 10998 10999 11000 11001 11002 11003 11004 11005 11006 11007 11008 11009 11010 11011 11012 11013 11014 11015 11016 11017 11018 11019 11020 11021 11022 11023 11024 11025 11026 11027 11028 11029 11030 11031 11032 11033 11034 11035 11036 11037 11038 11039 11040 11041 11042 11043 11044 11045 11046 11047 11048 11049 11050 11051 11052 11053 11054 11055 11056 11057 11058 11059 11060 11061 11062 11063 11064 11065 11066 11067 11068 11069 11070 11071 11072 11073 11074 11075 11076 11077 11078 11079 11080 11081 11082 11083 11084 11085 11086 11087 11088 11089 11090 11091 11092 11093 11094 11095 11096 11097 11098 11099 11100 11101 11102 11103 11104 11105 11106 11107 11108 11109 11110 11111 11112 11113 11114 11115 11116 11117 11118 11119 11120 11121 11122 11123 11124 11125 11126 11127 11128 11129 11130 11131 11132 11133 11134 11135 11136 11137 11138 11139 11140 11141 11142 11143 11144 11145 11146 11147 11148 11149 11150 11151 11152 11153 11154 11155 11156 11157 11158 11159 11160 11161 11162 11163 11164 11165 11166 11167 11168 11169 11170 11171 11172 11173 11174 11175 11176 11177 11178 11179 11180 11181 11182 11183 11184 11185 11186 11187 11188 11189 11190 11191 11192 11193 11194 11195 11196 11197 11198 11199 11200 11201 11202 11203 11204 11205 11206 11207 11208 11209 11210 11211 11212 11213 11214 11215 11216 11217 11218 11219 11220 11221 11222 11223 11224 11225 11226 11227 11228 11229 11230 11231 11232 11233 11234 11235 11236 11237 11238 11239 11240 11241 11242 11243 11244 11245 11246 11247 11248 11249 11250 11251 11252 11253 11254 11255 11256 11257 11258 11259 11260 11261 11262 11263 11264 11265 11266 11267 11268 11269 11270 11271 11272 11273 11274 11275 11276 11277 11278 11279 11280 11281 11282 11283 11284 11285 11286 11287 11288 11289 11290 11291 11292 11293 11294 11295 11296 11297 11298 11299 11300 11301 11302 11303 11304 11305 11306 11307 11308 11309 11310 11311 11312 11313 11314 11315 11316 11317 11318 11319 11320 11321 11322 11323 11324 11325 11326 11327 11328 11329 11330 11331 11332 11333 11334 11335 11336 11337 11338 11339 11340 11341 11342 11343 11344 11345 11346 11347 11348 11349 11350 11351 11352 11353 11354 11355 11356 11357 11358 11359 11360 11361 11362 11363 11364 11365 11366 11367 11368 11369 11370 11371 11372 11373 11374 11375 11376 11377 11378 11379 11380 11381 11382 11383 11384 11385 11386 11387 11388 11389 11390 11391 11392 11393 11394 11395 11396 11397 11398 11399 11400 11401 11402 11403 11404 11405 11406 11407 11408 11409 11410 11411 11412 11413 11414 11415 11416 11417 11418 11419 11420 11421 11422 11423 11424 11425 11426 11427 11428 11429 11430 11431 11432 11433 11434 11435 11436 11437 11438 11439 11440 11441 11442 11443 11444 11445 11446 11447 11448 11449 11450 11451 11452 11453 11454 11455 11456 11457 11458 11459 11460 11461 11462 11463 11464 11465 11466 11467 11468 11469 11470 11471 11472 11473 11474 11475 11476 11477 11478 11479 11480 11481 11482 11483 11484 11485 11486 11487 11488 11489 11490 11491 11492 11493 11494 11495 11496 11497 11498 11499 11500 11501 11502 11503 11504 11505 11506 11507 11508 11509 11510 11511 11512 11513 11514 11515 11516 11517 11518 11519 11520 11521 11522 11523 11524 11525 11526 11527 11528 11529 11530 11531 11532 11533 11534 11535 11536 11537 11538 11539 11540 11541 11542 11543 11544 11545 11546 11547 11548 11549 11550 11551 11552 11553 11554 11555 11556 11557 11558 11559 11560 11561 11562 11563 11564 11565 11566 11567 11568 11569 11570 11571 11572 11573 11574 11575 11576 11577 11578 11579 11580 11581 11582 11583 11584 11585 11586 11587 11588 11589 11590 11591 11592 11593 11594 11595 11596 11597 11598 11599 11600 11601 11602 11603 11604 11605 11606 11607 11608 11609 11610 11611 11612 11613 11614 11615 11616 11617 11618 11619 11620 11621 11622 11623 11624 11625 11626 11627 11628 11629 11630 11631 11632 11633 11634 11635 11636 11637 11638 11639 11640 11641 11642 11643 11644 11645 11646 11647 11648 11649 11650 11651 11652 11653 11654 11655 11656 11657 11658 11659 11660 11661 11662 11663 11664 11665 11666 11667 11668 11669 11670 11671 11672 11673 11674 11675 11676 11677 11678 11679 11680 11681 11682 11683 11684 11685 11686 11687 11688 11689 11690 11691 11692 11693 11694 11695 11696 11697 11698 11699 11700 11701 11702 11703 11704 11705 11706 11707 11708 11709 11710 11711 11712 11713 11714 11715 11716 11717 11718 11719 11720 11721 11722 11723 11724 11725 11726 11727 11728 11729 11730 11731 11732 11733 11734 11735 11736 11737 11738 11739 11740 11741 11742 11743 11744 11745 11746 11747 11748 11749 11750 11751 11752 11753 11754 11755 11756 11757 11758 11759 11760 11761 11762 11763 11764 11765 11766 11767 11768 11769 11770 11771 11772 11773 11774 11775 11776 11777 11778 11779 11780 11781 11782 11783 11784 11785 11786 11787 11788 11789 11790 11791 11792 11793 11794 11795 11796 11797 11798 11799 11800 11801 11802 11803 11804 11805 11806 11807 11808 11809 11810 11811 11812 11813 11814 11815 11816 11817 11818 11819 11820 11821 11822 11823 11824 11825 11826 11827 11828 11829 11830 11831 11832 11833 11834 11835 11836 11837 11838 11839 11840 11841 11842 11843 11844 11845 11846 11847 11848 11849 11850 11851 11852 11853 11854 11855 11856 11857 11858 11859 11860 11861 11862 11863 11864 11865 11866 11867 11868 11869 11870 11871 11872 11873 11874 11875 11876 11877 11878 11879 11880 11881 11882 11883 11884 11885 11886 11887 11888 11889 11890 11891 11892 11893 11894 11895 11896 11897 11898 11899 11900 11901 11902 11903 11904 11905 11906 11907 11908 11909 11910 11911 11912 11913 11914 11915 11916 11917 11918 11919 11920 11921 11922 11923 11924 11925 11926 11927 11928 11929 11930 11931 11932 11933 11934 11935 11936 11937 11938 11939 11940 11941 11942 11943 11944 11945 11946 11947 11948 11949 11950 11951 11952 11953 11954 11955 11956 11957 11958 11959 11960 11961 11962 11963 11964 11965 11966 11967 11968 11969 11970 11971 11972 11973 11974 11975 11976 11977 11978 11979 11980 11981 11982 11983 11984 11985 11986 11987 11988 11989 11990 11991 11992 11993 11994 11995 11996 11997 11998 11999 12000 12001 12002 12003 12004 12005 12006 12007 12008 12009 12010 12011 12012 12013 12014 12015 12016 12017 12018 12019 12020 12021 12022 12023 12024 12025 12026 12027 12028 12029 12030 12031 12032 12033 12034 12035 12036 12037 12038 12039 12040 12041 12042 12043 12044 12045 12046 12047 12048 12049 12050 12051 12052 12053 12054 12055 12056 12057 12058 12059 12060 12061 12062 12063 12064 12065 12066 12067 12068 12069 12070 12071 12072 12073 12074 12075 12076 12077 12078 12079 12080 12081 12082 12083 12084 12085 12086 12087 12088 12089 12090 12091 12092 12093 12094 12095 12096 12097 12098 12099 12100 12101 12102 12103 12104 12105 12106 12107 12108 12109 12110 12111 12112 12113 12114 12115 12116 12117 12118 12119 12120 12121 12122 12123 12124 12125 12126 12127 12128 12129 12130 12131 12132 12133 12134 12135 12136 12137 12138 12139 12140 12141 12142 12143 12144 12145 12146 12147 12148 12149 12150 12151 12152 12153 12154 12155 12156 12157 12158 12159 12160 12161 12162 12163 12164 12165 12166 12167 12168 12169 12170 12171 12172 12173 12174 12175 12176 12177 12178 12179 12180 12181 12182 12183 12184 12185 12186 12187 12188 12189 12190 12191 12192 12193 12194 12195 12196 12197 12198 12199 12200 12201 12202 12203 12204 12205 12206 12207 12208 12209 12210 12211 12212 12213 12214 12215 12216 12217 12218 12219 12220 12221 12222 12223 12224 12225 12226 12227 12228 12229 12230 12231 12232 12233 12234 12235 12236 12237 12238 12239 12240 12241 12242 12243 12244 12245 12246 12247 12248 12249 12250 12251 12252 12253 12254 12255 12256 12257 12258 12259 12260 12261 12262 12263 12264 12265 12266 12267 12268 12269 12270 12271 12272 12273 12274 12275 12276 12277 12278 12279 12280 12281 12282 12283 12284 12285 12286 12287 12288 12289 12290 12291 12292 12293 12294 12295 12296 12297 12298 12299 12300 12301 12302 12303 12304 12305 12306 12307 12308 12309 12310 12311 12312 12313 12314 12315 12316 12317 12318 12319 12320 12321 12322 12323 12324 12325 12326 12327 12328 12329 12330 12331 12332 12333 12334 12335 12336 12337 12338 12339 12340 12341 12342 12343 12344 12345 12346 12347 12348 12349 12350 12351 12352 12353 12354 12355 12356 12357 12358 12359 12360 12361 12362 12363 12364 12365 12366 12367 12368 12369 12370 12371 12372 12373 12374 12375 12376 12377 12378 12379 12380 12381 12382 12383 12384 12385 12386 12387 12388 12389 12390 12391 12392 12393 12394 12395 12396 12397 12398 12399 12400 12401 12402 12403 12404 12405 12406 12407 12408 12409 12410 12411 12412 12413 12414 12415 12416 12417 12418 12419 12420 12421 12422 12423 12424 12425 12426 12427 12428 12429 12430 12431 12432 12433 12434 12435 12436 12437 12438 12439 12440 12441 12442 12443 12444 12445 12446 12447 12448 12449 12450 12451 12452 12453 12454 12455 12456 12457 12458 12459 12460 12461 12462 12463 12464 12465 12466 12467 12468 12469 12470 12471 12472 12473 12474 12475 12476 12477 12478 12479 12480 12481 12482 12483 12484 12485 12486 12487 12488 12489 12490 12491 12492 12493 12494 12495 12496 12497 12498 12499 12500 12501 12502 12503 12504 12505 12506 12507 12508 12509 12510 12511 12512 12513 12514 12515 12516 12517 12518 12519 12520 12521 12522 12523 12524 12525 12526 12527 12528 12529 12530 12531 12532 12533 12534 12535 12536 12537 12538 12539 12540 12541 12542 12543 12544 12545 12546 12547 12548 12549 12550 12551 12552 12553 12554 12555 12556 12557 12558 12559 12560 12561 12562 12563 12564 12565 12566 12567 12568 12569 12570 12571 12572 12573 12574 12575 12576 12577 12578 12579 12580 12581 12582 12583 12584 12585 12586 12587 12588 12589 12590 12591 12592 12593 12594 12595 12596 12597 12598 12599 12600 12601 12602 12603 12604 12605 12606 12607 12608 12609 12610 12611 12612 12613 12614 12615 12616 12617 12618 12619 12620 12621 12622 12623 12624 12625 12626 12627 12628 12629 12630 12631 12632 12633 12634 12635 12636 12637 12638 12639 12640 12641 12642 12643 12644 12645 12646 12647 12648 12649 12650 12651 12652 12653 12654 12655 12656 12657 12658 12659 12660 12661 12662 12663 12664 12665 12666 12667 12668 12669 12670 12671 12672 12673 12674 12675 12676 12677 12678 12679 12680 12681 12682 12683 12684 12685 12686 12687 12688 12689 12690 12691 12692 12693 12694 12695 12696 12697 12698 12699 12700 12701 12702 12703 12704 12705 12706 12707 12708 12709 12710 12711 12712 12713 12714 12715 12716 12717 12718 12719 12720 12721 12722 12723 12724 12725 12726 12727 12728 12729 12730 12731 12732 12733 12734 12735 12736 12737 12738 12739 12740 12741 12742 12743 12744 12745 12746 12747 12748 12749 12750 12751 12752 12753 12754 12755 12756 12757 12758 12759 12760 12761 12762 12763 12764 12765 12766 12767 12768 12769 12770 12771 12772 12773 12774 12775 12776 12777 12778 12779 12780 12781 12782 12783 12784 12785 12786 12787 12788 12789 12790 12791 12792 12793 12794 12795 12796 12797 12798 12799 12800 12801 12802 12803 12804 12805 12806 12807 12808 12809 12810 12811 12812 12813 12814 12815 12816 12817 12818 12819 12820 12821 12822 12823 12824 12825 12826 12827 12828 12829 12830 12831 12832 12833 12834 12835 12836 12837 12838 12839 12840 12841 12842 12843 12844 12845 12846 12847 12848 12849 12850 12851 12852 12853 12854 12855 12856 12857 12858 12859 12860 12861 12862 12863 12864 12865 12866 12867 12868 12869 12870 12871 12872 12873 12874 12875 12876 12877 12878 12879 12880 12881 12882 12883 12884 12885 12886 12887 12888 12889 12890 12891 12892 12893 12894 12895 12896 12897 12898 12899 12900 12901 12902 12903 12904 12905 12906 12907 12908 12909 12910 12911 12912 12913 12914 12915 12916 12917 12918 12919 12920 12921 12922 12923 12924 12925 12926 12927 12928 12929 12930 12931 12932 12933 12934 12935 12936 12937 12938 12939 12940 12941 12942 12943 12944 12945 12946 12947 12948 12949 12950 12951 12952 12953 12954 12955 12956 12957 12958 12959 12960 12961 12962 12963 12964 12965 12966 12967 12968 12969 12970 12971 12972 12973 12974 12975 12976 12977 12978 12979 12980 12981 12982 12983 12984 12985 12986 12987 12988 12989 12990 12991 12992 12993 12994 12995 12996 12997 12998 12999 13000 13001 13002 13003 13004 13005 13006 13007 13008 13009 13010 13011 13012 13013 13014 13015 13016 13017 13018 13019 13020 13021 13022 13023 13024 13025 13026 13027 13028 13029 13030 13031 13032 13033 13034 13035 13036 13037 13038 13039 13040 13041 13042 13043 13044 13045 13046 13047 13048 13049 13050 13051 13052 13053 13054 13055 13056 13057 13058 13059 13060 13061 13062 13063 13064 13065 13066 13067 13068 13069 13070 13071 13072 13073 13074 13075 13076 13077 13078 13079 13080 13081 13082 13083 13084 13085 13086 13087 13088 13089 13090 13091 13092 13093 13094 13095 13096 13097 13098 13099 13100 13101 13102 13103 13104 13105 13106 13107 13108 13109 13110 13111 13112 13113 13114 13115 13116 13117 13118 13119 13120 13121 13122 13123 13124 13125 13126 13127 13128 13129 13130 13131 13132 13133 13134 13135 13136 13137 13138 13139 13140 13141 13142 13143 13144 13145 13146 13147 13148 13149 13150 13151 13152 13153 13154 13155 13156 13157 13158 13159 13160 13161 13162 13163 13164 13165 13166 13167 13168 13169 13170 13171 13172 13173 13174 13175 13176 13177 13178 13179 13180 13181 13182 13183 13184 13185 13186 13187 13188 13189 13190 13191 13192 13193 13194 13195 13196 13197 13198 13199 13200 13201 13202 13203 13204 13205 13206 13207 13208 13209 13210 13211 13212 13213 13214 13215 13216 13217 13218 13219 13220 13221 13222 13223 13224 13225 13226 13227 13228 13229 13230 13231 13232 13233 13234 13235 13236 13237 13238 13239 13240 13241 13242 13243 13244 13245 13246 13247 13248 13249 13250 13251 13252 13253 13254 13255 13256 13257 13258 13259 13260 13261 13262 13263 13264 13265 13266 13267 13268 13269 13270 13271 13272 13273 13274 13275 13276 13277 13278 13279 13280 13281 13282 13283 13284 13285 13286 13287 13288 13289 13290 13291 13292 13293 13294 13295 13296 13297 13298 13299 13300 13301 13302 13303 13304 13305 13306 13307 13308 13309 13310 13311 13312 13313 13314 13315 13316 13317 13318 13319 13320 13321 13322 13323 13324 13325 13326 13327 13328 13329 13330 13331 13332 13333 13334 13335 13336 13337 13338 13339 13340 13341 13342 13343 13344 13345 13346 13347 13348 13349 13350 13351 13352 13353 13354 13355 13356 13357 13358 13359 13360 13361 13362 13363 13364 13365 13366 13367 13368 13369 13370 13371 13372 13373 13374 13375 13376 13377 13378 13379 13380 13381 13382 13383 13384 13385 13386 13387 13388 13389 13390 13391 13392 13393 13394 13395 13396 13397 13398 13399 13400 13401 13402 13403 13404 13405 13406 13407 13408 13409 13410 13411 13412 13413 13414 13415 13416 13417 13418 13419 13420 13421 13422 13423 13424 13425 13426 13427 13428 13429 13430 13431 13432 13433 13434 13435 13436 13437 13438 13439 13440 13441 13442 13443 13444 13445 13446 13447 13448 13449 13450 13451 13452 13453 13454 13455 13456 13457 13458 13459 13460 13461 13462 13463 13464 13465 13466 13467 13468 13469 13470 13471 13472 13473 13474 13475 13476 13477 13478 13479 13480 13481 13482 13483 13484 13485 13486 13487 13488 13489 13490 13491 13492 13493 13494 13495 13496 13497 13498 13499 13500 13501 13502 13503 13504 13505 13506 13507 13508 13509 13510 13511 13512 13513 13514 13515 13516 13517 13518 13519 13520 13521 13522 13523 13524 13525 13526 13527 13528 13529 13530 13531 13532 13533 13534 13535 13536 13537 13538 13539 13540 13541 13542 13543 13544 13545 13546 13547 13548 13549 13550 13551 13552 13553 13554 13555 13556 13557 13558 13559 13560 13561 13562 13563 13564 13565 13566 13567 13568 13569 13570 13571 13572 13573 13574 13575 13576 13577 13578 13579 13580 13581 13582 13583 13584 13585 13586 13587 13588 13589 13590 13591 13592 13593 13594 13595 13596 13597 13598 13599 13600 13601 13602 13603 13604 13605 13606 13607 13608 13609 13610 13611 13612 13613 13614 13615 13616 13617 13618 13619 13620 13621 13622 13623 13624 13625 13626 13627 13628 13629 13630 13631 13632 13633 13634 13635 13636 13637 13638 13639 13640 13641 13642 13643 13644 13645 13646 13647 13648 13649 13650 13651 13652 13653 13654 13655 13656 13657 13658 13659 13660 13661 13662 13663 13664 13665 13666 13667 13668 13669 13670 13671 13672 13673 13674 13675 13676 13677 13678 13679 13680 13681 13682 13683 13684 13685 13686 13687 13688 13689 13690 13691 13692 13693 13694 13695 13696 13697 13698 13699 13700 13701 13702 13703 13704 13705 13706 13707 13708 13709 13710 13711 13712 13713 13714 13715 13716 13717 13718 13719 13720 13721 13722 13723 13724 13725 13726 13727 13728 13729 13730 13731 13732 13733 13734 13735 13736 13737 13738 13739 13740 13741 13742 13743 13744 13745 13746 13747 13748 13749 13750 13751 13752 13753 13754 13755 13756 13757 13758 13759 13760 13761 13762 13763 13764 13765 13766 13767 13768 13769 13770 13771 13772 13773 13774 13775 13776 13777 13778 13779 13780 13781 13782 13783 13784 13785 13786 13787 13788 13789 13790 13791 13792 13793 13794 13795 13796 13797 13798 13799 13800 13801 13802 13803 13804 13805 13806 13807 13808 13809 13810 13811 13812 13813 13814 13815 13816 13817 13818 13819 13820 13821 13822 13823 13824 13825 13826 13827 13828 13829 13830 13831 13832 13833 13834 13835 13836 13837 13838 13839 13840 13841 13842 13843 13844 13845 13846 13847 13848 13849 13850 13851 13852 13853 13854 13855 13856 13857 13858 13859 13860 13861 13862 13863 13864 13865 13866 13867 13868 13869 13870 13871 13872 13873 13874 13875 13876 13877 13878 13879 13880 13881 13882 13883 13884 13885 13886 13887 13888 13889 13890 13891 13892 13893 13894 13895 13896 13897 13898 13899 13900 13901 13902 13903 13904 13905 13906 13907 13908 13909 13910 13911 13912 13913 13914 13915 13916 13917 13918 13919 13920 13921 13922 13923 13924 13925 13926 13927 13928 13929 13930 13931 13932 13933 13934 13935 13936 13937 13938 13939 13940 13941 13942 13943 13944 13945 13946 13947 13948 13949 13950 13951 13952 13953 13954 13955 13956 13957 13958 13959 13960 13961 13962 13963 13964 13965 13966 13967 13968 13969 13970 13971 13972 13973 13974 13975 13976 13977 13978 13979 13980 13981 13982 13983 13984 13985 13986 13987 13988 13989 13990 13991 13992 13993 13994 13995 13996 13997 13998 13999 14000 14001 14002 14003 14004 14005 14006 14007 14008 14009 14010 14011 14012 14013 14014 14015 14016 14017 14018 14019 14020 14021 14022 14023 14024 14025 14026 14027 14028 14029 14030 14031 14032 14033 14034 14035 14036 14037 14038 14039 14040 14041 14042 14043 14044 14045 14046 14047 14048 14049 14050 14051 14052 14053 14054 14055 14056 14057 14058 14059 14060 14061 14062 14063 14064 14065 14066 14067 14068 14069 14070 14071 14072 14073 14074 14075 14076 14077 14078 14079 14080 14081 14082 14083 14084 14085 14086 14087 14088 14089 14090 14091 14092 14093 14094 14095 14096 14097 14098 14099 14100 14101 14102 14103 14104 14105 14106 14107 14108 14109 14110 14111 14112 14113 14114 14115 14116 14117 14118 14119 14120 14121 14122 14123 14124 14125 14126 14127 14128 14129 14130 14131 14132 14133 14134 14135 14136 14137 14138 14139 14140 14141 14142 14143 14144 14145 14146 14147 14148 14149 14150 14151 14152 14153 14154 14155 14156 14157 14158 14159 14160 14161 14162 14163 14164 14165 14166 14167 14168 14169 14170 14171 14172 14173 14174 14175 14176 14177 14178 14179 14180 14181 14182 14183 14184 14185 14186 14187 14188 14189 14190 14191 14192 14193 14194 14195 14196 14197 14198 14199 14200 14201 14202 14203 14204 14205 14206 14207 14208 14209 14210 14211 14212 14213 14214 14215 14216 14217 14218 14219 14220 14221 14222 14223 14224 14225 14226 14227 14228 14229 14230 14231 14232 14233 14234 14235 14236 14237 14238 14239 14240 14241 14242 14243 14244 14245 14246 14247 14248 14249 14250 14251 14252 14253 14254 14255 14256 14257 14258 14259 14260 14261 14262 14263 14264 14265 14266 14267 14268 14269 14270 14271 14272 14273 14274 14275 14276 14277 14278 14279 14280 14281 14282 14283 14284 14285 14286 14287 14288 14289 14290 14291 14292 14293 14294 14295 14296 14297 14298 14299 14300 14301 14302 14303 14304 14305 14306 14307 14308 14309 14310 14311 14312 14313 14314 14315 14316 14317 14318 14319 14320 14321 14322 14323 14324 14325 14326 14327 14328 14329 14330 14331 14332 14333 14334 14335 14336 14337 14338 14339 14340 14341 14342 14343 14344 14345 14346 14347 14348 14349 14350 14351 14352 14353 14354 14355 14356 14357 14358 14359 14360 14361 14362 14363 14364 14365 14366 14367 14368 14369 14370 14371 14372 14373 14374 14375 14376 14377 14378 14379 14380 14381 14382 14383 14384 14385 14386 14387 14388 14389 14390 14391 14392 14393 14394 14395 14396 14397 14398 14399 14400 14401 14402 14403 14404 14405 14406 14407 14408 14409 14410 14411 14412 14413 14414 14415 14416 14417 14418 14419 14420 14421 14422 14423 14424 14425 14426 14427 14428 14429 14430 14431 14432 14433 14434 14435 14436 14437 14438 14439 14440 14441 14442 14443 14444 14445 14446 14447 14448 14449 14450 14451 14452 14453 14454 14455 14456 14457 14458 14459 14460 14461 14462 14463 14464 14465 14466 14467 14468 14469 14470 14471 14472 14473 14474 14475 14476 14477 14478 14479 14480 14481 14482 14483 14484 14485 14486 14487 14488 14489 14490 14491 14492 14493 14494 14495 14496 14497 14498 14499 14500 14501 14502 14503 14504 14505 14506 14507 14508 14509 14510 14511 14512 14513 14514 14515 14516 14517 14518 14519 14520 14521 14522 14523 14524 14525 14526 14527 14528 14529 14530 14531 14532 14533 14534 14535 14536 14537 14538 14539 14540 14541 14542 14543 14544 14545 14546 14547 14548 14549 14550 14551 14552 14553 14554 14555 14556 14557 14558 14559 14560 14561 14562 14563 14564 14565 14566 14567 14568 14569 14570 14571 14572 14573 14574 14575 14576 14577 14578 14579 14580 14581 14582 14583 14584 14585 14586 14587 14588 14589 14590 14591 14592 14593 14594 14595 14596 14597 14598 14599 14600 14601 14602 14603 14604 14605 14606 14607 14608 14609 14610 14611 14612 14613 14614 14615 14616 14617 14618 14619 14620 14621 14622 14623 14624 14625 14626 14627 14628 14629 14630 14631 14632 14633 14634 14635 14636 14637 14638 14639 14640 14641 14642 14643 14644 14645 14646 14647 14648 14649 14650 14651 14652 14653 14654 14655 14656 14657 14658 14659 14660 14661 14662 14663 14664 14665 14666 14667 14668 14669 14670 14671 14672 14673 14674 14675 14676 14677 14678 14679 14680 14681 14682 14683 14684 14685 14686 14687 14688 14689 14690 14691 14692 14693 14694 14695 14696 14697 14698 14699 14700 14701 14702 14703 14704 14705 14706 14707 14708 14709 14710 14711 14712 14713 14714 14715 14716 14717 14718 14719 14720 14721 14722 14723 14724 14725 14726 14727 14728 14729 14730 14731 14732 14733 14734 14735 14736 14737 14738 14739 14740 14741 14742 14743 14744 14745 14746 14747 14748 14749 14750 14751 14752 14753 14754 14755 14756 14757 14758 14759 14760 14761 14762 14763 14764 14765 14766 14767 14768 14769 14770 14771 14772 14773 14774 14775 14776 14777 14778 14779 14780 14781 14782 14783 14784 14785 14786 14787 14788 14789 14790 14791 14792 14793 14794 14795 14796 14797 14798 14799 14800 14801 14802 14803 14804 14805 14806 14807 14808 14809 14810 14811 14812 14813 14814 14815 14816 14817 14818 14819 14820 14821 14822 14823 14824 14825 14826 14827 14828 14829 14830 14831 14832 14833 14834 14835 14836 14837 14838 14839 14840 14841 14842 14843 14844 14845 14846 14847 14848 14849 14850 14851 14852 14853 14854 14855 14856 14857 14858 14859 14860 14861 14862 14863 14864 14865 14866 14867 14868 14869 14870 14871 14872 14873 14874 14875 14876 14877 14878 14879 14880 14881 14882 14883 14884 14885 14886 14887 14888 14889 14890 14891 14892 14893 14894 14895 14896 14897 14898 14899 14900 14901 14902 14903 14904 14905 14906 14907 14908 14909 14910 14911 14912 14913 14914 14915 14916 14917 14918 14919 14920 14921 14922 14923 14924 14925 14926 14927 14928 14929 14930 14931 14932 14933 14934 14935 14936 14937 14938 14939 14940 14941 14942 14943 14944 14945 14946 14947 14948 14949 14950 14951 14952 14953 14954 14955 14956 14957 14958 14959 14960 14961 14962 14963 14964 14965 14966 14967 14968 14969 14970 14971 14972 14973 14974 14975 14976 14977 14978 14979 14980 14981 14982 14983 14984 14985 14986 14987 14988 14989 14990 14991 14992 14993 14994 14995 14996 14997 14998 14999 15000 15001 15002 15003 15004 15005 15006 15007 15008 15009 15010 15011 15012 15013 15014 15015 15016 15017 15018 15019 15020 15021 15022 15023 15024 15025 15026 15027 15028 15029 15030 15031 15032 15033 15034 15035 15036 15037 15038 15039 15040 15041 15042 15043 15044 15045 15046 15047 15048 15049 15050 15051 15052 15053 15054 15055 
/*
  Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
  All rights reserved.

  Redistribution and use in source and binary forms, with or without
  modification, are permitted provided that the following conditions are met:

  * Redistributions of source code must retain the above copyright notice,
    this list of conditions and the following disclaimer.
  * Redistributions in binary form must reproduce the above copyright notice,
    this list of conditions and the following disclaimer in the documentation
	and/or other materials provided with the distribution.
  * Neither the name of Trident Microsystems nor Hauppauge Computer Works
    nor the names of its contributors may be used to endorse or promote
	products derived from this software without specific prior written
	permission.

  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  POSSIBILITY OF SUCH DAMAGE.
*/

/*
 ***********************************************************************************************************************
 * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE
 *
 * Filename:        drxj_map.h
 * Generated on:    Mon Jan 18 12:09:24 2010
 * Generated by:    IDF:x 1.3.0
 * Generated from:  reg_map
 * Output start:    [entry point]
 *
 * filename         last modified               re-use
 * -----------------------------------------------------
 * reg_map.1.tmp    Mon Jan 18 12:09:24 2010    -
 *
 */

#ifndef __DRXJ_MAP__H__
#define __DRXJ_MAP__H__ INCLUDED

#ifdef _REGISTERTABLE_
#include <registertable.h>
	extern register_table_t drxj_map[];
	extern register_table_info_t drxj_map_info[];
#endif

#define ATV_COMM_EXEC__A                                                    0xC00000
#define ATV_COMM_EXEC__W                                                    2
#define ATV_COMM_EXEC__M                                                    0x3
#define ATV_COMM_EXEC__PRE                                                  0x0
#define   ATV_COMM_EXEC_STOP                                                0x0
#define   ATV_COMM_EXEC_ACTIVE                                              0x1
#define   ATV_COMM_EXEC_HOLD                                                0x2

#define ATV_COMM_STATE__A                                                   0xC00001
#define ATV_COMM_STATE__W                                                   16
#define ATV_COMM_STATE__M                                                   0xFFFF
#define ATV_COMM_STATE__PRE                                                 0x0
#define ATV_COMM_MB__A                                                      0xC00002
#define ATV_COMM_MB__W                                                      16
#define ATV_COMM_MB__M                                                      0xFFFF
#define ATV_COMM_MB__PRE                                                    0x0
#define ATV_COMM_INT_REQ__A                                                 0xC00003
#define ATV_COMM_INT_REQ__W                                                 16
#define ATV_COMM_INT_REQ__M                                                 0xFFFF
#define ATV_COMM_INT_REQ__PRE                                               0x0
#define   ATV_COMM_INT_REQ_COMM_INT_REQ__B                                  0
#define   ATV_COMM_INT_REQ_COMM_INT_REQ__W                                  1
#define   ATV_COMM_INT_REQ_COMM_INT_REQ__M                                  0x1
#define   ATV_COMM_INT_REQ_COMM_INT_REQ__PRE                                0x0

#define ATV_COMM_INT_STA__A                                                 0xC00005
#define ATV_COMM_INT_STA__W                                                 16
#define ATV_COMM_INT_STA__M                                                 0xFFFF
#define ATV_COMM_INT_STA__PRE                                               0x0
#define ATV_COMM_INT_MSK__A                                                 0xC00006
#define ATV_COMM_INT_MSK__W                                                 16
#define ATV_COMM_INT_MSK__M                                                 0xFFFF
#define ATV_COMM_INT_MSK__PRE                                               0x0
#define ATV_COMM_INT_STM__A                                                 0xC00007
#define ATV_COMM_INT_STM__W                                                 16
#define ATV_COMM_INT_STM__M                                                 0xFFFF
#define ATV_COMM_INT_STM__PRE                                               0x0

#define ATV_COMM_KEY__A                                                     0xC0000F
#define ATV_COMM_KEY__W                                                     16
#define ATV_COMM_KEY__M                                                     0xFFFF
#define ATV_COMM_KEY__PRE                                                   0x0
#define   ATV_COMM_KEY_KEY                                                  0xFABA
#define   ATV_COMM_KEY_MIN                                                  0x0
#define   ATV_COMM_KEY_MAX                                                  0xFFFF

#define ATV_TOP_COMM_EXEC__A                                                0xC10000
#define ATV_TOP_COMM_EXEC__W                                                2
#define ATV_TOP_COMM_EXEC__M                                                0x3
#define ATV_TOP_COMM_EXEC__PRE                                              0x0
#define   ATV_TOP_COMM_EXEC_STOP                                            0x0
#define   ATV_TOP_COMM_EXEC_ACTIVE                                          0x1
#define   ATV_TOP_COMM_EXEC_HOLD                                            0x2

#define ATV_TOP_COMM_STATE__A                                               0xC10001
#define ATV_TOP_COMM_STATE__W                                               16
#define ATV_TOP_COMM_STATE__M                                               0xFFFF
#define ATV_TOP_COMM_STATE__PRE                                             0x0
#define   ATV_TOP_COMM_STATE_STATE__B                                       0
#define   ATV_TOP_COMM_STATE_STATE__W                                       16
#define   ATV_TOP_COMM_STATE_STATE__M                                       0xFFFF
#define   ATV_TOP_COMM_STATE_STATE__PRE                                     0x0

#define ATV_TOP_COMM_MB__A                                                  0xC10002
#define ATV_TOP_COMM_MB__W                                                  16
#define ATV_TOP_COMM_MB__M                                                  0xFFFF
#define ATV_TOP_COMM_MB__PRE                                                0x0
#define   ATV_TOP_COMM_MB_CTL__B                                            0
#define   ATV_TOP_COMM_MB_CTL__W                                            1
#define   ATV_TOP_COMM_MB_CTL__M                                            0x1
#define   ATV_TOP_COMM_MB_CTL__PRE                                          0x0
#define   ATV_TOP_COMM_MB_OBS__B                                            1
#define   ATV_TOP_COMM_MB_OBS__W                                            1
#define   ATV_TOP_COMM_MB_OBS__M                                            0x2
#define   ATV_TOP_COMM_MB_OBS__PRE                                          0x0

#define   ATV_TOP_COMM_MB_MUX_CTRL__B                                       2
#define   ATV_TOP_COMM_MB_MUX_CTRL__W                                       4
#define   ATV_TOP_COMM_MB_MUX_CTRL__M                                       0x3C
#define   ATV_TOP_COMM_MB_MUX_CTRL__PRE                                     0x0
#define     ATV_TOP_COMM_MB_MUX_CTRL_PEAK_S                                 0x0
#define     ATV_TOP_COMM_MB_MUX_CTRL_VID_GAIN                               0x4
#define     ATV_TOP_COMM_MB_MUX_CTRL_CORR_O                                 0x8
#define     ATV_TOP_COMM_MB_MUX_CTRL_CR_ROT_O                               0xC
#define     ATV_TOP_COMM_MB_MUX_CTRL_CR_IIR_IQ                              0x10
#define     ATV_TOP_COMM_MB_MUX_CTRL_VIDEO_O                                0x14
#define     ATV_TOP_COMM_MB_MUX_CTRL_SIF_O                                  0x18
#define     ATV_TOP_COMM_MB_MUX_CTRL_SIF2025_O                              0x1C
#define     ATV_TOP_COMM_MB_MUX_CTRL_POST_S                                 0x20

#define   ATV_TOP_COMM_MB_MUX_OBS__B                                        6
#define   ATV_TOP_COMM_MB_MUX_OBS__W                                        4
#define   ATV_TOP_COMM_MB_MUX_OBS__M                                        0x3C0
#define   ATV_TOP_COMM_MB_MUX_OBS__PRE                                      0x0
#define     ATV_TOP_COMM_MB_MUX_OBS_PEAK_S                                  0x0
#define     ATV_TOP_COMM_MB_MUX_OBS_VID_GAIN                                0x40
#define     ATV_TOP_COMM_MB_MUX_OBS_CORR_O                                  0x80
#define     ATV_TOP_COMM_MB_MUX_OBS_CR_ROT_O                                0xC0
#define     ATV_TOP_COMM_MB_MUX_OBS_CR_IIR_IQ                               0x100
#define     ATV_TOP_COMM_MB_MUX_OBS_VIDEO_O                                 0x140
#define     ATV_TOP_COMM_MB_MUX_OBS_SIF_O                                   0x180
#define     ATV_TOP_COMM_MB_MUX_OBS_SIF2025_O                               0x1C0
#define     ATV_TOP_COMM_MB_MUX_OBS_POST_S                                  0x200

#define ATV_TOP_COMM_INT_REQ__A                                             0xC10003
#define ATV_TOP_COMM_INT_REQ__W                                             16
#define ATV_TOP_COMM_INT_REQ__M                                             0xFFFF
#define ATV_TOP_COMM_INT_REQ__PRE                                           0x0
#define ATV_TOP_COMM_INT_STA__A                                             0xC10005
#define ATV_TOP_COMM_INT_STA__W                                             16
#define ATV_TOP_COMM_INT_STA__M                                             0xFFFF
#define ATV_TOP_COMM_INT_STA__PRE                                           0x0

#define   ATV_TOP_COMM_INT_STA_FAGC_STA__B                                  0
#define   ATV_TOP_COMM_INT_STA_FAGC_STA__W                                  1
#define   ATV_TOP_COMM_INT_STA_FAGC_STA__M                                  0x1
#define   ATV_TOP_COMM_INT_STA_FAGC_STA__PRE                                0x0

#define   ATV_TOP_COMM_INT_STA_OVM_STA__B                                   1
#define   ATV_TOP_COMM_INT_STA_OVM_STA__W                                   1
#define   ATV_TOP_COMM_INT_STA_OVM_STA__M                                   0x2
#define   ATV_TOP_COMM_INT_STA_OVM_STA__PRE                                 0x0

#define   ATV_TOP_COMM_INT_STA_AMPTH_STA__B                                 2
#define   ATV_TOP_COMM_INT_STA_AMPTH_STA__W                                 1
#define   ATV_TOP_COMM_INT_STA_AMPTH_STA__M                                 0x4
#define   ATV_TOP_COMM_INT_STA_AMPTH_STA__PRE                               0x0

#define ATV_TOP_COMM_INT_MSK__A                                             0xC10006
#define ATV_TOP_COMM_INT_MSK__W                                             16
#define ATV_TOP_COMM_INT_MSK__M                                             0xFFFF
#define ATV_TOP_COMM_INT_MSK__PRE                                           0x0

#define   ATV_TOP_COMM_INT_MSK_FAGC_MSK__B                                  0
#define   ATV_TOP_COMM_INT_MSK_FAGC_MSK__W                                  1
#define   ATV_TOP_COMM_INT_MSK_FAGC_MSK__M                                  0x1
#define   ATV_TOP_COMM_INT_MSK_FAGC_MSK__PRE                                0x0

#define   ATV_TOP_COMM_INT_MSK_OVM_MSK__B                                   1
#define   ATV_TOP_COMM_INT_MSK_OVM_MSK__W                                   1
#define   ATV_TOP_COMM_INT_MSK_OVM_MSK__M                                   0x2
#define   ATV_TOP_COMM_INT_MSK_OVM_MSK__PRE                                 0x0

#define   ATV_TOP_COMM_INT_MSK_AMPTH_MSK__B                                 2
#define   ATV_TOP_COMM_INT_MSK_AMPTH_MSK__W                                 1
#define   ATV_TOP_COMM_INT_MSK_AMPTH_MSK__M                                 0x4
#define   ATV_TOP_COMM_INT_MSK_AMPTH_MSK__PRE                               0x0

#define ATV_TOP_COMM_INT_STM__A                                             0xC10007
#define ATV_TOP_COMM_INT_STM__W                                             16
#define ATV_TOP_COMM_INT_STM__M                                             0xFFFF
#define ATV_TOP_COMM_INT_STM__PRE                                           0x0

#define   ATV_TOP_COMM_INT_STM_FAGC_STM__B                                  0
#define   ATV_TOP_COMM_INT_STM_FAGC_STM__W                                  1
#define   ATV_TOP_COMM_INT_STM_FAGC_STM__M                                  0x1
#define   ATV_TOP_COMM_INT_STM_FAGC_STM__PRE                                0x0

#define   ATV_TOP_COMM_INT_STM_OVM_STM__B                                   1
#define   ATV_TOP_COMM_INT_STM_OVM_STM__W                                   1
#define   ATV_TOP_COMM_INT_STM_OVM_STM__M                                   0x2
#define   ATV_TOP_COMM_INT_STM_OVM_STM__PRE                                 0x0

#define   ATV_TOP_COMM_INT_STM_AMPTH_STM__B                                 2
#define   ATV_TOP_COMM_INT_STM_AMPTH_STM__W                                 1
#define   ATV_TOP_COMM_INT_STM_AMPTH_STM__M                                 0x4
#define   ATV_TOP_COMM_INT_STM_AMPTH_STM__PRE                               0x0

#define ATV_TOP_COMM_KEY__A                                                 0xC1000F
#define ATV_TOP_COMM_KEY__W                                                 16
#define ATV_TOP_COMM_KEY__M                                                 0xFFFF
#define ATV_TOP_COMM_KEY__PRE                                               0x0

#define   ATV_TOP_COMM_KEY_KEY__B                                           0
#define   ATV_TOP_COMM_KEY_KEY__W                                           16
#define   ATV_TOP_COMM_KEY_KEY__M                                           0xFFFF
#define   ATV_TOP_COMM_KEY_KEY__PRE                                         0x0
#define     ATV_TOP_COMM_KEY_KEY_KEY                                        0xFABA
#define     ATV_TOP_COMM_KEY_KEY_MIN                                        0x0
#define     ATV_TOP_COMM_KEY_KEY_MAX                                        0xFFFF

#define ATV_TOP_CR_AMP_TH__A                                                0xC10010
#define ATV_TOP_CR_AMP_TH__W                                                8
#define ATV_TOP_CR_AMP_TH__M                                                0xFF
#define ATV_TOP_CR_AMP_TH__PRE                                              0x8
#define   ATV_TOP_CR_AMP_TH_MN                                              0x8

#define ATV_TOP_CR_CONT__A                                                  0xC10011
#define ATV_TOP_CR_CONT__W                                                  9
#define ATV_TOP_CR_CONT__M                                                  0x1FF
#define ATV_TOP_CR_CONT__PRE                                                0x9C

#define   ATV_TOP_CR_CONT_CR_P__B                                           0
#define   ATV_TOP_CR_CONT_CR_P__W                                           3
#define   ATV_TOP_CR_CONT_CR_P__M                                           0x7
#define   ATV_TOP_CR_CONT_CR_P__PRE                                         0x4
#define     ATV_TOP_CR_CONT_CR_P_MN                                         0x4
#define     ATV_TOP_CR_CONT_CR_P_FM                                         0x0

#define   ATV_TOP_CR_CONT_CR_D__B                                           3
#define   ATV_TOP_CR_CONT_CR_D__W                                           3
#define   ATV_TOP_CR_CONT_CR_D__M                                           0x38
#define   ATV_TOP_CR_CONT_CR_D__PRE                                         0x18
#define     ATV_TOP_CR_CONT_CR_D_MN                                         0x18
#define     ATV_TOP_CR_CONT_CR_D_FM                                         0x0

#define   ATV_TOP_CR_CONT_CR_I__B                                           6
#define   ATV_TOP_CR_CONT_CR_I__W                                           3
#define   ATV_TOP_CR_CONT_CR_I__M                                           0x1C0
#define   ATV_TOP_CR_CONT_CR_I__PRE                                         0x80
#define     ATV_TOP_CR_CONT_CR_I_MN                                         0x80
#define     ATV_TOP_CR_CONT_CR_I_FM                                         0x0

#define ATV_TOP_CR_OVM_TH__A                                                0xC10012
#define ATV_TOP_CR_OVM_TH__W                                                8
#define ATV_TOP_CR_OVM_TH__M                                                0xFF
#define ATV_TOP_CR_OVM_TH__PRE                                              0xA0
#define   ATV_TOP_CR_OVM_TH_MN                                              0xA0
#define   ATV_TOP_CR_OVM_TH_FM                                              0x0

#define ATV_TOP_NOISE_TH__A                                                 0xC10013
#define ATV_TOP_NOISE_TH__W                                                 4
#define ATV_TOP_NOISE_TH__M                                                 0xF
#define ATV_TOP_NOISE_TH__PRE                                               0x8
#define   ATV_TOP_NOISE_TH_MN                                               0x8

#define ATV_TOP_EQU0__A                                                     0xC10014
#define ATV_TOP_EQU0__W                                                     9
#define ATV_TOP_EQU0__M                                                     0x1FF
#define ATV_TOP_EQU0__PRE                                                   0x1FB

#define   ATV_TOP_EQU0_EQU_C0__B                                            0
#define   ATV_TOP_EQU0_EQU_C0__W                                            9
#define   ATV_TOP_EQU0_EQU_C0__M                                            0x1FF
#define   ATV_TOP_EQU0_EQU_C0__PRE                                          0x1FB
#define     ATV_TOP_EQU0_EQU_C0_MN                                          0xFB

#define ATV_TOP_EQU1__A                                                     0xC10015
#define ATV_TOP_EQU1__W                                                     9
#define ATV_TOP_EQU1__M                                                     0x1FF
#define ATV_TOP_EQU1__PRE                                                   0x1CE

#define   ATV_TOP_EQU1_EQU_C1__B                                            0
#define   ATV_TOP_EQU1_EQU_C1__W                                            9
#define   ATV_TOP_EQU1_EQU_C1__M                                            0x1FF
#define   ATV_TOP_EQU1_EQU_C1__PRE                                          0x1CE
#define     ATV_TOP_EQU1_EQU_C1_MN                                          0xCE

#define ATV_TOP_EQU2__A                                                     0xC10016
#define ATV_TOP_EQU2__W                                                     9
#define ATV_TOP_EQU2__M                                                     0x1FF
#define ATV_TOP_EQU2__PRE                                                   0xD2

#define   ATV_TOP_EQU2_EQU_C2__B                                            0
#define   ATV_TOP_EQU2_EQU_C2__W                                            9
#define   ATV_TOP_EQU2_EQU_C2__M                                            0x1FF
#define   ATV_TOP_EQU2_EQU_C2__PRE                                          0xD2
#define     ATV_TOP_EQU2_EQU_C2_MN                                          0xD2

#define ATV_TOP_EQU3__A                                                     0xC10017
#define ATV_TOP_EQU3__W                                                     9
#define ATV_TOP_EQU3__M                                                     0x1FF
#define ATV_TOP_EQU3__PRE                                                   0x160

#define   ATV_TOP_EQU3_EQU_C3__B                                            0
#define   ATV_TOP_EQU3_EQU_C3__W                                            9
#define   ATV_TOP_EQU3_EQU_C3__M                                            0x1FF
#define   ATV_TOP_EQU3_EQU_C3__PRE                                          0x160
#define     ATV_TOP_EQU3_EQU_C3_MN                                          0x60

#define ATV_TOP_ROT_MODE__A                                                 0xC10018
#define ATV_TOP_ROT_MODE__W                                                 1
#define ATV_TOP_ROT_MODE__M                                                 0x1
#define ATV_TOP_ROT_MODE__PRE                                               0x0
#define   ATV_TOP_ROT_MODE_AMPTH_DEPEND                                     0x0
#define   ATV_TOP_ROT_MODE_ALWAYS                                           0x1

#define ATV_TOP_MOD_CONTROL__A                                              0xC10019
#define ATV_TOP_MOD_CONTROL__W                                              12
#define ATV_TOP_MOD_CONTROL__M                                              0xFFF
#define ATV_TOP_MOD_CONTROL__PRE                                            0x5B1

#define   ATV_TOP_MOD_CONTROL_MOD_IR__B                                     0
#define   ATV_TOP_MOD_CONTROL_MOD_IR__W                                     3
#define   ATV_TOP_MOD_CONTROL_MOD_IR__M                                     0x7
#define   ATV_TOP_MOD_CONTROL_MOD_IR__PRE                                   0x1
#define     ATV_TOP_MOD_CONTROL_MOD_IR_MN                                   0x1
#define     ATV_TOP_MOD_CONTROL_MOD_IR_FM                                   0x0

#define   ATV_TOP_MOD_CONTROL_MOD_IF__B                                     3
#define   ATV_TOP_MOD_CONTROL_MOD_IF__W                                     4
#define   ATV_TOP_MOD_CONTROL_MOD_IF__M                                     0x78
#define   ATV_TOP_MOD_CONTROL_MOD_IF__PRE                                   0x30
#define     ATV_TOP_MOD_CONTROL_MOD_IF_MN                                   0x30
#define     ATV_TOP_MOD_CONTROL_MOD_IF_FM                                   0x0

#define   ATV_TOP_MOD_CONTROL_MOD_MODE__B                                   7
#define   ATV_TOP_MOD_CONTROL_MOD_MODE__W                                   1
#define   ATV_TOP_MOD_CONTROL_MOD_MODE__M                                   0x80
#define   ATV_TOP_MOD_CONTROL_MOD_MODE__PRE                                 0x80
#define     ATV_TOP_MOD_CONTROL_MOD_MODE_RISE                               0x0
#define     ATV_TOP_MOD_CONTROL_MOD_MODE_RISE_FALL                          0x80

#define   ATV_TOP_MOD_CONTROL_MOD_TH__B                                     8
#define   ATV_TOP_MOD_CONTROL_MOD_TH__W                                     4
#define   ATV_TOP_MOD_CONTROL_MOD_TH__M                                     0xF00
#define   ATV_TOP_MOD_CONTROL_MOD_TH__PRE                                   0x500
#define     ATV_TOP_MOD_CONTROL_MOD_TH_MN                                   0x500
#define     ATV_TOP_MOD_CONTROL_MOD_TH_FM                                   0x0

#define ATV_TOP_STD__A                                                      0xC1001A
#define ATV_TOP_STD__W                                                      2
#define ATV_TOP_STD__M                                                      0x3
#define ATV_TOP_STD__PRE                                                    0x0

#define   ATV_TOP_STD_MODE__B                                               0
#define   ATV_TOP_STD_MODE__W                                               1
#define   ATV_TOP_STD_MODE__M                                               0x1
#define   ATV_TOP_STD_MODE__PRE                                             0x0
#define     ATV_TOP_STD_MODE_MN                                             0x0
#define     ATV_TOP_STD_MODE_FM                                             0x1

#define   ATV_TOP_STD_VID_POL__B                                            1
#define   ATV_TOP_STD_VID_POL__W                                            1
#define   ATV_TOP_STD_VID_POL__M                                            0x2
#define   ATV_TOP_STD_VID_POL__PRE                                          0x0
#define     ATV_TOP_STD_VID_POL_NEG                                         0x0
#define     ATV_TOP_STD_VID_POL_POS                                         0x2

#define ATV_TOP_VID_AMP__A                                                  0xC1001B
#define ATV_TOP_VID_AMP__W                                                  12
#define ATV_TOP_VID_AMP__M                                                  0xFFF
#define ATV_TOP_VID_AMP__PRE                                                0x380
#define   ATV_TOP_VID_AMP_MN                                                0x380
#define   ATV_TOP_VID_AMP_FM                                                0x0

#define ATV_TOP_VID_PEAK__A                                                 0xC1001C
#define ATV_TOP_VID_PEAK__W                                                 5
#define ATV_TOP_VID_PEAK__M                                                 0x1F
#define ATV_TOP_VID_PEAK__PRE                                               0x1

#define ATV_TOP_FAGC_TH__A                                                  0xC1001D
#define ATV_TOP_FAGC_TH__W                                                  11
#define ATV_TOP_FAGC_TH__M                                                  0x7FF
#define ATV_TOP_FAGC_TH__PRE                                                0x2B2
#define   ATV_TOP_FAGC_TH_MN                                                0x2B2

#define ATV_TOP_SYNC_SLICE__A                                               0xC1001E
#define ATV_TOP_SYNC_SLICE__W                                               11
#define ATV_TOP_SYNC_SLICE__M                                               0x7FF
#define ATV_TOP_SYNC_SLICE__PRE                                             0x243
#define   ATV_TOP_SYNC_SLICE_MN                                             0x243

#define ATV_TOP_SIF_GAIN__A                                                 0xC1001F
#define ATV_TOP_SIF_GAIN__W                                                 11
#define ATV_TOP_SIF_GAIN__M                                                 0x7FF
#define ATV_TOP_SIF_GAIN__PRE                                               0x0

#define ATV_TOP_SIF_TP__A                                                   0xC10020
#define ATV_TOP_SIF_TP__W                                                   6
#define ATV_TOP_SIF_TP__M                                                   0x3F
#define ATV_TOP_SIF_TP__PRE                                                 0x0

#define ATV_TOP_MOD_ACCU__A                                                 0xC10021
#define ATV_TOP_MOD_ACCU__W                                                 10
#define ATV_TOP_MOD_ACCU__M                                                 0x3FF
#define ATV_TOP_MOD_ACCU__PRE                                               0x0

#define ATV_TOP_CR_FREQ__A                                                  0xC10022
#define ATV_TOP_CR_FREQ__W                                                  8
#define ATV_TOP_CR_FREQ__M                                                  0xFF
#define ATV_TOP_CR_FREQ__PRE                                                0x0

#define ATV_TOP_CR_PHAD__A                                                  0xC10023
#define ATV_TOP_CR_PHAD__W                                                  12
#define ATV_TOP_CR_PHAD__M                                                  0xFFF
#define ATV_TOP_CR_PHAD__PRE                                                0x0

#define ATV_TOP_AF_SIF_ATT__A                                               0xC10024
#define ATV_TOP_AF_SIF_ATT__W                                               2
#define ATV_TOP_AF_SIF_ATT__M                                               0x3
#define ATV_TOP_AF_SIF_ATT__PRE                                             0x0
#define   ATV_TOP_AF_SIF_ATT_0DB                                            0x0
#define   ATV_TOP_AF_SIF_ATT_M3DB                                           0x1
#define   ATV_TOP_AF_SIF_ATT_M6DB                                           0x2
#define   ATV_TOP_AF_SIF_ATT_M9DB                                           0x3

#define ATV_TOP_STDBY__A                                                    0xC10025
#define ATV_TOP_STDBY__W                                                    2
#define ATV_TOP_STDBY__M                                                    0x3
#define ATV_TOP_STDBY__PRE                                                  0x1

#define   ATV_TOP_STDBY_SIF_STDBY__B                                        0
#define   ATV_TOP_STDBY_SIF_STDBY__W                                        1
#define   ATV_TOP_STDBY_SIF_STDBY__M                                        0x1
#define   ATV_TOP_STDBY_SIF_STDBY__PRE                                      0x1
#define     ATV_TOP_STDBY_SIF_STDBY_ACTIVE                                  0x0
#define     ATV_TOP_STDBY_SIF_STDBY_STANDBY                                 0x1

#define   ATV_TOP_STDBY_CVBS_STDBY__B                                       1
#define   ATV_TOP_STDBY_CVBS_STDBY__W                                       1
#define   ATV_TOP_STDBY_CVBS_STDBY__M                                       0x2
#define   ATV_TOP_STDBY_CVBS_STDBY__PRE                                     0x0
#define     ATV_TOP_STDBY_CVBS_STDBY_A1_ACTIVE                              0x0
#define     ATV_TOP_STDBY_CVBS_STDBY_A1_STANDBY                             0x2
#define     ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE                              0x2
#define     ATV_TOP_STDBY_CVBS_STDBY_A2_STANDBY                             0x0

#define ATV_TOP_OVERRIDE_SFR__A                                             0xC10026
#define ATV_TOP_OVERRIDE_SFR__W                                             1
#define ATV_TOP_OVERRIDE_SFR__M                                             0x1
#define ATV_TOP_OVERRIDE_SFR__PRE                                           0x0
#define   ATV_TOP_OVERRIDE_SFR_ACTIVE                                       0x0
#define   ATV_TOP_OVERRIDE_SFR_OVERRIDE                                     0x1

#define ATV_TOP_SFR_VID_GAIN__A                                             0xC10027
#define ATV_TOP_SFR_VID_GAIN__W                                             16
#define ATV_TOP_SFR_VID_GAIN__M                                             0xFFFF
#define ATV_TOP_SFR_VID_GAIN__PRE                                           0x0

#define ATV_TOP_SFR_AGC_RES__A                                              0xC10028
#define ATV_TOP_SFR_AGC_RES__W                                              5
#define ATV_TOP_SFR_AGC_RES__M                                              0x1F
#define ATV_TOP_SFR_AGC_RES__PRE                                            0x0

#define ATV_TOP_OVM_COMP__A                                                 0xC10029
#define ATV_TOP_OVM_COMP__W                                                 12
#define ATV_TOP_OVM_COMP__M                                                 0xFFF
#define ATV_TOP_OVM_COMP__PRE                                               0x0
#define ATV_TOP_OUT_CONF__A                                                 0xC1002A
#define ATV_TOP_OUT_CONF__W                                                 5
#define ATV_TOP_OUT_CONF__M                                                 0x1F
#define ATV_TOP_OUT_CONF__PRE                                               0x0

#define   ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__B                                 0
#define   ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__W                                 1
#define   ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__M                                 0x1
#define   ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__PRE                               0x0
#define     ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_UNSIGNED                         0x0
#define     ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_SIGNED                           0x1

#define   ATV_TOP_OUT_CONF_SIF_DAC_SIGN__B                                  1
#define   ATV_TOP_OUT_CONF_SIF_DAC_SIGN__W                                  1
#define   ATV_TOP_OUT_CONF_SIF_DAC_SIGN__M                                  0x2
#define   ATV_TOP_OUT_CONF_SIF_DAC_SIGN__PRE                                0x0
#define     ATV_TOP_OUT_CONF_SIF_DAC_SIGN_UNSIGNED                          0x0
#define     ATV_TOP_OUT_CONF_SIF_DAC_SIGN_SIGNED                            0x2

#define   ATV_TOP_OUT_CONF_SIF20_SIGN__B                                    2
#define   ATV_TOP_OUT_CONF_SIF20_SIGN__W                                    1
#define   ATV_TOP_OUT_CONF_SIF20_SIGN__M                                    0x4
#define   ATV_TOP_OUT_CONF_SIF20_SIGN__PRE                                  0x0
#define     ATV_TOP_OUT_CONF_SIF20_SIGN_UNSIGNED                            0x0
#define     ATV_TOP_OUT_CONF_SIF20_SIGN_SIGNED                              0x4

#define   ATV_TOP_OUT_CONF_CVBS_DAC_BR__B                                   3
#define   ATV_TOP_OUT_CONF_CVBS_DAC_BR__W                                   1
#define   ATV_TOP_OUT_CONF_CVBS_DAC_BR__M                                   0x8
#define   ATV_TOP_OUT_CONF_CVBS_DAC_BR__PRE                                 0x0
#define     ATV_TOP_OUT_CONF_CVBS_DAC_BR_NORMAL                             0x0
#define     ATV_TOP_OUT_CONF_CVBS_DAC_BR_BITREVERSED                        0x8

#define   ATV_TOP_OUT_CONF_SIF_DAC_BR__B                                    4
#define   ATV_TOP_OUT_CONF_SIF_DAC_BR__W                                    1
#define   ATV_TOP_OUT_CONF_SIF_DAC_BR__M                                    0x10
#define   ATV_TOP_OUT_CONF_SIF_DAC_BR__PRE                                  0x0
#define     ATV_TOP_OUT_CONF_SIF_DAC_BR_NORMAL                              0x0
#define     ATV_TOP_OUT_CONF_SIF_DAC_BR_BITREVERSED                         0x10

#define ATV_AFT_COMM_EXEC__A                                                0xFF0000
#define ATV_AFT_COMM_EXEC__W                                                2
#define ATV_AFT_COMM_EXEC__M                                                0x3
#define ATV_AFT_COMM_EXEC__PRE                                              0x0
#define   ATV_AFT_COMM_EXEC_STOP                                            0x0
#define   ATV_AFT_COMM_EXEC_ACTIVE                                          0x1
#define   ATV_AFT_COMM_EXEC_HOLD                                            0x2

#define ATV_AFT_TST__A                                                      0xFF0010
#define ATV_AFT_TST__W                                                      4
#define ATV_AFT_TST__M                                                      0xF
#define ATV_AFT_TST__PRE                                                    0x0

#define AUD_COMM_EXEC__A                                                    0x1000000
#define AUD_COMM_EXEC__W                                                    2
#define AUD_COMM_EXEC__M                                                    0x3
#define AUD_COMM_EXEC__PRE                                                  0x0
#define   AUD_COMM_EXEC_STOP                                                0x0
#define   AUD_COMM_EXEC_ACTIVE                                              0x1

#define AUD_COMM_MB__A                                                      0x1000002
#define AUD_COMM_MB__W                                                      16
#define AUD_COMM_MB__M                                                      0xFFFF
#define AUD_COMM_MB__PRE                                                    0x0

#define AUD_TOP_COMM_EXEC__A                                                0x1010000
#define AUD_TOP_COMM_EXEC__W                                                2
#define AUD_TOP_COMM_EXEC__M                                                0x3
#define AUD_TOP_COMM_EXEC__PRE                                              0x0
#define   AUD_TOP_COMM_EXEC_STOP                                            0x0
#define   AUD_TOP_COMM_EXEC_ACTIVE                                          0x1

#define AUD_TOP_COMM_MB__A                                                  0x1010002
#define AUD_TOP_COMM_MB__W                                                  16
#define AUD_TOP_COMM_MB__M                                                  0xFFFF
#define AUD_TOP_COMM_MB__PRE                                                0x0

#define   AUD_TOP_COMM_MB_CTL__B                                            0
#define   AUD_TOP_COMM_MB_CTL__W                                            1
#define   AUD_TOP_COMM_MB_CTL__M                                            0x1
#define   AUD_TOP_COMM_MB_CTL__PRE                                          0x0
#define     AUD_TOP_COMM_MB_CTL_CTR_OFF                                     0x0
#define     AUD_TOP_COMM_MB_CTL_CTR_ON                                      0x1

#define   AUD_TOP_COMM_MB_OBS__B                                            1
#define   AUD_TOP_COMM_MB_OBS__W                                            1
#define   AUD_TOP_COMM_MB_OBS__M                                            0x2
#define   AUD_TOP_COMM_MB_OBS__PRE                                          0x0
#define     AUD_TOP_COMM_MB_OBS_OBS_OFF                                     0x0
#define     AUD_TOP_COMM_MB_OBS_OBS_ON                                      0x2

#define   AUD_TOP_COMM_MB_MUX_CTRL__B                                       2
#define   AUD_TOP_COMM_MB_MUX_CTRL__W                                       4
#define   AUD_TOP_COMM_MB_MUX_CTRL__M                                       0x3C
#define   AUD_TOP_COMM_MB_MUX_CTRL__PRE                                     0x0
#define     AUD_TOP_COMM_MB_MUX_CTRL_DEMOD_TBO                              0x0
#define     AUD_TOP_COMM_MB_MUX_CTRL_XDFP_IRQS                              0x4
#define     AUD_TOP_COMM_MB_MUX_CTRL_OBSERVEPC                              0x8
#define     AUD_TOP_COMM_MB_MUX_CTRL_SAOUT                                  0xC
#define     AUD_TOP_COMM_MB_MUX_CTRL_XDFP_SCHEQ                             0x10

#define   AUD_TOP_COMM_MB_MUX_OBS__B                                        6
#define   AUD_TOP_COMM_MB_MUX_OBS__W                                        4
#define   AUD_TOP_COMM_MB_MUX_OBS__M                                        0x3C0
#define   AUD_TOP_COMM_MB_MUX_OBS__PRE                                      0x0
#define     AUD_TOP_COMM_MB_MUX_OBS_DEMOD_TBO                               0x0
#define     AUD_TOP_COMM_MB_MUX_OBS_XDFP_IRQS                               0x40
#define     AUD_TOP_COMM_MB_MUX_OBS_OBSERVEPC                               0x80
#define     AUD_TOP_COMM_MB_MUX_OBS_SAOUT                                   0xC0
#define     AUD_TOP_COMM_MB_MUX_OBS_XDFP_SCHEQ                              0x100

#define AUD_TOP_TR_MDE__A                                                   0x1010010
#define AUD_TOP_TR_MDE__W                                                   5
#define AUD_TOP_TR_MDE__M                                                   0x1F
#define AUD_TOP_TR_MDE__PRE                                                 0x18

#define   AUD_TOP_TR_MDE_FIFO_SIZE__B                                       0
#define   AUD_TOP_TR_MDE_FIFO_SIZE__W                                       4
#define   AUD_TOP_TR_MDE_FIFO_SIZE__M                                       0xF
#define   AUD_TOP_TR_MDE_FIFO_SIZE__PRE                                     0x8

#define   AUD_TOP_TR_MDE_RD_LOCK__B                                         4
#define   AUD_TOP_TR_MDE_RD_LOCK__W                                         1
#define   AUD_TOP_TR_MDE_RD_LOCK__M                                         0x10
#define   AUD_TOP_TR_MDE_RD_LOCK__PRE                                       0x10
#define     AUD_TOP_TR_MDE_RD_LOCK_NORMAL                                   0x0
#define     AUD_TOP_TR_MDE_RD_LOCK_LOCK                                     0x10

#define AUD_TOP_TR_CTR__A                                                   0x1010011
#define AUD_TOP_TR_CTR__W                                                   4
#define AUD_TOP_TR_CTR__M                                                   0xF
#define AUD_TOP_TR_CTR__PRE                                                 0x0

#define   AUD_TOP_TR_CTR_FIFO_RD_RDY__B                                     0
#define   AUD_TOP_TR_CTR_FIFO_RD_RDY__W                                     1
#define   AUD_TOP_TR_CTR_FIFO_RD_RDY__M                                     0x1
#define   AUD_TOP_TR_CTR_FIFO_RD_RDY__PRE                                   0x0
#define     AUD_TOP_TR_CTR_FIFO_RD_RDY_NOT_READY                            0x0
#define     AUD_TOP_TR_CTR_FIFO_RD_RDY_READY                                0x1

#define   AUD_TOP_TR_CTR_FIFO_EMPTY__B                                      1
#define   AUD_TOP_TR_CTR_FIFO_EMPTY__W                                      1
#define   AUD_TOP_TR_CTR_FIFO_EMPTY__M                                      0x2
#define   AUD_TOP_TR_CTR_FIFO_EMPTY__PRE                                    0x0
#define     AUD_TOP_TR_CTR_FIFO_EMPTY_NOT_EMPTY                             0x0
#define     AUD_TOP_TR_CTR_FIFO_EMPTY_EMPTY                                 0x2

#define   AUD_TOP_TR_CTR_FIFO_LOCK__B                                       2
#define   AUD_TOP_TR_CTR_FIFO_LOCK__W                                       1
#define   AUD_TOP_TR_CTR_FIFO_LOCK__M                                       0x4
#define   AUD_TOP_TR_CTR_FIFO_LOCK__PRE                                     0x0
#define     AUD_TOP_TR_CTR_FIFO_LOCK_UNLOCKED                               0x0
#define     AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED                                 0x4

#define   AUD_TOP_TR_CTR_FIFO_FULL__B                                       3
#define   AUD_TOP_TR_CTR_FIFO_FULL__W                                       1
#define   AUD_TOP_TR_CTR_FIFO_FULL__M                                       0x8
#define   AUD_TOP_TR_CTR_FIFO_FULL__PRE                                     0x0
#define     AUD_TOP_TR_CTR_FIFO_FULL_EMPTY                                  0x0
#define     AUD_TOP_TR_CTR_FIFO_FULL_FULL                                   0x8

#define AUD_TOP_TR_RD_REG__A                                                0x1010012
#define AUD_TOP_TR_RD_REG__W                                                16
#define AUD_TOP_TR_RD_REG__M                                                0xFFFF
#define AUD_TOP_TR_RD_REG__PRE                                              0x0

#define   AUD_TOP_TR_RD_REG_RESULT__B                                       0
#define   AUD_TOP_TR_RD_REG_RESULT__W                                       16
#define   AUD_TOP_TR_RD_REG_RESULT__M                                       0xFFFF
#define   AUD_TOP_TR_RD_REG_RESULT__PRE                                     0x0

#define AUD_TOP_TR_TIMER__A                                                 0x1010013
#define AUD_TOP_TR_TIMER__W                                                 16
#define AUD_TOP_TR_TIMER__M                                                 0xFFFF
#define AUD_TOP_TR_TIMER__PRE                                               0x0

#define   AUD_TOP_TR_TIMER_CYCLES__B                                        0
#define   AUD_TOP_TR_TIMER_CYCLES__W                                        16
#define   AUD_TOP_TR_TIMER_CYCLES__M                                        0xFFFF
#define   AUD_TOP_TR_TIMER_CYCLES__PRE                                      0x0

#define AUD_TOP_DEMOD_TBO_SEL__A                                            0x1010014
#define AUD_TOP_DEMOD_TBO_SEL__W                                            5
#define AUD_TOP_DEMOD_TBO_SEL__M                                            0x1F
#define AUD_TOP_DEMOD_TBO_SEL__PRE                                          0x0

#define AUD_DEM_WR_MODUS__A                                                 0x1030030
#define AUD_DEM_WR_MODUS__W                                                 16
#define AUD_DEM_WR_MODUS__M                                                 0xFFFF
#define AUD_DEM_WR_MODUS__PRE                                               0x0

#define   AUD_DEM_WR_MODUS_MOD_ASS__B                                       0
#define   AUD_DEM_WR_MODUS_MOD_ASS__W                                       1
#define   AUD_DEM_WR_MODUS_MOD_ASS__M                                       0x1
#define   AUD_DEM_WR_MODUS_MOD_ASS__PRE                                     0x0
#define     AUD_DEM_WR_MODUS_MOD_ASS_OFF                                    0x0
#define     AUD_DEM_WR_MODUS_MOD_ASS_ON                                     0x1

#define   AUD_DEM_WR_MODUS_MOD_STATINTERR__B                                1
#define   AUD_DEM_WR_MODUS_MOD_STATINTERR__W                                1
#define   AUD_DEM_WR_MODUS_MOD_STATINTERR__M                                0x2
#define   AUD_DEM_WR_MODUS_MOD_STATINTERR__PRE                              0x0
#define     AUD_DEM_WR_MODUS_MOD_STATINTERR_DISABLE                         0x0
#define     AUD_DEM_WR_MODUS_MOD_STATINTERR_ENABLE                          0x2

#define   AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__B                               2
#define   AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__W                               1
#define   AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M                               0x4
#define   AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__PRE                             0x0
#define     AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED                        0x0
#define     AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED                       0x4

#define   AUD_DEM_WR_MODUS_MOD_HDEV_A__B                                    8
#define   AUD_DEM_WR_MODUS_MOD_HDEV_A__W                                    1
#define   AUD_DEM_WR_MODUS_MOD_HDEV_A__M                                    0x100
#define   AUD_DEM_WR_MODUS_MOD_HDEV_A__PRE                                  0x0
#define     AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL                              0x0
#define     AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION                      0x100

#define   AUD_DEM_WR_MODUS_MOD_CM_A__B                                      9
#define   AUD_DEM_WR_MODUS_MOD_CM_A__W                                      1
#define   AUD_DEM_WR_MODUS_MOD_CM_A__M                                      0x200
#define   AUD_DEM_WR_MODUS_MOD_CM_A__PRE                                    0x0
#define     AUD_DEM_WR_MODUS_MOD_CM_A_MUTE                                  0x0
#define     AUD_DEM_WR_MODUS_MOD_CM_A_NOISE                                 0x200

#define   AUD_DEM_WR_MODUS_MOD_CM_B__B                                      10
#define   AUD_DEM_WR_MODUS_MOD_CM_B__W                                      1
#define   AUD_DEM_WR_MODUS_MOD_CM_B__M                                      0x400
#define   AUD_DEM_WR_MODUS_MOD_CM_B__PRE                                    0x0
#define     AUD_DEM_WR_MODUS_MOD_CM_B_MUTE                                  0x0
#define     AUD_DEM_WR_MODUS_MOD_CM_B_NOISE                                 0x400

#define   AUD_DEM_WR_MODUS_MOD_FMRADIO__B                                   11
#define   AUD_DEM_WR_MODUS_MOD_FMRADIO__W                                   1
#define   AUD_DEM_WR_MODUS_MOD_FMRADIO__M                                   0x800
#define   AUD_DEM_WR_MODUS_MOD_FMRADIO__PRE                                 0x0
#define     AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U                             0x0
#define     AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U                             0x800

#define   AUD_DEM_WR_MODUS_MOD_6_5MHZ__B                                    12
#define   AUD_DEM_WR_MODUS_MOD_6_5MHZ__W                                    1
#define   AUD_DEM_WR_MODUS_MOD_6_5MHZ__M                                    0x1000
#define   AUD_DEM_WR_MODUS_MOD_6_5MHZ__PRE                                  0x0
#define     AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM                               0x0
#define     AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K                                 0x1000

#define   AUD_DEM_WR_MODUS_MOD_4_5MHZ__B                                    13
#define   AUD_DEM_WR_MODUS_MOD_4_5MHZ__W                                    2
#define   AUD_DEM_WR_MODUS_MOD_4_5MHZ__M                                    0x6000
#define   AUD_DEM_WR_MODUS_MOD_4_5MHZ__PRE                                  0x0
#define     AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_KOREA                             0x0
#define     AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC                              0x2000
#define     AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_EIAJ                              0x4000
#define     AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA                              0x6000

#define   AUD_DEM_WR_MODUS_MOD_BTSC__B                                      15
#define   AUD_DEM_WR_MODUS_MOD_BTSC__W                                      1
#define   AUD_DEM_WR_MODUS_MOD_BTSC__M                                      0x8000
#define   AUD_DEM_WR_MODUS_MOD_BTSC__PRE                                    0x0
#define     AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO                           0x0
#define     AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP                              0x8000

#define AUD_DEM_WR_STANDARD_SEL__A                                          0x1030020
#define AUD_DEM_WR_STANDARD_SEL__W                                          16
#define AUD_DEM_WR_STANDARD_SEL__M                                          0xFFFF
#define AUD_DEM_WR_STANDARD_SEL__PRE                                        0x0

#define   AUD_DEM_WR_STANDARD_SEL_STD_SEL__B                                0
#define   AUD_DEM_WR_STANDARD_SEL_STD_SEL__W                                12
#define   AUD_DEM_WR_STANDARD_SEL_STD_SEL__M                                0xFFF
#define   AUD_DEM_WR_STANDARD_SEL_STD_SEL__PRE                              0x0
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO                            0x1
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA                         0x2
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM                           0x3
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1                            0x4
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2                            0x5
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3                            0x7
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM                     0x8
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM                      0x9
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM                      0xA
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM                    0xB
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO                     0x20
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP                        0x21
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J                           0x30
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO                        0x40

#define AUD_DEM_RD_STANDARD_RES__A                                          0x102007E
#define AUD_DEM_RD_STANDARD_RES__W                                          16
#define AUD_DEM_RD_STANDARD_RES__M                                          0xFFFF
#define AUD_DEM_RD_STANDARD_RES__PRE                                        0x0

#define   AUD_DEM_RD_STANDARD_RES_STD_RESULT__B                             0
#define   AUD_DEM_RD_STANDARD_RES_STD_RESULT__W                             16
#define   AUD_DEM_RD_STANDARD_RES_STD_RESULT__M                             0xFFFF
#define   AUD_DEM_RD_STANDARD_RES_STD_RESULT__PRE                           0x0
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD            0x0
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM       0x2
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM          0x3
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM         0x4
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM         0x5
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM         0x7
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM                 0x8
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM                   0x9
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM                   0xA
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM                 0xB
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO                  0x20
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP                0x21
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J                   0x30
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO                     0x40
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE       0x7FF

#define AUD_DEM_RD_STATUS__A                                                0x1020200
#define AUD_DEM_RD_STATUS__W                                                16
#define AUD_DEM_RD_STATUS__M                                                0xFFFF
#define AUD_DEM_RD_STATUS__PRE                                              0x0

#define   AUD_DEM_RD_STATUS_STAT_NEW_RDS__B                                 0
#define   AUD_DEM_RD_STATUS_STAT_NEW_RDS__W                                 1
#define   AUD_DEM_RD_STATUS_STAT_NEW_RDS__M                                 0x1
#define   AUD_DEM_RD_STATUS_STAT_NEW_RDS__PRE                               0x0
#define     AUD_DEM_RD_STATUS_STAT_NEW_RDS_NO_RDS_DATA                      0x0
#define     AUD_DEM_RD_STATUS_STAT_NEW_RDS_NEW_RDS_DATA                     0x1

#define   AUD_DEM_RD_STATUS_STAT_CARR_A__B                                  1
#define   AUD_DEM_RD_STATUS_STAT_CARR_A__W                                  1
#define   AUD_DEM_RD_STATUS_STAT_CARR_A__M                                  0x2
#define   AUD_DEM_RD_STATUS_STAT_CARR_A__PRE                                0x0
#define     AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED                          0x0
#define     AUD_DEM_RD_STATUS_STAT_CARR_A_NOT_DETECTED                      0x2

#define   AUD_DEM_RD_STATUS_STAT_CARR_B__B                                  2
#define   AUD_DEM_RD_STATUS_STAT_CARR_B__W                                  1
#define   AUD_DEM_RD_STATUS_STAT_CARR_B__M                                  0x4
#define   AUD_DEM_RD_STATUS_STAT_CARR_B__PRE                                0x0
#define     AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED                          0x0
#define     AUD_DEM_RD_STATUS_STAT_CARR_B_NOT_DETECTED                      0x4

#define   AUD_DEM_RD_STATUS_STAT_NICAM__B                                   5
#define   AUD_DEM_RD_STATUS_STAT_NICAM__W                                   1
#define   AUD_DEM_RD_STATUS_STAT_NICAM__M                                   0x20
#define   AUD_DEM_RD_STATUS_STAT_NICAM__PRE                                 0x0
#define     AUD_DEM_RD_STATUS_STAT_NICAM_NO_NICAM                           0x0
#define     AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED                     0x20

#define   AUD_DEM_RD_STATUS_STAT_STEREO__B                                  6
#define   AUD_DEM_RD_STATUS_STAT_STEREO__W                                  1
#define   AUD_DEM_RD_STATUS_STAT_STEREO__M                                  0x40
#define   AUD_DEM_RD_STATUS_STAT_STEREO__PRE                                0x0
#define     AUD_DEM_RD_STATUS_STAT_STEREO_NO_STEREO                         0x0
#define     AUD_DEM_RD_STATUS_STAT_STEREO_STEREO                            0x40

#define   AUD_DEM_RD_STATUS_STAT_INDEP_MONO__B                              7
#define   AUD_DEM_RD_STATUS_STAT_INDEP_MONO__W                              1
#define   AUD_DEM_RD_STATUS_STAT_INDEP_MONO__M                              0x80
#define   AUD_DEM_RD_STATUS_STAT_INDEP_MONO__PRE                            0x0
#define     AUD_DEM_RD_STATUS_STAT_INDEP_MONO_DEPENDENT_FM_MONO_PROGRAM     0x0
#define     AUD_DEM_RD_STATUS_STAT_INDEP_MONO_INDEPENDENT_FM_MONO_PROGRAM   0x80

#define   AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__B                              8
#define   AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__W                              1
#define   AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M                              0x100
#define   AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__PRE                            0x0
#define     AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_NO_SAP                        0x0
#define     AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP                           0x100

#define   AUD_DEM_RD_STATUS_BAD_NICAM__B                                    9
#define   AUD_DEM_RD_STATUS_BAD_NICAM__W                                    1
#define   AUD_DEM_RD_STATUS_BAD_NICAM__M                                    0x200
#define   AUD_DEM_RD_STATUS_BAD_NICAM__PRE                                  0x0
#define     AUD_DEM_RD_STATUS_BAD_NICAM_OK                                  0x0
#define     AUD_DEM_RD_STATUS_BAD_NICAM_BAD                                 0x200

#define AUD_DEM_RD_RDS_ARRAY_CNT__A                                         0x102020F
#define AUD_DEM_RD_RDS_ARRAY_CNT__W                                         12
#define AUD_DEM_RD_RDS_ARRAY_CNT__M                                         0xFFF
#define AUD_DEM_RD_RDS_ARRAY_CNT__PRE                                       0x0

#define   AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__B                          0
#define   AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__W                          12
#define   AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__M                          0xFFF
#define   AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__PRE                        0x0
#define     AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID        0xFFF

#define AUD_DEM_RD_RDS_DATA__A                                              0x1020210
#define AUD_DEM_RD_RDS_DATA__W                                              12
#define AUD_DEM_RD_RDS_DATA__M                                              0xFFF
#define AUD_DEM_RD_RDS_DATA__PRE                                            0x0

#define AUD_DSP_WR_FM_PRESC__A                                              0x105000E
#define AUD_DSP_WR_FM_PRESC__W                                              16
#define AUD_DSP_WR_FM_PRESC__M                                              0xFFFF
#define AUD_DSP_WR_FM_PRESC__PRE                                            0x0

#define   AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B                                8
#define   AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__W                                8
#define   AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__M                                0xFF00
#define   AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__PRE                              0x0
#define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION             0x7F00
#define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_50_KHZ_FM_DEVIATION             0x4800
#define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_75_KHZ_FM_DEVIATION             0x3000
#define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_100_KHZ_FM_DEVIATION            0x2400
#define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_150_KHZ_FM_DEVIATION            0x1800
#define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_180_KHZ_FM_DEVIATION            0x1300
#define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_380_KHZ_FM_DEVIATION            0x900

#define AUD_DSP_WR_NICAM_PRESC__A                                           0x1050010
#define AUD_DSP_WR_NICAM_PRESC__W                                           16
#define AUD_DSP_WR_NICAM_PRESC__M                                           0xFFFF
#define AUD_DSP_WR_NICAM_PRESC__PRE                                         0x0
#define AUD_DSP_WR_VOLUME__A                                                0x1050000
#define AUD_DSP_WR_VOLUME__W                                                16
#define AUD_DSP_WR_VOLUME__M                                                0xFFFF
#define AUD_DSP_WR_VOLUME__PRE                                              0x0

#define   AUD_DSP_WR_VOLUME_VOL_MAIN__B                                     8
#define   AUD_DSP_WR_VOLUME_VOL_MAIN__W                                     8
#define   AUD_DSP_WR_VOLUME_VOL_MAIN__M                                     0xFF00
#define   AUD_DSP_WR_VOLUME_VOL_MAIN__PRE                                   0x0

#define AUD_DSP_WR_SRC_I2S_MATR__A                                          0x1050038
#define AUD_DSP_WR_SRC_I2S_MATR__W                                          16
#define AUD_DSP_WR_SRC_I2S_MATR__M                                          0xFFFF
#define AUD_DSP_WR_SRC_I2S_MATR__PRE                                        0x0

#define   AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__B                                8
#define   AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__W                                8
#define   AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M                                0xFF00
#define   AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__PRE                              0x0
#define     AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO                            0x0
#define     AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB                       0x100
#define     AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A                        0x300
#define     AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B                        0x400

#define   AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__B                                0
#define   AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__W                                8
#define   AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M                                0xFF
#define   AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__PRE                              0x0
#define     AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A                         0x0
#define     AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B                         0x10
#define     AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO                          0x20
#define     AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO                            0x30

#define AUD_DSP_WR_AVC__A                                                   0x1050029
#define AUD_DSP_WR_AVC__W                                                   16
#define AUD_DSP_WR_AVC__M                                                   0xFFFF
#define AUD_DSP_WR_AVC__PRE                                                 0x0

#define   AUD_DSP_WR_AVC_AVC_ON__B                                          14
#define   AUD_DSP_WR_AVC_AVC_ON__W                                          2
#define   AUD_DSP_WR_AVC_AVC_ON__M                                          0xC000
#define   AUD_DSP_WR_AVC_AVC_ON__PRE                                        0x0
#define     AUD_DSP_WR_AVC_AVC_ON_OFF                                       0x0
#define     AUD_DSP_WR_AVC_AVC_ON_ON                                        0xC000

#define   AUD_DSP_WR_AVC_AVC_DECAY__B                                       8
#define   AUD_DSP_WR_AVC_AVC_DECAY__W                                       4
#define   AUD_DSP_WR_AVC_AVC_DECAY__M                                       0xF00
#define   AUD_DSP_WR_AVC_AVC_DECAY__PRE                                     0x0
#define     AUD_DSP_WR_AVC_AVC_DECAY_8_SEC                                  0x800
#define     AUD_DSP_WR_AVC_AVC_DECAY_4_SEC                                  0x400
#define     AUD_DSP_WR_AVC_AVC_DECAY_2_SEC                                  0x200
#define     AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC                                0x100

#define   AUD_DSP_WR_AVC_AVC_REF_LEV__B                                     4
#define   AUD_DSP_WR_AVC_AVC_REF_LEV__W                                     4
#define   AUD_DSP_WR_AVC_AVC_REF_LEV__M                                     0xF0
#define   AUD_DSP_WR_AVC_AVC_REF_LEV__PRE                                   0x0

#define   AUD_DSP_WR_AVC_AVC_MAX_ATT__B                                     2
#define   AUD_DSP_WR_AVC_AVC_MAX_ATT__W                                     2
#define   AUD_DSP_WR_AVC_AVC_MAX_ATT__M                                     0xC
#define   AUD_DSP_WR_AVC_AVC_MAX_ATT__PRE                                   0x0
#define     AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB                                 0x0
#define     AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB                                 0x4
#define     AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB                                 0x8

#define   AUD_DSP_WR_AVC_AVC_MAX_GAIN__B                                    0
#define   AUD_DSP_WR_AVC_AVC_MAX_GAIN__W                                    2
#define   AUD_DSP_WR_AVC_AVC_MAX_GAIN__M                                    0x3
#define   AUD_DSP_WR_AVC_AVC_MAX_GAIN__PRE                                  0x0
#define     AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB                                 0x0
#define     AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB                                0x1
#define     AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB                                 0x3

#define AUD_DSP_WR_QPEAK__A                                                 0x105000C
#define AUD_DSP_WR_QPEAK__W                                                 16
#define AUD_DSP_WR_QPEAK__M                                                 0xFFFF
#define AUD_DSP_WR_QPEAK__PRE                                               0x0

#define   AUD_DSP_WR_QPEAK_SRC_QP__B                                        8
#define   AUD_DSP_WR_QPEAK_SRC_QP__W                                        8
#define   AUD_DSP_WR_QPEAK_SRC_QP__M                                        0xFF00
#define   AUD_DSP_WR_QPEAK_SRC_QP__PRE                                      0x0
#define     AUD_DSP_WR_QPEAK_SRC_QP_MONO                                    0x0
#define     AUD_DSP_WR_QPEAK_SRC_QP_STEREO_AB                               0x100
#define     AUD_DSP_WR_QPEAK_SRC_QP_STEREO_A                                0x300
#define     AUD_DSP_WR_QPEAK_SRC_QP_STEREO_B                                0x400

#define   AUD_DSP_WR_QPEAK_MAT_QP__B                                        0
#define   AUD_DSP_WR_QPEAK_MAT_QP__W                                        8
#define   AUD_DSP_WR_QPEAK_MAT_QP__M                                        0xFF
#define   AUD_DSP_WR_QPEAK_MAT_QP__PRE                                      0x0
#define     AUD_DSP_WR_QPEAK_MAT_QP_SOUND_A                                 0x0
#define     AUD_DSP_WR_QPEAK_MAT_QP_SOUND_B                                 0x10
#define     AUD_DSP_WR_QPEAK_MAT_QP_STEREO                                  0x20
#define     AUD_DSP_WR_QPEAK_MAT_QP_MONO                                    0x30

#define AUD_DSP_RD_QPEAK_L__A                                               0x1040019
#define AUD_DSP_RD_QPEAK_L__W                                               16
#define AUD_DSP_RD_QPEAK_L__M                                               0xFFFF
#define AUD_DSP_RD_QPEAK_L__PRE                                             0x0

#define AUD_DSP_RD_QPEAK_R__A                                               0x104001A
#define AUD_DSP_RD_QPEAK_R__W                                               16
#define AUD_DSP_RD_QPEAK_R__M                                               0xFFFF
#define AUD_DSP_RD_QPEAK_R__PRE                                             0x0

#define AUD_DSP_WR_BEEPER__A                                                0x1050014
#define AUD_DSP_WR_BEEPER__W                                                16
#define AUD_DSP_WR_BEEPER__M                                                0xFFFF
#define AUD_DSP_WR_BEEPER__PRE                                              0x0

#define   AUD_DSP_WR_BEEPER_BEEP_VOLUME__B                                  8
#define   AUD_DSP_WR_BEEPER_BEEP_VOLUME__W                                  7
#define   AUD_DSP_WR_BEEPER_BEEP_VOLUME__M                                  0x7F00
#define   AUD_DSP_WR_BEEPER_BEEP_VOLUME__PRE                                0x0

#define   AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__B                               0
#define   AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__W                               7
#define   AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M                               0x7F
#define   AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__PRE                             0x0

#define AUD_DEM_WR_I2S_CONFIG2__A                                           0x1030050
#define AUD_DEM_WR_I2S_CONFIG2__W                                           16
#define AUD_DEM_WR_I2S_CONFIG2__M                                           0xFFFF
#define AUD_DEM_WR_I2S_CONFIG2__PRE                                         0x0

#define   AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__B                              6
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__W                              1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__M                              0x40
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__PRE                            0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_NORMAL                        0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_INVERTED                      0x40

#define   AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__B                              4
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__W                              1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M                              0x10
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__PRE                            0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE                       0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE                        0x10

#define   AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__B                             3
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__W                             1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M                             0x8
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__PRE                           0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER                       0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE                        0x8

#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__B                              2
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__W                              1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M                              0x4
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__PRE                            0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW                      0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH                     0x4

#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__B                             1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__W                             1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M                             0x2
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__PRE                           0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY                     0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY                        0x2

#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__B                            0
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__W                            1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M                            0x1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__PRE                          0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32                      0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16                      0x1

#define AUD_DSP_WR_I2S_OUT_FS__A                                            0x105002A
#define AUD_DSP_WR_I2S_OUT_FS__W                                            16
#define AUD_DSP_WR_I2S_OUT_FS__M                                            0xFFFF
#define AUD_DSP_WR_I2S_OUT_FS__PRE                                          0x0

#define   AUD_DSP_WR_I2S_OUT_FS_FS_OUT__B                                   0
#define   AUD_DSP_WR_I2S_OUT_FS_FS_OUT__W                                   16
#define   AUD_DSP_WR_I2S_OUT_FS_FS_OUT__M                                   0xFFFF
#define   AUD_DSP_WR_I2S_OUT_FS_FS_OUT__PRE                                 0x0

#define AUD_DSP_WR_AV_SYNC__A                                               0x105002B
#define AUD_DSP_WR_AV_SYNC__W                                               16
#define AUD_DSP_WR_AV_SYNC__M                                               0xFFFF
#define AUD_DSP_WR_AV_SYNC__PRE                                             0x0

#define   AUD_DSP_WR_AV_SYNC_AV_ON__B                                       15
#define   AUD_DSP_WR_AV_SYNC_AV_ON__W                                       1
#define   AUD_DSP_WR_AV_SYNC_AV_ON__M                                       0x8000
#define   AUD_DSP_WR_AV_SYNC_AV_ON__PRE                                     0x0
#define     AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE                                0x0
#define     AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE                                 0x8000

#define   AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__B                                14
#define   AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__W                                1
#define   AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__M                                0x4000
#define   AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__PRE                              0x0
#define     AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_MONOCHROME                      0x0
#define     AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_NTSC                            0x4000

#define   AUD_DSP_WR_AV_SYNC_AV_STD_SEL__B                                  0
#define   AUD_DSP_WR_AV_SYNC_AV_STD_SEL__W                                  2
#define   AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M                                  0x3
#define   AUD_DSP_WR_AV_SYNC_AV_STD_SEL__PRE                                0x0
#define     AUD_DSP_WR_AV_SYNC_AV_STD_SEL_AUTO                              0x0
#define     AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM                         0x1
#define     AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC                              0x2
#define     AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME                        0x3

#define AUD_DSP_RD_STATUS2__A                                               0x104007B
#define AUD_DSP_RD_STATUS2__W                                               16
#define AUD_DSP_RD_STATUS2__M                                               0xFFFF
#define AUD_DSP_RD_STATUS2__PRE                                             0x0

#define   AUD_DSP_RD_STATUS2_AV_ACTIVE__B                                   15
#define   AUD_DSP_RD_STATUS2_AV_ACTIVE__W                                   1
#define   AUD_DSP_RD_STATUS2_AV_ACTIVE__M                                   0x8000
#define   AUD_DSP_RD_STATUS2_AV_ACTIVE__PRE                                 0x0
#define     AUD_DSP_RD_STATUS2_AV_ACTIVE_NO_SYNC                            0x0
#define     AUD_DSP_RD_STATUS2_AV_ACTIVE_SYNC_ACTIVE                        0x8000

#define AUD_DSP_RD_XDFP_FW__A                                               0x104001D
#define AUD_DSP_RD_XDFP_FW__W                                               16
#define AUD_DSP_RD_XDFP_FW__M                                               0xFFFF
#define AUD_DSP_RD_XDFP_FW__PRE                                             0x344

#define   AUD_DSP_RD_XDFP_FW_DSP_FW_REV__B                                  0
#define   AUD_DSP_RD_XDFP_FW_DSP_FW_REV__W                                  16
#define   AUD_DSP_RD_XDFP_FW_DSP_FW_REV__M                                  0xFFFF
#define   AUD_DSP_RD_XDFP_FW_DSP_FW_REV__PRE                                0x344

#define AUD_DSP_RD_XFP_FW__A                                                0x10404B8
#define AUD_DSP_RD_XFP_FW__W                                                16
#define AUD_DSP_RD_XFP_FW__M                                                0xFFFF
#define AUD_DSP_RD_XFP_FW__PRE                                              0x42

#define   AUD_DSP_RD_XFP_FW_FP_FW_REV__B                                    0
#define   AUD_DSP_RD_XFP_FW_FP_FW_REV__W                                    16
#define   AUD_DSP_RD_XFP_FW_FP_FW_REV__M                                    0xFFFF
#define   AUD_DSP_RD_XFP_FW_FP_FW_REV__PRE                                  0x42

#define AUD_DEM_WR_DCO_B_HI__A                                              0x103009B
#define AUD_DEM_WR_DCO_B_HI__W                                              16
#define AUD_DEM_WR_DCO_B_HI__M                                              0xFFFF
#define AUD_DEM_WR_DCO_B_HI__PRE                                            0x0

#define AUD_DEM_WR_DCO_B_LO__A                                              0x1030093
#define AUD_DEM_WR_DCO_B_LO__W                                              16
#define AUD_DEM_WR_DCO_B_LO__M                                              0xFFFF
#define AUD_DEM_WR_DCO_B_LO__PRE                                            0x0

#define AUD_DEM_WR_DCO_A_HI__A                                              0x10300AB
#define AUD_DEM_WR_DCO_A_HI__W                                              16
#define AUD_DEM_WR_DCO_A_HI__M                                              0xFFFF
#define AUD_DEM_WR_DCO_A_HI__PRE                                            0x0

#define AUD_DEM_WR_DCO_A_LO__A                                              0x10300A3
#define AUD_DEM_WR_DCO_A_LO__W                                              16
#define AUD_DEM_WR_DCO_A_LO__M                                              0xFFFF
#define AUD_DEM_WR_DCO_A_LO__PRE                                            0x0
#define AUD_DEM_WR_NICAM_THRSHLD__A                                         0x1030021
#define AUD_DEM_WR_NICAM_THRSHLD__W                                         16
#define AUD_DEM_WR_NICAM_THRSHLD__M                                         0xFFFF
#define AUD_DEM_WR_NICAM_THRSHLD__PRE                                       0x2BC

#define   AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__B                            0
#define   AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__W                            12
#define   AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__M                            0xFFF
#define   AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__PRE                          0x2BC

#define AUD_DEM_WR_A2_THRSHLD__A                                            0x1030022
#define AUD_DEM_WR_A2_THRSHLD__W                                            16
#define AUD_DEM_WR_A2_THRSHLD__M                                            0xFFFF
#define AUD_DEM_WR_A2_THRSHLD__PRE                                          0x190

#define   AUD_DEM_WR_A2_THRSHLD_A2_THLD__B                                  0
#define   AUD_DEM_WR_A2_THRSHLD_A2_THLD__W                                  12
#define   AUD_DEM_WR_A2_THRSHLD_A2_THLD__M                                  0xFFF
#define   AUD_DEM_WR_A2_THRSHLD_A2_THLD__PRE                                0x190

#define AUD_DEM_WR_BTSC_THRSHLD__A                                          0x1030023
#define AUD_DEM_WR_BTSC_THRSHLD__W                                          16
#define AUD_DEM_WR_BTSC_THRSHLD__M                                          0xFFFF
#define AUD_DEM_WR_BTSC_THRSHLD__PRE                                        0xC

#define   AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__B                              0
#define   AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__W                              12
#define   AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__M                              0xFFF
#define   AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__PRE                            0xC

#define AUD_DEM_WR_CM_A_THRSHLD__A                                          0x1030024
#define AUD_DEM_WR_CM_A_THRSHLD__W                                          16
#define AUD_DEM_WR_CM_A_THRSHLD__M                                          0xFFFF
#define AUD_DEM_WR_CM_A_THRSHLD__PRE                                        0x2A

#define   AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__B                              0
#define   AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__W                              12
#define   AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__M                              0xFFF
#define   AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__PRE                            0x2A

#define AUD_DEM_WR_CM_B_THRSHLD__A                                          0x1030025
#define AUD_DEM_WR_CM_B_THRSHLD__W                                          16
#define AUD_DEM_WR_CM_B_THRSHLD__M                                          0xFFFF
#define AUD_DEM_WR_CM_B_THRSHLD__PRE                                        0x2A

#define   AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__B                              0
#define   AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__W                              12
#define   AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__M                              0xFFF
#define   AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__PRE                            0x2A

#define AUD_DEM_RD_NIC_C_AD_BITS__A                                         0x1020023
#define AUD_DEM_RD_NIC_C_AD_BITS__W                                         16
#define AUD_DEM_RD_NIC_C_AD_BITS__M                                         0xFFFF
#define AUD_DEM_RD_NIC_C_AD_BITS__PRE                                       0x0

#define   AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__B                            0
#define   AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__W                            1
#define   AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__M                            0x1
#define   AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__PRE                          0x0
#define     AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_NOT_SYNCED                  0x0
#define     AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_SYNCED                      0x1

#define   AUD_DEM_RD_NIC_C_AD_BITS_C__B                                     1
#define   AUD_DEM_RD_NIC_C_AD_BITS_C__W                                     4
#define   AUD_DEM_RD_NIC_C_AD_BITS_C__M                                     0x1E
#define   AUD_DEM_RD_NIC_C_AD_BITS_C__PRE                                   0x0

#define   AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__B                            5
#define   AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__W                            3
#define   AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__M                            0xE0
#define   AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__PRE                          0x0

#define AUD_DEM_RD_NIC_ADD_BITS_HI__A                                       0x1020038
#define AUD_DEM_RD_NIC_ADD_BITS_HI__W                                       16
#define AUD_DEM_RD_NIC_ADD_BITS_HI__M                                       0xFFFF
#define AUD_DEM_RD_NIC_ADD_BITS_HI__PRE                                     0x0

#define   AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__B                          0
#define   AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__W                          8
#define   AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__M                          0xFF
#define   AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__PRE                        0x0

#define AUD_DEM_RD_NIC_CIB__A                                               0x1020038
#define AUD_DEM_RD_NIC_CIB__W                                               16
#define AUD_DEM_RD_NIC_CIB__M                                               0xFFFF
#define AUD_DEM_RD_NIC_CIB__PRE                                             0x0

#define   AUD_DEM_RD_NIC_CIB_CIB2__B                                        0
#define   AUD_DEM_RD_NIC_CIB_CIB2__W                                        1
#define   AUD_DEM_RD_NIC_CIB_CIB2__M                                        0x1
#define   AUD_DEM_RD_NIC_CIB_CIB2__PRE                                      0x0

#define   AUD_DEM_RD_NIC_CIB_CIB1__B                                        1
#define   AUD_DEM_RD_NIC_CIB_CIB1__W                                        1
#define   AUD_DEM_RD_NIC_CIB_CIB1__M                                        0x2
#define   AUD_DEM_RD_NIC_CIB_CIB1__PRE                                      0x0

#define AUD_DEM_RD_NIC_ERROR_RATE__A                                        0x1020057
#define AUD_DEM_RD_NIC_ERROR_RATE__W                                        16
#define AUD_DEM_RD_NIC_ERROR_RATE__M                                        0xFFFF
#define AUD_DEM_RD_NIC_ERROR_RATE__PRE                                      0x0

#define   AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__B                           0
#define   AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__W                           12
#define   AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__M                           0xFFF
#define   AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__PRE                         0x0

#define AUD_DEM_WR_FM_DEEMPH__A                                             0x103000F
#define AUD_DEM_WR_FM_DEEMPH__W                                             16
#define AUD_DEM_WR_FM_DEEMPH__M                                             0xFFFF
#define AUD_DEM_WR_FM_DEEMPH__PRE                                           0x0
#define   AUD_DEM_WR_FM_DEEMPH_50US                                         0x0
#define   AUD_DEM_WR_FM_DEEMPH_75US                                         0x1
#define   AUD_DEM_WR_FM_DEEMPH_OFF                                          0x3F

#define AUD_DEM_WR_FM_MATRIX__A                                             0x103006F
#define AUD_DEM_WR_FM_MATRIX__W                                             16
#define AUD_DEM_WR_FM_MATRIX__M                                             0xFFFF
#define AUD_DEM_WR_FM_MATRIX__PRE                                           0x0
#define   AUD_DEM_WR_FM_MATRIX_NO_MATRIX                                    0x0
#define   AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX                                0x1
#define   AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX                                0x2
#define   AUD_DEM_WR_FM_MATRIX_SOUND_A                                      0x3
#define   AUD_DEM_WR_FM_MATRIX_SOUND_B                                      0x4

#define AUD_DSP_RD_FM_IDENT_VALUE__A                                        0x1040018
#define AUD_DSP_RD_FM_IDENT_VALUE__W                                        16
#define AUD_DSP_RD_FM_IDENT_VALUE__M                                        0xFFFF
#define AUD_DSP_RD_FM_IDENT_VALUE__PRE                                      0x0

#define   AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B                             8
#define   AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__W                             8
#define   AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__M                             0xFF00
#define   AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__PRE                           0x0

#define AUD_DSP_RD_FM_DC_LEVEL_A__A                                         0x104001B
#define AUD_DSP_RD_FM_DC_LEVEL_A__W                                         16
#define AUD_DSP_RD_FM_DC_LEVEL_A__M                                         0xFFFF
#define AUD_DSP_RD_FM_DC_LEVEL_A__PRE                                       0x0

#define   AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__B                           0
#define   AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__W                           16
#define   AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__M                           0xFFFF
#define   AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__PRE                         0x0

#define AUD_DSP_RD_FM_DC_LEVEL_B__A                                         0x104001C
#define AUD_DSP_RD_FM_DC_LEVEL_B__W                                         16
#define AUD_DSP_RD_FM_DC_LEVEL_B__M                                         0xFFFF
#define AUD_DSP_RD_FM_DC_LEVEL_B__PRE                                       0x0

#define   AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__B                           0
#define   AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__W                           16
#define   AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__M                           0xFFFF
#define   AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__PRE                         0x0

#define AUD_DEM_WR_FM_DC_NOTCH_SW__A                                        0x1030017
#define AUD_DEM_WR_FM_DC_NOTCH_SW__W                                        16
#define AUD_DEM_WR_FM_DC_NOTCH_SW__M                                        0xFFFF
#define AUD_DEM_WR_FM_DC_NOTCH_SW__PRE                                      0x0

#define   AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__B                          0
#define   AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__W                          16
#define   AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__M                          0xFFFF
#define   AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__PRE                        0x0
#define     AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_ON                        0x0
#define     AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_OFF                       0x3F

#define AUD_DSP_WR_SYNC_OUT__A                                              0x1050026
#define AUD_DSP_WR_SYNC_OUT__W                                              16
#define AUD_DSP_WR_SYNC_OUT__M                                              0xFFFF
#define AUD_DSP_WR_SYNC_OUT__PRE                                            0x0
#define   AUD_DSP_WR_SYNC_OUT_OFF                                           0x0
#define   AUD_DSP_WR_SYNC_OUT_SYNCHRONOUS                                   0x1

#define AUD_XFP_DRAM_1K__A                                                  0x1060000
#define AUD_XFP_DRAM_1K__W                                                  16
#define AUD_XFP_DRAM_1K__M                                                  0xFFFF
#define AUD_XFP_DRAM_1K__PRE                                                0x0
#define   AUD_XFP_DRAM_1K_D__B                                              0
#define   AUD_XFP_DRAM_1K_D__W                                              16
#define   AUD_XFP_DRAM_1K_D__M                                              0xFFFF
#define   AUD_XFP_DRAM_1K_D__PRE                                            0x0

#define AUD_XFP_PRAM_4K__A                                                  0x1070000
#define AUD_XFP_PRAM_4K__W                                                  16
#define AUD_XFP_PRAM_4K__M                                                  0xFFFF
#define AUD_XFP_PRAM_4K__PRE                                                0x0
#define   AUD_XFP_PRAM_4K_D__B                                              0
#define   AUD_XFP_PRAM_4K_D__W                                              16
#define   AUD_XFP_PRAM_4K_D__M                                              0xFFFF
#define   AUD_XFP_PRAM_4K_D__PRE                                            0x0

#define AUD_XDFP_DRAM_1K__A                                                 0x1080000
#define AUD_XDFP_DRAM_1K__W                                                 16
#define AUD_XDFP_DRAM_1K__M                                                 0xFFFF
#define AUD_XDFP_DRAM_1K__PRE                                               0x0
#define   AUD_XDFP_DRAM_1K_D__B                                             0
#define   AUD_XDFP_DRAM_1K_D__W                                             16
#define   AUD_XDFP_DRAM_1K_D__M                                             0xFFFF
#define   AUD_XDFP_DRAM_1K_D__PRE                                           0x0

#define AUD_XDFP_PRAM_4K__A                                                 0x1090000
#define AUD_XDFP_PRAM_4K__W                                                 16
#define AUD_XDFP_PRAM_4K__M                                                 0xFFFF
#define AUD_XDFP_PRAM_4K__PRE                                               0x0
#define   AUD_XDFP_PRAM_4K_D__B                                             0
#define   AUD_XDFP_PRAM_4K_D__W                                             16
#define   AUD_XDFP_PRAM_4K_D__M                                             0xFFFF
#define   AUD_XDFP_PRAM_4K_D__PRE                                           0x0

#define FEC_COMM_EXEC__A                                                    0x2400000
#define FEC_COMM_EXEC__W                                                    2
#define FEC_COMM_EXEC__M                                                    0x3
#define FEC_COMM_EXEC__PRE                                                  0x0
#define   FEC_COMM_EXEC_STOP                                                0x0
#define   FEC_COMM_EXEC_ACTIVE                                              0x1
#define   FEC_COMM_EXEC_HOLD                                                0x2

#define FEC_COMM_MB__A                                                      0x2400002
#define FEC_COMM_MB__W                                                      16
#define FEC_COMM_MB__M                                                      0xFFFF
#define FEC_COMM_MB__PRE                                                    0x0
#define FEC_COMM_INT_REQ__A                                                 0x2400003
#define FEC_COMM_INT_REQ__W                                                 16
#define FEC_COMM_INT_REQ__M                                                 0xFFFF
#define FEC_COMM_INT_REQ__PRE                                               0x0
#define   FEC_COMM_INT_REQ_OC_REQ__B                                        0
#define   FEC_COMM_INT_REQ_OC_REQ__W                                        1
#define   FEC_COMM_INT_REQ_OC_REQ__M                                        0x1
#define   FEC_COMM_INT_REQ_OC_REQ__PRE                                      0x0
#define   FEC_COMM_INT_REQ_RS_REQ__B                                        1
#define   FEC_COMM_INT_REQ_RS_REQ__W                                        1
#define   FEC_COMM_INT_REQ_RS_REQ__M                                        0x2
#define   FEC_COMM_INT_REQ_RS_REQ__PRE                                      0x0
#define   FEC_COMM_INT_REQ_DI_REQ__B                                        2
#define   FEC_COMM_INT_REQ_DI_REQ__W                                        1
#define   FEC_COMM_INT_REQ_DI_REQ__M                                        0x4
#define   FEC_COMM_INT_REQ_DI_REQ__PRE                                      0x0

#define FEC_COMM_INT_STA__A                                                 0x2400005
#define FEC_COMM_INT_STA__W                                                 16
#define FEC_COMM_INT_STA__M                                                 0xFFFF
#define FEC_COMM_INT_STA__PRE                                               0x0
#define FEC_COMM_INT_MSK__A                                                 0x2400006
#define FEC_COMM_INT_MSK__W                                                 16
#define FEC_COMM_INT_MSK__M                                                 0xFFFF
#define FEC_COMM_INT_MSK__PRE                                               0x0
#define FEC_COMM_INT_STM__A                                                 0x2400007
#define FEC_COMM_INT_STM__W                                                 16
#define FEC_COMM_INT_STM__M                                                 0xFFFF
#define FEC_COMM_INT_STM__PRE                                               0x0

#define FEC_TOP_COMM_EXEC__A                                                0x2410000
#define FEC_TOP_COMM_EXEC__W                                                2
#define FEC_TOP_COMM_EXEC__M                                                0x3
#define FEC_TOP_COMM_EXEC__PRE                                              0x0
#define   FEC_TOP_COMM_EXEC_STOP                                            0x0
#define   FEC_TOP_COMM_EXEC_ACTIVE                                          0x1
#define   FEC_TOP_COMM_EXEC_HOLD                                            0x2

#define FEC_TOP_ANNEX__A                                                    0x2410010
#define FEC_TOP_ANNEX__W                                                    2
#define FEC_TOP_ANNEX__M                                                    0x3
#define FEC_TOP_ANNEX__PRE                                                  0x0
#define   FEC_TOP_ANNEX_A                                                   0x0
#define   FEC_TOP_ANNEX_B                                                   0x1
#define   FEC_TOP_ANNEX_C                                                   0x2
#define   FEC_TOP_ANNEX_D                                                   0x3

#define FEC_DI_COMM_EXEC__A                                                 0x2420000
#define FEC_DI_COMM_EXEC__W                                                 2
#define FEC_DI_COMM_EXEC__M                                                 0x3
#define FEC_DI_COMM_EXEC__PRE                                               0x0
#define   FEC_DI_COMM_EXEC_STOP                                             0x0
#define   FEC_DI_COMM_EXEC_ACTIVE                                           0x1
#define   FEC_DI_COMM_EXEC_HOLD                                             0x2

#define FEC_DI_COMM_MB__A                                                   0x2420002
#define FEC_DI_COMM_MB__W                                                   2
#define FEC_DI_COMM_MB__M                                                   0x3
#define FEC_DI_COMM_MB__PRE                                                 0x0
#define   FEC_DI_COMM_MB_CTL__B                                             0
#define   FEC_DI_COMM_MB_CTL__W                                             1
#define   FEC_DI_COMM_MB_CTL__M                                             0x1
#define   FEC_DI_COMM_MB_CTL__PRE                                           0x0
#define     FEC_DI_COMM_MB_CTL_OFF                                          0x0
#define     FEC_DI_COMM_MB_CTL_ON                                           0x1
#define   FEC_DI_COMM_MB_OBS__B                                             1
#define   FEC_DI_COMM_MB_OBS__W                                             1
#define   FEC_DI_COMM_MB_OBS__M                                             0x2
#define   FEC_DI_COMM_MB_OBS__PRE                                           0x0
#define     FEC_DI_COMM_MB_OBS_OFF                                          0x0
#define     FEC_DI_COMM_MB_OBS_ON                                           0x2

#define FEC_DI_COMM_INT_REQ__A                                              0x2420003
#define FEC_DI_COMM_INT_REQ__W                                              1
#define FEC_DI_COMM_INT_REQ__M                                              0x1
#define FEC_DI_COMM_INT_REQ__PRE                                            0x0
#define FEC_DI_COMM_INT_STA__A                                              0x2420005
#define FEC_DI_COMM_INT_STA__W                                              2
#define FEC_DI_COMM_INT_STA__M                                              0x3
#define FEC_DI_COMM_INT_STA__PRE                                            0x0

#define   FEC_DI_COMM_INT_STA_STAT_INT__B                                   0
#define   FEC_DI_COMM_INT_STA_STAT_INT__W                                   1
#define   FEC_DI_COMM_INT_STA_STAT_INT__M                                   0x1
#define   FEC_DI_COMM_INT_STA_STAT_INT__PRE                                 0x0

#define   FEC_DI_COMM_INT_STA_TIMEOUT_INT__B                                1
#define   FEC_DI_COMM_INT_STA_TIMEOUT_INT__W                                1
#define   FEC_DI_COMM_INT_STA_TIMEOUT_INT__M                                0x2
#define   FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE                              0x0

#define FEC_DI_COMM_INT_MSK__A                                              0x2420006
#define FEC_DI_COMM_INT_MSK__W                                              2
#define FEC_DI_COMM_INT_MSK__M                                              0x3
#define FEC_DI_COMM_INT_MSK__PRE                                            0x0
#define   FEC_DI_COMM_INT_MSK_STAT_INT__B                                   0
#define   FEC_DI_COMM_INT_MSK_STAT_INT__W                                   1
#define   FEC_DI_COMM_INT_MSK_STAT_INT__M                                   0x1
#define   FEC_DI_COMM_INT_MSK_STAT_INT__PRE                                 0x0
#define   FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B                                1
#define   FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W                                1
#define   FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M                                0x2
#define   FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE                              0x0

#define FEC_DI_COMM_INT_STM__A                                              0x2420007
#define FEC_DI_COMM_INT_STM__W                                              2
#define FEC_DI_COMM_INT_STM__M                                              0x3
#define FEC_DI_COMM_INT_STM__PRE                                            0x0
#define   FEC_DI_COMM_INT_STM_STAT_INT__B                                   0
#define   FEC_DI_COMM_INT_STM_STAT_INT__W                                   1
#define   FEC_DI_COMM_INT_STM_STAT_INT__M                                   0x1
#define   FEC_DI_COMM_INT_STM_STAT_INT__PRE                                 0x0
#define   FEC_DI_COMM_INT_STM_TIMEOUT_INT__B                                1
#define   FEC_DI_COMM_INT_STM_TIMEOUT_INT__W                                1
#define   FEC_DI_COMM_INT_STM_TIMEOUT_INT__M                                0x2
#define   FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE                              0x0

#define FEC_DI_STATUS__A                                                    0x2420010
#define FEC_DI_STATUS__W                                                    1
#define FEC_DI_STATUS__M                                                    0x1
#define FEC_DI_STATUS__PRE                                                  0x0
#define FEC_DI_MODE__A                                                      0x2420011
#define FEC_DI_MODE__W                                                      3
#define FEC_DI_MODE__M                                                      0x7
#define FEC_DI_MODE__PRE                                                    0x0

#define   FEC_DI_MODE_NO_SYNC__B                                            0
#define   FEC_DI_MODE_NO_SYNC__W                                            1
#define   FEC_DI_MODE_NO_SYNC__M                                            0x1
#define   FEC_DI_MODE_NO_SYNC__PRE                                          0x0

#define   FEC_DI_MODE_IGNORE_LOST_SYNC__B                                   1
#define   FEC_DI_MODE_IGNORE_LOST_SYNC__W                                   1
#define   FEC_DI_MODE_IGNORE_LOST_SYNC__M                                   0x2
#define   FEC_DI_MODE_IGNORE_LOST_SYNC__PRE                                 0x0

#define   FEC_DI_MODE_IGNORE_TIMEOUT__B                                     2
#define   FEC_DI_MODE_IGNORE_TIMEOUT__W                                     1
#define   FEC_DI_MODE_IGNORE_TIMEOUT__M                                     0x4
#define   FEC_DI_MODE_IGNORE_TIMEOUT__PRE                                   0x0

#define FEC_DI_CONTROL_WORD__A                                              0x2420012
#define FEC_DI_CONTROL_WORD__W                                              4
#define FEC_DI_CONTROL_WORD__M                                              0xF
#define FEC_DI_CONTROL_WORD__PRE                                            0x0

#define FEC_DI_RESTART__A                                                   0x2420013
#define FEC_DI_RESTART__W                                                   1
#define FEC_DI_RESTART__M                                                   0x1
#define FEC_DI_RESTART__PRE                                                 0x0

#define FEC_DI_TIMEOUT_LO__A                                                0x2420014
#define FEC_DI_TIMEOUT_LO__W                                                16
#define FEC_DI_TIMEOUT_LO__M                                                0xFFFF
#define FEC_DI_TIMEOUT_LO__PRE                                              0x0

#define FEC_DI_TIMEOUT_HI__A                                                0x2420015
#define FEC_DI_TIMEOUT_HI__W                                                8
#define FEC_DI_TIMEOUT_HI__M                                                0xFF
#define FEC_DI_TIMEOUT_HI__PRE                                              0xA

#define FEC_RS_COMM_EXEC__A                                                 0x2430000
#define FEC_RS_COMM_EXEC__W                                                 2
#define FEC_RS_COMM_EXEC__M                                                 0x3
#define FEC_RS_COMM_EXEC__PRE                                               0x0
#define   FEC_RS_COMM_EXEC_STOP                                             0x0
#define   FEC_RS_COMM_EXEC_ACTIVE                                           0x1
#define   FEC_RS_COMM_EXEC_HOLD                                             0x2

#define FEC_RS_COMM_MB__A                                                   0x2430002
#define FEC_RS_COMM_MB__W                                                   2
#define FEC_RS_COMM_MB__M                                                   0x3
#define FEC_RS_COMM_MB__PRE                                                 0x0
#define   FEC_RS_COMM_MB_CTL__B                                             0
#define   FEC_RS_COMM_MB_CTL__W                                             1
#define   FEC_RS_COMM_MB_CTL__M                                             0x1
#define   FEC_RS_COMM_MB_CTL__PRE                                           0x0
#define     FEC_RS_COMM_MB_CTL_OFF                                          0x0
#define     FEC_RS_COMM_MB_CTL_ON                                           0x1
#define   FEC_RS_COMM_MB_OBS__B                                             1
#define   FEC_RS_COMM_MB_OBS__W                                             1
#define   FEC_RS_COMM_MB_OBS__M                                             0x2
#define   FEC_RS_COMM_MB_OBS__PRE                                           0x0
#define     FEC_RS_COMM_MB_OBS_OFF                                          0x0
#define     FEC_RS_COMM_MB_OBS_ON                                           0x2

#define FEC_RS_COMM_INT_REQ__A                                              0x2430003
#define FEC_RS_COMM_INT_REQ__W                                              1
#define FEC_RS_COMM_INT_REQ__M                                              0x1
#define FEC_RS_COMM_INT_REQ__PRE                                            0x0
#define FEC_RS_COMM_INT_STA__A                                              0x2430005
#define FEC_RS_COMM_INT_STA__W                                              2
#define FEC_RS_COMM_INT_STA__M                                              0x3
#define FEC_RS_COMM_INT_STA__PRE                                            0x0

#define   FEC_RS_COMM_INT_STA_FAILURE_INT__B                                0
#define   FEC_RS_COMM_INT_STA_FAILURE_INT__W                                1
#define   FEC_RS_COMM_INT_STA_FAILURE_INT__M                                0x1
#define   FEC_RS_COMM_INT_STA_FAILURE_INT__PRE                              0x0

#define   FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B                            1
#define   FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W                            1
#define   FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M                            0x2
#define   FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE                          0x0

#define FEC_RS_COMM_INT_MSK__A                                              0x2430006
#define FEC_RS_COMM_INT_MSK__W                                              2
#define FEC_RS_COMM_INT_MSK__M                                              0x3
#define FEC_RS_COMM_INT_MSK__PRE                                            0x0
#define   FEC_RS_COMM_INT_MSK_FAILURE_MSK__B                                0
#define   FEC_RS_COMM_INT_MSK_FAILURE_MSK__W                                1
#define   FEC_RS_COMM_INT_MSK_FAILURE_MSK__M                                0x1
#define   FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE                              0x0
#define   FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B                            1
#define   FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W                            1
#define   FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M                            0x2
#define   FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE                          0x0

#define FEC_RS_COMM_INT_STM__A                                              0x2430007
#define FEC_RS_COMM_INT_STM__W                                              2
#define FEC_RS_COMM_INT_STM__M                                              0x3
#define FEC_RS_COMM_INT_STM__PRE                                            0x0
#define   FEC_RS_COMM_INT_STM_FAILURE_MSK__B                                0
#define   FEC_RS_COMM_INT_STM_FAILURE_MSK__W                                1
#define   FEC_RS_COMM_INT_STM_FAILURE_MSK__M                                0x1
#define   FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE                              0x0
#define   FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B                            1
#define   FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W                            1
#define   FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M                            0x2
#define   FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE                          0x0

#define FEC_RS_STATUS__A                                                    0x2430010
#define FEC_RS_STATUS__W                                                    1
#define FEC_RS_STATUS__M                                                    0x1
#define FEC_RS_STATUS__PRE                                                  0x0
#define FEC_RS_MODE__A                                                      0x2430011
#define FEC_RS_MODE__W                                                      1
#define FEC_RS_MODE__M                                                      0x1
#define FEC_RS_MODE__PRE                                                    0x0

#define   FEC_RS_MODE_BYPASS__B                                             0
#define   FEC_RS_MODE_BYPASS__W                                             1
#define   FEC_RS_MODE_BYPASS__M                                             0x1
#define   FEC_RS_MODE_BYPASS__PRE                                           0x0

#define FEC_RS_MEASUREMENT_PERIOD__A                                        0x2430012
#define FEC_RS_MEASUREMENT_PERIOD__W                                        16
#define FEC_RS_MEASUREMENT_PERIOD__M                                        0xFFFF
#define FEC_RS_MEASUREMENT_PERIOD__PRE                                      0x1171

#define   FEC_RS_MEASUREMENT_PERIOD_PERIOD__B                               0
#define   FEC_RS_MEASUREMENT_PERIOD_PERIOD__W                               16
#define   FEC_RS_MEASUREMENT_PERIOD_PERIOD__M                               0xFFFF
#define   FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE                             0x1171

#define FEC_RS_MEASUREMENT_PRESCALE__A                                      0x2430013
#define FEC_RS_MEASUREMENT_PRESCALE__W                                      16
#define FEC_RS_MEASUREMENT_PRESCALE__M                                      0xFFFF
#define FEC_RS_MEASUREMENT_PRESCALE__PRE                                    0x1

#define   FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B                           0
#define   FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W                           16
#define   FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M                           0xFFFF
#define   FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE                         0x1

#define FEC_RS_NR_BIT_ERRORS__A                                             0x2430014
#define FEC_RS_NR_BIT_ERRORS__W                                             16
#define FEC_RS_NR_BIT_ERRORS__M                                             0xFFFF
#define FEC_RS_NR_BIT_ERRORS__PRE                                           0xFFFF

#define   FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B                                0
#define   FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W                                12
#define   FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M                                0xFFF
#define   FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE                              0xFFF

#define   FEC_RS_NR_BIT_ERRORS_EXP__B                                       12
#define   FEC_RS_NR_BIT_ERRORS_EXP__W                                       4
#define   FEC_RS_NR_BIT_ERRORS_EXP__M                                       0xF000
#define   FEC_RS_NR_BIT_ERRORS_EXP__PRE                                     0xF000

#define FEC_RS_NR_SYMBOL_ERRORS__A                                          0x2430015
#define FEC_RS_NR_SYMBOL_ERRORS__W                                          16
#define FEC_RS_NR_SYMBOL_ERRORS__M                                          0xFFFF
#define FEC_RS_NR_SYMBOL_ERRORS__PRE                                        0xFFFF

#define   FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B                             0
#define   FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W                             12
#define   FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M                             0xFFF
#define   FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE                           0xFFF

#define   FEC_RS_NR_SYMBOL_ERRORS_EXP__B                                    12
#define   FEC_RS_NR_SYMBOL_ERRORS_EXP__W                                    4
#define   FEC_RS_NR_SYMBOL_ERRORS_EXP__M                                    0xF000
#define   FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE                                  0xF000

#define FEC_RS_NR_PACKET_ERRORS__A                                          0x2430016
#define FEC_RS_NR_PACKET_ERRORS__W                                          16
#define FEC_RS_NR_PACKET_ERRORS__M                                          0xFFFF
#define FEC_RS_NR_PACKET_ERRORS__PRE                                        0xFFFF

#define   FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B                             0
#define   FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W                             12
#define   FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M                             0xFFF
#define   FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE                           0xFFF

#define   FEC_RS_NR_PACKET_ERRORS_EXP__B                                    12
#define   FEC_RS_NR_PACKET_ERRORS_EXP__W                                    4
#define   FEC_RS_NR_PACKET_ERRORS_EXP__M                                    0xF000
#define   FEC_RS_NR_PACKET_ERRORS_EXP__PRE                                  0xF000

#define FEC_RS_NR_FAILURES__A                                               0x2430017
#define FEC_RS_NR_FAILURES__W                                               16
#define FEC_RS_NR_FAILURES__M                                               0xFFFF
#define FEC_RS_NR_FAILURES__PRE                                             0x0

#define   FEC_RS_NR_FAILURES_FIXED_MANT__B                                  0
#define   FEC_RS_NR_FAILURES_FIXED_MANT__W                                  12
#define   FEC_RS_NR_FAILURES_FIXED_MANT__M                                  0xFFF
#define   FEC_RS_NR_FAILURES_FIXED_MANT__PRE                                0x0

#define   FEC_RS_NR_FAILURES_EXP__B                                         12
#define   FEC_RS_NR_FAILURES_EXP__W                                         4
#define   FEC_RS_NR_FAILURES_EXP__M                                         0xF000
#define   FEC_RS_NR_FAILURES_EXP__PRE                                       0x0

#define FEC_OC_COMM_EXEC__A                                                 0x2440000
#define FEC_OC_COMM_EXEC__W                                                 2
#define FEC_OC_COMM_EXEC__M                                                 0x3
#define FEC_OC_COMM_EXEC__PRE                                               0x0
#define   FEC_OC_COMM_EXEC_STOP                                             0x0
#define   FEC_OC_COMM_EXEC_ACTIVE                                           0x1
#define   FEC_OC_COMM_EXEC_HOLD                                             0x2

#define FEC_OC_COMM_MB__A                                                   0x2440002
#define FEC_OC_COMM_MB__W                                                   2
#define FEC_OC_COMM_MB__M                                                   0x3
#define FEC_OC_COMM_MB__PRE                                                 0x0
#define   FEC_OC_COMM_MB_CTL__B                                             0
#define   FEC_OC_COMM_MB_CTL__W                                             1
#define   FEC_OC_COMM_MB_CTL__M                                             0x1
#define   FEC_OC_COMM_MB_CTL__PRE                                           0x0
#define     FEC_OC_COMM_MB_CTL_OFF                                          0x0
#define     FEC_OC_COMM_MB_CTL_ON                                           0x1
#define   FEC_OC_COMM_MB_OBS__B                                             1
#define   FEC_OC_COMM_MB_OBS__W                                             1
#define   FEC_OC_COMM_MB_OBS__M                                             0x2
#define   FEC_OC_COMM_MB_OBS__PRE                                           0x0
#define     FEC_OC_COMM_MB_OBS_OFF                                          0x0
#define     FEC_OC_COMM_MB_OBS_ON                                           0x2

#define FEC_OC_COMM_INT_REQ__A                                              0x2440003
#define FEC_OC_COMM_INT_REQ__W                                              1
#define FEC_OC_COMM_INT_REQ__M                                              0x1
#define FEC_OC_COMM_INT_REQ__PRE                                            0x0
#define FEC_OC_COMM_INT_STA__A                                              0x2440005
#define FEC_OC_COMM_INT_STA__W                                              8
#define FEC_OC_COMM_INT_STA__M                                              0xFF
#define FEC_OC_COMM_INT_STA__PRE                                            0x0

#define   FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B                               0
#define   FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W                               1
#define   FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M                               0x1
#define   FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE                             0x0

#define   FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B                               1
#define   FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W                               1
#define   FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M                               0x2
#define   FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE                             0x0

#define   FEC_OC_COMM_INT_STA_SNC_LOST_INT__B                               2
#define   FEC_OC_COMM_INT_STA_SNC_LOST_INT__W                               1
#define   FEC_OC_COMM_INT_STA_SNC_LOST_INT__M                               0x4
#define   FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE                             0x0

#define   FEC_OC_COMM_INT_STA_SNC_PAR_INT__B                                3
#define   FEC_OC_COMM_INT_STA_SNC_PAR_INT__W                                1
#define   FEC_OC_COMM_INT_STA_SNC_PAR_INT__M                                0x8
#define   FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE                              0x0

#define   FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B                              4
#define   FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W                              1
#define   FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M                              0x10
#define   FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE                            0x0

#define   FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B                             5
#define   FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W                             1
#define   FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M                             0x20
#define   FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE                           0x0

#define   FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B                                6
#define   FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W                                1
#define   FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M                                0x40
#define   FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE                              0x0

#define   FEC_OC_COMM_INT_STA_STAT_CHG_INT__B                               7
#define   FEC_OC_COMM_INT_STA_STAT_CHG_INT__W                               1
#define   FEC_OC_COMM_INT_STA_STAT_CHG_INT__M                               0x80
#define   FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE                             0x0

#define FEC_OC_COMM_INT_MSK__A                                              0x2440006
#define FEC_OC_COMM_INT_MSK__W                                              8
#define FEC_OC_COMM_INT_MSK__M                                              0xFF
#define FEC_OC_COMM_INT_MSK__PRE                                            0x0
#define   FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B                               0
#define   FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W                               1
#define   FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M                               0x1
#define   FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE                             0x0
#define   FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B                               1
#define   FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W                               1
#define   FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M                               0x2
#define   FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE                             0x0
#define   FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B                               2
#define   FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W                               1
#define   FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M                               0x4
#define   FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE                             0x0
#define   FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B                                3
#define   FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W                                1
#define   FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M                                0x8
#define   FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE                              0x0
#define   FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B                              4
#define   FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W                              1
#define   FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M                              0x10
#define   FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE                            0x0
#define   FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B                             5
#define   FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W                             1
#define   FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M                             0x20
#define   FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE                           0x0
#define   FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B                                6
#define   FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W                                1
#define   FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M                                0x40
#define   FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE                              0x0
#define   FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B                               7
#define   FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W                               1
#define   FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M                               0x80
#define   FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE                             0x0

#define FEC_OC_COMM_INT_STM__A                                              0x2440007
#define FEC_OC_COMM_INT_STM__W                                              8
#define FEC_OC_COMM_INT_STM__M                                              0xFF
#define FEC_OC_COMM_INT_STM__PRE                                            0x0
#define   FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B                               0
#define   FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W                               1
#define   FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M                               0x1
#define   FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE                             0x0
#define   FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B                               1
#define   FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W                               1
#define   FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M                               0x2
#define   FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE                             0x0
#define   FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B                               2
#define   FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W                               1
#define   FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M                               0x4
#define   FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE                             0x0
#define   FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B                                3
#define   FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W                                1
#define   FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M                                0x8
#define   FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE                              0x0
#define   FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B                              4
#define   FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W                              1
#define   FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M                              0x10
#define   FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE                            0x0
#define   FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B                             5
#define   FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W                             1
#define   FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M                             0x20
#define   FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE                           0x0
#define   FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B                                6
#define   FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W                                1
#define   FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M                                0x40
#define   FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE                              0x0
#define   FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B                               7
#define   FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W                               1
#define   FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M                               0x80
#define   FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE                             0x0

#define FEC_OC_STATUS__A                                                    0x2440010
#define FEC_OC_STATUS__W                                                    5
#define FEC_OC_STATUS__M                                                    0x1F
#define FEC_OC_STATUS__PRE                                                  0x0

#define   FEC_OC_STATUS_DPR_STATUS__B                                       0
#define   FEC_OC_STATUS_DPR_STATUS__W                                       1
#define   FEC_OC_STATUS_DPR_STATUS__M                                       0x1
#define   FEC_OC_STATUS_DPR_STATUS__PRE                                     0x0

#define   FEC_OC_STATUS_SNC_STATUS__B                                       1
#define   FEC_OC_STATUS_SNC_STATUS__W                                       2
#define   FEC_OC_STATUS_SNC_STATUS__M                                       0x6
#define   FEC_OC_STATUS_SNC_STATUS__PRE                                     0x0

#define   FEC_OC_STATUS_FIFO_FULL__B                                        3
#define   FEC_OC_STATUS_FIFO_FULL__W                                        1
#define   FEC_OC_STATUS_FIFO_FULL__M                                        0x8
#define   FEC_OC_STATUS_FIFO_FULL__PRE                                      0x0

#define   FEC_OC_STATUS_FIFO_EMPTY__B                                       4
#define   FEC_OC_STATUS_FIFO_EMPTY__W                                       1
#define   FEC_OC_STATUS_FIFO_EMPTY__M                                       0x10
#define   FEC_OC_STATUS_FIFO_EMPTY__PRE                                     0x0

#define FEC_OC_MODE__A                                                      0x2440011
#define FEC_OC_MODE__W                                                      4
#define FEC_OC_MODE__M                                                      0xF
#define FEC_OC_MODE__PRE                                                    0x0

#define   FEC_OC_MODE_PARITY__B                                             0
#define   FEC_OC_MODE_PARITY__W                                             1
#define   FEC_OC_MODE_PARITY__M                                             0x1
#define   FEC_OC_MODE_PARITY__PRE                                           0x0

#define   FEC_OC_MODE_TRANSPARENT__B                                        1
#define   FEC_OC_MODE_TRANSPARENT__W                                        1
#define   FEC_OC_MODE_TRANSPARENT__M                                        0x2
#define   FEC_OC_MODE_TRANSPARENT__PRE                                      0x0

#define   FEC_OC_MODE_CLEAR__B                                              2
#define   FEC_OC_MODE_CLEAR__W                                              1
#define   FEC_OC_MODE_CLEAR__M                                              0x4
#define   FEC_OC_MODE_CLEAR__PRE                                            0x0

#define   FEC_OC_MODE_RETAIN_FRAMING__B                                     3
#define   FEC_OC_MODE_RETAIN_FRAMING__W                                     1
#define   FEC_OC_MODE_RETAIN_FRAMING__M                                     0x8
#define   FEC_OC_MODE_RETAIN_FRAMING__PRE                                   0x0

#define FEC_OC_DPR_MODE__A                                                  0x2440012
#define FEC_OC_DPR_MODE__W                                                  2
#define FEC_OC_DPR_MODE__M                                                  0x3
#define FEC_OC_DPR_MODE__PRE                                                0x0

#define   FEC_OC_DPR_MODE_ERR_DISABLE__B                                    0
#define   FEC_OC_DPR_MODE_ERR_DISABLE__W                                    1
#define   FEC_OC_DPR_MODE_ERR_DISABLE__M                                    0x1
#define   FEC_OC_DPR_MODE_ERR_DISABLE__PRE                                  0x0

#define   FEC_OC_DPR_MODE_NOSYNC_ENABLE__B                                  1
#define   FEC_OC_DPR_MODE_NOSYNC_ENABLE__W                                  1
#define   FEC_OC_DPR_MODE_NOSYNC_ENABLE__M                                  0x2
#define   FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE                                0x0

#define FEC_OC_DPR_UNLOCK__A                                                0x2440013
#define FEC_OC_DPR_UNLOCK__W                                                1
#define FEC_OC_DPR_UNLOCK__M                                                0x1
#define FEC_OC_DPR_UNLOCK__PRE                                              0x0
#define FEC_OC_DTO_MODE__A                                                  0x2440014
#define FEC_OC_DTO_MODE__W                                                  3
#define FEC_OC_DTO_MODE__M                                                  0x7
#define FEC_OC_DTO_MODE__PRE                                                0x0

#define   FEC_OC_DTO_MODE_DYNAMIC__B                                        0
#define   FEC_OC_DTO_MODE_DYNAMIC__W                                        1
#define   FEC_OC_DTO_MODE_DYNAMIC__M                                        0x1
#define   FEC_OC_DTO_MODE_DYNAMIC__PRE                                      0x0

#define   FEC_OC_DTO_MODE_DUTY_CYCLE__B                                     1
#define   FEC_OC_DTO_MODE_DUTY_CYCLE__W                                     1
#define   FEC_OC_DTO_MODE_DUTY_CYCLE__M                                     0x2
#define   FEC_OC_DTO_MODE_DUTY_CYCLE__PRE                                   0x0

#define   FEC_OC_DTO_MODE_OFFSET_ENABLE__B                                  2
#define   FEC_OC_DTO_MODE_OFFSET_ENABLE__W                                  1
#define   FEC_OC_DTO_MODE_OFFSET_ENABLE__M                                  0x4
#define   FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE                                0x0

#define FEC_OC_DTO_PERIOD__A                                                0x2440015
#define FEC_OC_DTO_PERIOD__W                                                8
#define FEC_OC_DTO_PERIOD__M                                                0xFF
#define FEC_OC_DTO_PERIOD__PRE                                              0x0
#define FEC_OC_DTO_RATE_LO__A                                               0x2440016
#define FEC_OC_DTO_RATE_LO__W                                               16
#define FEC_OC_DTO_RATE_LO__M                                               0xFFFF
#define FEC_OC_DTO_RATE_LO__PRE                                             0x0

#define   FEC_OC_DTO_RATE_LO_RATE_LO__B                                     0
#define   FEC_OC_DTO_RATE_LO_RATE_LO__W                                     16
#define   FEC_OC_DTO_RATE_LO_RATE_LO__M                                     0xFFFF
#define   FEC_OC_DTO_RATE_LO_RATE_LO__PRE                                   0x0

#define FEC_OC_DTO_RATE_HI__A                                               0x2440017
#define FEC_OC_DTO_RATE_HI__W                                               10
#define FEC_OC_DTO_RATE_HI__M                                               0x3FF
#define FEC_OC_DTO_RATE_HI__PRE                                             0xC0

#define   FEC_OC_DTO_RATE_HI_RATE_HI__B                                     0
#define   FEC_OC_DTO_RATE_HI_RATE_HI__W                                     10
#define   FEC_OC_DTO_RATE_HI_RATE_HI__M                                     0x3FF
#define   FEC_OC_DTO_RATE_HI_RATE_HI__PRE                                   0xC0

#define FEC_OC_DTO_BURST_LEN__A                                             0x2440018
#define FEC_OC_DTO_BURST_LEN__W                                             8
#define FEC_OC_DTO_BURST_LEN__M                                             0xFF
#define FEC_OC_DTO_BURST_LEN__PRE                                           0xBC

#define   FEC_OC_DTO_BURST_LEN_BURST_LEN__B                                 0
#define   FEC_OC_DTO_BURST_LEN_BURST_LEN__W                                 8
#define   FEC_OC_DTO_BURST_LEN_BURST_LEN__M                                 0xFF
#define   FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE                               0xBC

#define FEC_OC_FCT_MODE__A                                                  0x244001A
#define FEC_OC_FCT_MODE__W                                                  2
#define FEC_OC_FCT_MODE__M                                                  0x3
#define FEC_OC_FCT_MODE__PRE                                                0x0

#define   FEC_OC_FCT_MODE_RAT_ENA__B                                        0
#define   FEC_OC_FCT_MODE_RAT_ENA__W                                        1
#define   FEC_OC_FCT_MODE_RAT_ENA__M                                        0x1
#define   FEC_OC_FCT_MODE_RAT_ENA__PRE                                      0x0

#define   FEC_OC_FCT_MODE_VIRT_ENA__B                                       1
#define   FEC_OC_FCT_MODE_VIRT_ENA__W                                       1
#define   FEC_OC_FCT_MODE_VIRT_ENA__M                                       0x2
#define   FEC_OC_FCT_MODE_VIRT_ENA__PRE                                     0x0

#define FEC_OC_FCT_USAGE__A                                                 0x244001B
#define FEC_OC_FCT_USAGE__W                                                 3
#define FEC_OC_FCT_USAGE__M                                                 0x7
#define FEC_OC_FCT_USAGE__PRE                                               0x2

#define   FEC_OC_FCT_USAGE_USAGE__B                                         0
#define   FEC_OC_FCT_USAGE_USAGE__W                                         3
#define   FEC_OC_FCT_USAGE_USAGE__M                                         0x7
#define   FEC_OC_FCT_USAGE_USAGE__PRE                                       0x2

#define FEC_OC_FCT_OCCUPATION__A                                            0x244001C
#define FEC_OC_FCT_OCCUPATION__W                                            12
#define FEC_OC_FCT_OCCUPATION__M                                            0xFFF
#define FEC_OC_FCT_OCCUPATION__PRE                                          0x0

#define   FEC_OC_FCT_OCCUPATION_OCCUPATION__B                               0
#define   FEC_OC_FCT_OCCUPATION_OCCUPATION__W                               12
#define   FEC_OC_FCT_OCCUPATION_OCCUPATION__M                               0xFFF
#define   FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE                             0x0

#define FEC_OC_TMD_MODE__A                                                  0x244001E
#define FEC_OC_TMD_MODE__W                                                  3
#define FEC_OC_TMD_MODE__M                                                  0x7
#define FEC_OC_TMD_MODE__PRE                                                0x4

#define   FEC_OC_TMD_MODE_MODE__B                                           0
#define   FEC_OC_TMD_MODE_MODE__W                                           3
#define   FEC_OC_TMD_MODE_MODE__M                                           0x7
#define   FEC_OC_TMD_MODE_MODE__PRE                                         0x4

#define FEC_OC_TMD_COUNT__A                                                 0x244001F
#define FEC_OC_TMD_COUNT__W                                                 10
#define FEC_OC_TMD_COUNT__M                                                 0x3FF
#define FEC_OC_TMD_COUNT__PRE                                               0x1F4

#define   FEC_OC_TMD_COUNT_COUNT__B                                         0
#define   FEC_OC_TMD_COUNT_COUNT__W                                         10
#define   FEC_OC_TMD_COUNT_COUNT__M                                         0x3FF
#define   FEC_OC_TMD_COUNT_COUNT__PRE                                       0x1F4

#define FEC_OC_TMD_HI_MARGIN__A                                             0x2440020
#define FEC_OC_TMD_HI_MARGIN__W                                             11
#define FEC_OC_TMD_HI_MARGIN__M                                             0x7FF
#define FEC_OC_TMD_HI_MARGIN__PRE                                           0x200

#define   FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B                                 0
#define   FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W                                 11
#define   FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M                                 0x7FF
#define   FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE                               0x200

#define FEC_OC_TMD_LO_MARGIN__A                                             0x2440021
#define FEC_OC_TMD_LO_MARGIN__W                                             11
#define FEC_OC_TMD_LO_MARGIN__M                                             0x7FF
#define FEC_OC_TMD_LO_MARGIN__PRE                                           0x100

#define   FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B                                 0
#define   FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W                                 11
#define   FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M                                 0x7FF
#define   FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE                               0x100

#define FEC_OC_TMD_CTL_UPD_RATE__A                                          0x2440022
#define FEC_OC_TMD_CTL_UPD_RATE__W                                          4
#define FEC_OC_TMD_CTL_UPD_RATE__M                                          0xF
#define FEC_OC_TMD_CTL_UPD_RATE__PRE                                        0x1

#define   FEC_OC_TMD_CTL_UPD_RATE_RATE__B                                   0
#define   FEC_OC_TMD_CTL_UPD_RATE_RATE__W                                   4
#define   FEC_OC_TMD_CTL_UPD_RATE_RATE__M                                   0xF
#define   FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE                                 0x1

#define FEC_OC_TMD_INT_UPD_RATE__A                                          0x2440023
#define FEC_OC_TMD_INT_UPD_RATE__W                                          4
#define FEC_OC_TMD_INT_UPD_RATE__M                                          0xF
#define FEC_OC_TMD_INT_UPD_RATE__PRE                                        0x4

#define   FEC_OC_TMD_INT_UPD_RATE_RATE__B                                   0
#define   FEC_OC_TMD_INT_UPD_RATE_RATE__W                                   4
#define   FEC_OC_TMD_INT_UPD_RATE_RATE__M                                   0xF
#define   FEC_OC_TMD_INT_UPD_RATE_RATE__PRE                                 0x4

#define FEC_OC_AVR_PARM_A__A                                                0x2440026
#define FEC_OC_AVR_PARM_A__W                                                4
#define FEC_OC_AVR_PARM_A__M                                                0xF
#define FEC_OC_AVR_PARM_A__PRE                                              0x6

#define   FEC_OC_AVR_PARM_A_PARM__B                                         0
#define   FEC_OC_AVR_PARM_A_PARM__W                                         4
#define   FEC_OC_AVR_PARM_A_PARM__M                                         0xF
#define   FEC_OC_AVR_PARM_A_PARM__PRE                                       0x6

#define FEC_OC_AVR_PARM_B__A                                                0x2440027
#define FEC_OC_AVR_PARM_B__W                                                4
#define FEC_OC_AVR_PARM_B__M                                                0xF
#define FEC_OC_AVR_PARM_B__PRE                                              0x4

#define   FEC_OC_AVR_PARM_B_PARM__B                                         0
#define   FEC_OC_AVR_PARM_B_PARM__W                                         4
#define   FEC_OC_AVR_PARM_B_PARM__M                                         0xF
#define   FEC_OC_AVR_PARM_B_PARM__PRE                                       0x4

#define FEC_OC_AVR_AVG_LO__A                                                0x2440028
#define FEC_OC_AVR_AVG_LO__W                                                16
#define FEC_OC_AVR_AVG_LO__M                                                0xFFFF
#define FEC_OC_AVR_AVG_LO__PRE                                              0x0

#define   FEC_OC_AVR_AVG_LO_AVG_LO__B                                       0
#define   FEC_OC_AVR_AVG_LO_AVG_LO__W                                       16
#define   FEC_OC_AVR_AVG_LO_AVG_LO__M                                       0xFFFF
#define   FEC_OC_AVR_AVG_LO_AVG_LO__PRE                                     0x0

#define FEC_OC_AVR_AVG_HI__A                                                0x2440029
#define FEC_OC_AVR_AVG_HI__W                                                6
#define FEC_OC_AVR_AVG_HI__M                                                0x3F
#define FEC_OC_AVR_AVG_HI__PRE                                              0x0

#define   FEC_OC_AVR_AVG_HI_AVG_HI__B                                       0
#define   FEC_OC_AVR_AVG_HI_AVG_HI__W                                       6
#define   FEC_OC_AVR_AVG_HI_AVG_HI__M                                       0x3F
#define   FEC_OC_AVR_AVG_HI_AVG_HI__PRE                                     0x0

#define FEC_OC_RCN_MODE__A                                                  0x244002C
#define FEC_OC_RCN_MODE__W                                                  5
#define FEC_OC_RCN_MODE__M                                                  0x1F
#define FEC_OC_RCN_MODE__PRE                                                0x1F

#define   FEC_OC_RCN_MODE_MODE__B                                           0
#define   FEC_OC_RCN_MODE_MODE__W                                           5
#define   FEC_OC_RCN_MODE_MODE__M                                           0x1F
#define   FEC_OC_RCN_MODE_MODE__PRE                                         0x1F

#define FEC_OC_RCN_OCC_SETTLE__A                                            0x244002D
#define FEC_OC_RCN_OCC_SETTLE__W                                            11
#define FEC_OC_RCN_OCC_SETTLE__M                                            0x7FF
#define FEC_OC_RCN_OCC_SETTLE__PRE                                          0x180

#define   FEC_OC_RCN_OCC_SETTLE_LEVEL__B                                    0
#define   FEC_OC_RCN_OCC_SETTLE_LEVEL__W                                    11
#define   FEC_OC_RCN_OCC_SETTLE_LEVEL__M                                    0x7FF
#define   FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE                                  0x180

#define FEC_OC_RCN_GAIN__A                                                  0x244002E
#define FEC_OC_RCN_GAIN__W                                                  4
#define FEC_OC_RCN_GAIN__M                                                  0xF
#define FEC_OC_RCN_GAIN__PRE                                                0xC

#define   FEC_OC_RCN_GAIN_GAIN__B                                           0
#define   FEC_OC_RCN_GAIN_GAIN__W                                           4
#define   FEC_OC_RCN_GAIN_GAIN__M                                           0xF
#define   FEC_OC_RCN_GAIN_GAIN__PRE                                         0xC

#define FEC_OC_RCN_CTL_RATE_LO__A                                           0x2440030
#define FEC_OC_RCN_CTL_RATE_LO__W                                           16
#define FEC_OC_RCN_CTL_RATE_LO__M                                           0xFFFF
#define FEC_OC_RCN_CTL_RATE_LO__PRE                                         0x0

#define   FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B                                  0
#define   FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W                                  16
#define   FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M                                  0xFFFF
#define   FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE                                0x0

#define FEC_OC_RCN_CTL_RATE_HI__A                                           0x2440031
#define FEC_OC_RCN_CTL_RATE_HI__W                                           8
#define FEC_OC_RCN_CTL_RATE_HI__M                                           0xFF
#define FEC_OC_RCN_CTL_RATE_HI__PRE                                         0xC0

#define   FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B                                  0
#define   FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W                                  8
#define   FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M                                  0xFF
#define   FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE                                0xC0

#define FEC_OC_RCN_CTL_STEP_LO__A                                           0x2440032
#define FEC_OC_RCN_CTL_STEP_LO__W                                           16
#define FEC_OC_RCN_CTL_STEP_LO__M                                           0xFFFF
#define FEC_OC_RCN_CTL_STEP_LO__PRE                                         0x0

#define   FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B                                  0
#define   FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W                                  16
#define   FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M                                  0xFFFF
#define   FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE                                0x0

#define FEC_OC_RCN_CTL_STEP_HI__A                                           0x2440033
#define FEC_OC_RCN_CTL_STEP_HI__W                                           8
#define FEC_OC_RCN_CTL_STEP_HI__M                                           0xFF
#define FEC_OC_RCN_CTL_STEP_HI__PRE                                         0x8

#define   FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B                                  0
#define   FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W                                  8
#define   FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M                                  0xFF
#define   FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE                                0x8

#define FEC_OC_RCN_DTO_OFS_LO__A                                            0x2440034
#define FEC_OC_RCN_DTO_OFS_LO__W                                            16
#define FEC_OC_RCN_DTO_OFS_LO__M                                            0xFFFF
#define FEC_OC_RCN_DTO_OFS_LO__PRE                                          0x0

#define   FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B                                   0
#define   FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W                                   16
#define   FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M                                   0xFFFF
#define   FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE                                 0x0

#define FEC_OC_RCN_DTO_OFS_HI__A                                            0x2440035
#define FEC_OC_RCN_DTO_OFS_HI__W                                            8
#define FEC_OC_RCN_DTO_OFS_HI__M                                            0xFF
#define FEC_OC_RCN_DTO_OFS_HI__PRE                                          0x0

#define   FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B                                   0
#define   FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W                                   8
#define   FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M                                   0xFF
#define   FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE                                 0x0

#define FEC_OC_RCN_DTO_RATE_LO__A                                           0x2440036
#define FEC_OC_RCN_DTO_RATE_LO__W                                           16
#define FEC_OC_RCN_DTO_RATE_LO__M                                           0xFFFF
#define FEC_OC_RCN_DTO_RATE_LO__PRE                                         0x0

#define   FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B                                  0
#define   FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W                                  16
#define   FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M                                  0xFFFF
#define   FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE                                0x0

#define FEC_OC_RCN_DTO_RATE_HI__A                                           0x2440037
#define FEC_OC_RCN_DTO_RATE_HI__W                                           8
#define FEC_OC_RCN_DTO_RATE_HI__M                                           0xFF
#define FEC_OC_RCN_DTO_RATE_HI__PRE                                         0x0

#define   FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B                                  0
#define   FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W                                  8
#define   FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M                                  0xFF
#define   FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE                                0x0

#define FEC_OC_RCN_RATE_CLIP_LO__A                                          0x2440038
#define FEC_OC_RCN_RATE_CLIP_LO__W                                          16
#define FEC_OC_RCN_RATE_CLIP_LO__M                                          0xFFFF
#define FEC_OC_RCN_RATE_CLIP_LO__PRE                                        0x0

#define   FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B                                0
#define   FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W                                16
#define   FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M                                0xFFFF
#define   FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE                              0x0

#define FEC_OC_RCN_RATE_CLIP_HI__A                                          0x2440039
#define FEC_OC_RCN_RATE_CLIP_HI__W                                          8
#define FEC_OC_RCN_RATE_CLIP_HI__M                                          0xFF
#define FEC_OC_RCN_RATE_CLIP_HI__PRE                                        0xF0

#define   FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B                                0
#define   FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W                                8
#define   FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M                                0xFF
#define   FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE                              0xF0

#define FEC_OC_RCN_DYN_RATE_LO__A                                           0x244003A
#define FEC_OC_RCN_DYN_RATE_LO__W                                           16
#define FEC_OC_RCN_DYN_RATE_LO__M                                           0xFFFF
#define FEC_OC_RCN_DYN_RATE_LO__PRE                                         0x0

#define   FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B                                 0
#define   FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W                                 16
#define   FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M                                 0xFFFF
#define   FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE                               0x0

#define FEC_OC_RCN_DYN_RATE_HI__A                                           0x244003B
#define FEC_OC_RCN_DYN_RATE_HI__W                                           8
#define FEC_OC_RCN_DYN_RATE_HI__M                                           0xFF
#define FEC_OC_RCN_DYN_RATE_HI__PRE                                         0x0

#define   FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B                                 0
#define   FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W                                 8
#define   FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M                                 0xFF
#define   FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE                               0x0

#define FEC_OC_SNC_MODE__A                                                  0x2440040
#define FEC_OC_SNC_MODE__W                                                  4
#define FEC_OC_SNC_MODE__M                                                  0xF
#define FEC_OC_SNC_MODE__PRE                                                0x0

#define   FEC_OC_SNC_MODE_UNLOCK_ENABLE__B                                  0
#define   FEC_OC_SNC_MODE_UNLOCK_ENABLE__W                                  1
#define   FEC_OC_SNC_MODE_UNLOCK_ENABLE__M                                  0x1
#define   FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE                                0x0

#define   FEC_OC_SNC_MODE_ERROR_CTL__B                                      1
#define   FEC_OC_SNC_MODE_ERROR_CTL__W                                      2
#define   FEC_OC_SNC_MODE_ERROR_CTL__M                                      0x6
#define   FEC_OC_SNC_MODE_ERROR_CTL__PRE                                    0x0

#define   FEC_OC_SNC_MODE_CORR_DISABLE__B                                   3
#define   FEC_OC_SNC_MODE_CORR_DISABLE__W                                   1
#define   FEC_OC_SNC_MODE_CORR_DISABLE__M                                   0x8
#define   FEC_OC_SNC_MODE_CORR_DISABLE__PRE                                 0x0

#define FEC_OC_SNC_LWM__A                                                   0x2440041
#define FEC_OC_SNC_LWM__W                                                   4
#define FEC_OC_SNC_LWM__M                                                   0xF
#define FEC_OC_SNC_LWM__PRE                                                 0x3

#define   FEC_OC_SNC_LWM_MARK__B                                            0
#define   FEC_OC_SNC_LWM_MARK__W                                            4
#define   FEC_OC_SNC_LWM_MARK__M                                            0xF
#define   FEC_OC_SNC_LWM_MARK__PRE                                          0x3

#define FEC_OC_SNC_HWM__A                                                   0x2440042
#define FEC_OC_SNC_HWM__W                                                   4
#define FEC_OC_SNC_HWM__M                                                   0xF
#define FEC_OC_SNC_HWM__PRE                                                 0x5

#define   FEC_OC_SNC_HWM_MARK__B                                            0
#define   FEC_OC_SNC_HWM_MARK__W                                            4
#define   FEC_OC_SNC_HWM_MARK__M                                            0xF
#define   FEC_OC_SNC_HWM_MARK__PRE                                          0x5

#define FEC_OC_SNC_UNLOCK__A                                                0x2440043
#define FEC_OC_SNC_UNLOCK__W                                                1
#define FEC_OC_SNC_UNLOCK__M                                                0x1
#define FEC_OC_SNC_UNLOCK__PRE                                              0x0

#define   FEC_OC_SNC_UNLOCK_RESTART__B                                      0
#define   FEC_OC_SNC_UNLOCK_RESTART__W                                      1
#define   FEC_OC_SNC_UNLOCK_RESTART__M                                      0x1
#define   FEC_OC_SNC_UNLOCK_RESTART__PRE                                    0x0

#define FEC_OC_SNC_LOCK_COUNT__A                                            0x2440044
#define FEC_OC_SNC_LOCK_COUNT__W                                            12
#define FEC_OC_SNC_LOCK_COUNT__M                                            0xFFF
#define FEC_OC_SNC_LOCK_COUNT__PRE                                          0x0

#define   FEC_OC_SNC_LOCK_COUNT_COUNT__B                                    0
#define   FEC_OC_SNC_LOCK_COUNT_COUNT__W                                    12
#define   FEC_OC_SNC_LOCK_COUNT_COUNT__M                                    0xFFF
#define   FEC_OC_SNC_LOCK_COUNT_COUNT__PRE                                  0x0

#define FEC_OC_SNC_FAIL_COUNT__A                                            0x2440045
#define FEC_OC_SNC_FAIL_COUNT__W                                            12
#define FEC_OC_SNC_FAIL_COUNT__M                                            0xFFF
#define FEC_OC_SNC_FAIL_COUNT__PRE                                          0x0

#define   FEC_OC_SNC_FAIL_COUNT_COUNT__B                                    0
#define   FEC_OC_SNC_FAIL_COUNT_COUNT__W                                    12
#define   FEC_OC_SNC_FAIL_COUNT_COUNT__M                                    0xFFF
#define   FEC_OC_SNC_FAIL_COUNT_COUNT__PRE                                  0x0

#define FEC_OC_SNC_FAIL_PERIOD__A                                           0x2440046
#define FEC_OC_SNC_FAIL_PERIOD__W                                           16
#define FEC_OC_SNC_FAIL_PERIOD__M                                           0xFFFF
#define FEC_OC_SNC_FAIL_PERIOD__PRE                                         0x1171

#define   FEC_OC_SNC_FAIL_PERIOD_PERIOD__B                                  0
#define   FEC_OC_SNC_FAIL_PERIOD_PERIOD__W                                  16
#define   FEC_OC_SNC_FAIL_PERIOD_PERIOD__M                                  0xFFFF
#define   FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE                                0x1171

#define FEC_OC_EMS_MODE__A                                                  0x2440047
#define FEC_OC_EMS_MODE__W                                                  2
#define FEC_OC_EMS_MODE__M                                                  0x3
#define FEC_OC_EMS_MODE__PRE                                                0x0

#define   FEC_OC_EMS_MODE_MODE__B                                           0
#define   FEC_OC_EMS_MODE_MODE__W                                           2
#define   FEC_OC_EMS_MODE_MODE__M                                           0x3
#define   FEC_OC_EMS_MODE_MODE__PRE                                         0x0

#define FEC_OC_IPR_MODE__A                                                  0x2440048
#define FEC_OC_IPR_MODE__W                                                  12
#define FEC_OC_IPR_MODE__M                                                  0xFFF
#define FEC_OC_IPR_MODE__PRE                                                0x0

#define   FEC_OC_IPR_MODE_SERIAL__B                                         0
#define   FEC_OC_IPR_MODE_SERIAL__W                                         1
#define   FEC_OC_IPR_MODE_SERIAL__M                                         0x1
#define   FEC_OC_IPR_MODE_SERIAL__PRE                                       0x0

#define   FEC_OC_IPR_MODE_REVERSE_ORDER__B                                  1
#define   FEC_OC_IPR_MODE_REVERSE_ORDER__W                                  1
#define   FEC_OC_IPR_MODE_REVERSE_ORDER__M                                  0x2
#define   FEC_OC_IPR_MODE_REVERSE_ORDER__PRE                                0x0

#define   FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B                               2
#define   FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W                               1
#define   FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M                               0x4
#define   FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE                             0x0

#define   FEC_OC_IPR_MODE_MCLK_DIS_PAR__B                                   3
#define   FEC_OC_IPR_MODE_MCLK_DIS_PAR__W                                   1
#define   FEC_OC_IPR_MODE_MCLK_DIS_PAR__M                                   0x8
#define   FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE                                 0x0

#define   FEC_OC_IPR_MODE_MVAL_DIS_PAR__B                                   4
#define   FEC_OC_IPR_MODE_MVAL_DIS_PAR__W                                   1
#define   FEC_OC_IPR_MODE_MVAL_DIS_PAR__M                                   0x10
#define   FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE                                 0x0

#define   FEC_OC_IPR_MODE_MERR_DIS_PAR__B                                   5
#define   FEC_OC_IPR_MODE_MERR_DIS_PAR__W                                   1
#define   FEC_OC_IPR_MODE_MERR_DIS_PAR__M                                   0x20
#define   FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE                                 0x0

#define   FEC_OC_IPR_MODE_MD_DIS_PAR__B                                     6
#define   FEC_OC_IPR_MODE_MD_DIS_PAR__W                                     1
#define   FEC_OC_IPR_MODE_MD_DIS_PAR__M                                     0x40
#define   FEC_OC_IPR_MODE_MD_DIS_PAR__PRE                                   0x0

#define   FEC_OC_IPR_MODE_MCLK_DIS_ERR__B                                   7
#define   FEC_OC_IPR_MODE_MCLK_DIS_ERR__W                                   1
#define   FEC_OC_IPR_MODE_MCLK_DIS_ERR__M                                   0x80
#define   FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE                                 0x0

#define   FEC_OC_IPR_MODE_MVAL_DIS_ERR__B                                   8
#define   FEC_OC_IPR_MODE_MVAL_DIS_ERR__W                                   1
#define   FEC_OC_IPR_MODE_MVAL_DIS_ERR__M                                   0x100
#define   FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE                                 0x0

#define   FEC_OC_IPR_MODE_MERR_DIS_ERR__B                                   9
#define   FEC_OC_IPR_MODE_MERR_DIS_ERR__W                                   1
#define   FEC_OC_IPR_MODE_MERR_DIS_ERR__M                                   0x200
#define   FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE                                 0x0

#define   FEC_OC_IPR_MODE_MD_DIS_ERR__B                                     10
#define   FEC_OC_IPR_MODE_MD_DIS_ERR__W                                     1
#define   FEC_OC_IPR_MODE_MD_DIS_ERR__M                                     0x400
#define   FEC_OC_IPR_MODE_MD_DIS_ERR__PRE                                   0x0

#define   FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B                                  11
#define   FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W                                  1
#define   FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M                                  0x800
#define   FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE                                0x0

#define FEC_OC_IPR_INVERT__A                                                0x2440049
#define FEC_OC_IPR_INVERT__W                                                12
#define FEC_OC_IPR_INVERT__M                                                0xFFF
#define FEC_OC_IPR_INVERT__PRE                                              0x0

#define   FEC_OC_IPR_INVERT_MD0__B                                          0
#define   FEC_OC_IPR_INVERT_MD0__W                                          1
#define   FEC_OC_IPR_INVERT_MD0__M                                          0x1
#define   FEC_OC_IPR_INVERT_MD0__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MD1__B                                          1
#define   FEC_OC_IPR_INVERT_MD1__W                                          1
#define   FEC_OC_IPR_INVERT_MD1__M                                          0x2
#define   FEC_OC_IPR_INVERT_MD1__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MD2__B                                          2
#define   FEC_OC_IPR_INVERT_MD2__W                                          1
#define   FEC_OC_IPR_INVERT_MD2__M                                          0x4
#define   FEC_OC_IPR_INVERT_MD2__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MD3__B                                          3
#define   FEC_OC_IPR_INVERT_MD3__W                                          1
#define   FEC_OC_IPR_INVERT_MD3__M                                          0x8
#define   FEC_OC_IPR_INVERT_MD3__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MD4__B                                          4
#define   FEC_OC_IPR_INVERT_MD4__W                                          1
#define   FEC_OC_IPR_INVERT_MD4__M                                          0x10
#define   FEC_OC_IPR_INVERT_MD4__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MD5__B                                          5
#define   FEC_OC_IPR_INVERT_MD5__W                                          1
#define   FEC_OC_IPR_INVERT_MD5__M                                          0x20
#define   FEC_OC_IPR_INVERT_MD5__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MD6__B                                          6
#define   FEC_OC_IPR_INVERT_MD6__W                                          1
#define   FEC_OC_IPR_INVERT_MD6__M                                          0x40
#define   FEC_OC_IPR_INVERT_MD6__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MD7__B                                          7
#define   FEC_OC_IPR_INVERT_MD7__W                                          1
#define   FEC_OC_IPR_INVERT_MD7__M                                          0x80
#define   FEC_OC_IPR_INVERT_MD7__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MERR__B                                         8
#define   FEC_OC_IPR_INVERT_MERR__W                                         1
#define   FEC_OC_IPR_INVERT_MERR__M                                         0x100
#define   FEC_OC_IPR_INVERT_MERR__PRE                                       0x0

#define   FEC_OC_IPR_INVERT_MSTRT__B                                        9
#define   FEC_OC_IPR_INVERT_MSTRT__W                                        1
#define   FEC_OC_IPR_INVERT_MSTRT__M                                        0x200
#define   FEC_OC_IPR_INVERT_MSTRT__PRE                                      0x0

#define   FEC_OC_IPR_INVERT_MVAL__B                                         10
#define   FEC_OC_IPR_INVERT_MVAL__W                                         1
#define   FEC_OC_IPR_INVERT_MVAL__M                                         0x400
#define   FEC_OC_IPR_INVERT_MVAL__PRE                                       0x0

#define   FEC_OC_IPR_INVERT_MCLK__B                                         11
#define   FEC_OC_IPR_INVERT_MCLK__W                                         1
#define   FEC_OC_IPR_INVERT_MCLK__M                                         0x800
#define   FEC_OC_IPR_INVERT_MCLK__PRE                                       0x0

#define FEC_OC_OCR_MODE__A                                                  0x2440050
#define FEC_OC_OCR_MODE__W                                                  4
#define FEC_OC_OCR_MODE__M                                                  0xF
#define FEC_OC_OCR_MODE__PRE                                                0x0

#define   FEC_OC_OCR_MODE_MB_SELECT__B                                      0
#define   FEC_OC_OCR_MODE_MB_SELECT__W                                      1
#define   FEC_OC_OCR_MODE_MB_SELECT__M                                      0x1
#define   FEC_OC_OCR_MODE_MB_SELECT__PRE                                    0x0

#define   FEC_OC_OCR_MODE_GRAB_ENABLE__B                                    1
#define   FEC_OC_OCR_MODE_GRAB_ENABLE__W                                    1
#define   FEC_OC_OCR_MODE_GRAB_ENABLE__M                                    0x2
#define   FEC_OC_OCR_MODE_GRAB_ENABLE__PRE                                  0x0

#define   FEC_OC_OCR_MODE_GRAB_SELECT__B                                    2
#define   FEC_OC_OCR_MODE_GRAB_SELECT__W                                    1
#define   FEC_OC_OCR_MODE_GRAB_SELECT__M                                    0x4
#define   FEC_OC_OCR_MODE_GRAB_SELECT__PRE                                  0x0

#define   FEC_OC_OCR_MODE_GRAB_COUNTED__B                                   3
#define   FEC_OC_OCR_MODE_GRAB_COUNTED__W                                   1
#define   FEC_OC_OCR_MODE_GRAB_COUNTED__M                                   0x8
#define   FEC_OC_OCR_MODE_GRAB_COUNTED__PRE                                 0x0

#define FEC_OC_OCR_RATE__A                                                  0x2440051
#define FEC_OC_OCR_RATE__W                                                  4
#define FEC_OC_OCR_RATE__M                                                  0xF
#define FEC_OC_OCR_RATE__PRE                                                0x0

#define   FEC_OC_OCR_RATE_RATE__B                                           0
#define   FEC_OC_OCR_RATE_RATE__W                                           4
#define   FEC_OC_OCR_RATE_RATE__M                                           0xF
#define   FEC_OC_OCR_RATE_RATE__PRE                                         0x0

#define FEC_OC_OCR_INVERT__A                                                0x2440052
#define FEC_OC_OCR_INVERT__W                                                12
#define FEC_OC_OCR_INVERT__M                                                0xFFF
#define FEC_OC_OCR_INVERT__PRE                                              0x800

#define   FEC_OC_OCR_INVERT_INVERT__B                                       0
#define   FEC_OC_OCR_INVERT_INVERT__W                                       12
#define   FEC_OC_OCR_INVERT_INVERT__M                                       0xFFF
#define   FEC_OC_OCR_INVERT_INVERT__PRE                                     0x800

#define FEC_OC_OCR_GRAB_COUNT__A                                            0x2440053
#define FEC_OC_OCR_GRAB_COUNT__W                                            16
#define FEC_OC_OCR_GRAB_COUNT__M                                            0xFFFF
#define FEC_OC_OCR_GRAB_COUNT__PRE                                          0x0

#define   FEC_OC_OCR_GRAB_COUNT_COUNT__B                                    0
#define   FEC_OC_OCR_GRAB_COUNT_COUNT__W                                    16
#define   FEC_OC_OCR_GRAB_COUNT_COUNT__M                                    0xFFFF
#define   FEC_OC_OCR_GRAB_COUNT_COUNT__PRE                                  0x0

#define FEC_OC_OCR_GRAB_SYNC__A                                             0x2440054
#define FEC_OC_OCR_GRAB_SYNC__W                                             8
#define FEC_OC_OCR_GRAB_SYNC__M                                             0xFF
#define FEC_OC_OCR_GRAB_SYNC__PRE                                           0x0

#define   FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B                                  0
#define   FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W                                  3
#define   FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M                                  0x7
#define   FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE                                0x0

#define   FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B                                   3
#define   FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W                                   4
#define   FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M                                   0x78
#define   FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE                                 0x0

#define   FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B                                 7
#define   FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W                                 1
#define   FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M                                 0x80
#define   FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE                               0x0

#define FEC_OC_OCR_GRAB_RD0__A                                              0x2440055
#define FEC_OC_OCR_GRAB_RD0__W                                              10
#define FEC_OC_OCR_GRAB_RD0__M                                              0x3FF
#define FEC_OC_OCR_GRAB_RD0__PRE                                            0x0

#define   FEC_OC_OCR_GRAB_RD0_DATA__B                                       0
#define   FEC_OC_OCR_GRAB_RD0_DATA__W                                       10
#define   FEC_OC_OCR_GRAB_RD0_DATA__M                                       0x3FF
#define   FEC_OC_OCR_GRAB_RD0_DATA__PRE                                     0x0

#define FEC_OC_OCR_GRAB_RD1__A                                              0x2440056
#define FEC_OC_OCR_GRAB_RD1__W                                              10
#define FEC_OC_OCR_GRAB_RD1__M                                              0x3FF
#define FEC_OC_OCR_GRAB_RD1__PRE                                            0x0

#define   FEC_OC_OCR_GRAB_RD1_DATA__B                                       0
#define   FEC_OC_OCR_GRAB_RD1_DATA__W                                       10
#define   FEC_OC_OCR_GRAB_RD1_DATA__M                                       0x3FF
#define   FEC_OC_OCR_GRAB_RD1_DATA__PRE                                     0x0

#define FEC_OC_OCR_GRAB_RD2__A                                              0x2440057
#define FEC_OC_OCR_GRAB_RD2__W                                              10
#define FEC_OC_OCR_GRAB_RD2__M                                              0x3FF
#define FEC_OC_OCR_GRAB_RD2__PRE                                            0x0

#define   FEC_OC_OCR_GRAB_RD2_DATA__B                                       0
#define   FEC_OC_OCR_GRAB_RD2_DATA__W                                       10
#define   FEC_OC_OCR_GRAB_RD2_DATA__M                                       0x3FF
#define   FEC_OC_OCR_GRAB_RD2_DATA__PRE                                     0x0

#define FEC_OC_OCR_GRAB_RD3__A                                              0x2440058
#define FEC_OC_OCR_GRAB_RD3__W                                              10
#define FEC_OC_OCR_GRAB_RD3__M                                              0x3FF
#define FEC_OC_OCR_GRAB_RD3__PRE                                            0x0

#define   FEC_OC_OCR_GRAB_RD3_DATA__B                                       0
#define   FEC_OC_OCR_GRAB_RD3_DATA__W                                       10
#define   FEC_OC_OCR_GRAB_RD3_DATA__M                                       0x3FF
#define   FEC_OC_OCR_GRAB_RD3_DATA__PRE                                     0x0

#define FEC_OC_OCR_GRAB_RD4__A                                              0x2440059
#define FEC_OC_OCR_GRAB_RD4__W                                              10
#define FEC_OC_OCR_GRAB_RD4__M                                              0x3FF
#define FEC_OC_OCR_GRAB_RD4__PRE                                            0x0

#define   FEC_OC_OCR_GRAB_RD4_DATA__B                                       0
#define   FEC_OC_OCR_GRAB_RD4_DATA__W                                       10
#define   FEC_OC_OCR_GRAB_RD4_DATA__M                                       0x3FF
#define   FEC_OC_OCR_GRAB_RD4_DATA__PRE                                     0x0

#define FEC_OC_OCR_GRAB_RD5__A                                              0x244005A
#define FEC_OC_OCR_GRAB_RD5__W                                              10
#define FEC_OC_OCR_GRAB_RD5__M                                              0x3FF
#define FEC_OC_OCR_GRAB_RD5__PRE                                            0x0

#define   FEC_OC_OCR_GRAB_RD5_DATA__B                                       0
#define   FEC_OC_OCR_GRAB_RD5_DATA__W                                       10
#define   FEC_OC_OCR_GRAB_RD5_DATA__M                                       0x3FF
#define   FEC_OC_OCR_GRAB_RD5_DATA__PRE                                     0x0

#define FEC_DI_RAM__A                                                       0x2450000

#define FEC_RS_RAM__A                                                       0x2460000

#define FEC_OC_RAM__A                                                       0x2470000

#define IQM_COMM_EXEC__A                                                    0x1800000
#define IQM_COMM_EXEC__W                                                    2
#define IQM_COMM_EXEC__M                                                    0x3
#define IQM_COMM_EXEC__PRE                                                  0x0
#define   IQM_COMM_EXEC_STOP                                                0x0
#define   IQM_COMM_EXEC_ACTIVE                                              0x1
#define   IQM_COMM_EXEC_HOLD                                                0x2

#define IQM_COMM_MB__A                                                      0x1800002
#define IQM_COMM_MB__W                                                      16
#define IQM_COMM_MB__M                                                      0xFFFF
#define IQM_COMM_MB__PRE                                                    0x0
#define IQM_COMM_INT_REQ__A                                                 0x1800003
#define IQM_COMM_INT_REQ__W                                                 2
#define IQM_COMM_INT_REQ__M                                                 0x3
#define IQM_COMM_INT_REQ__PRE                                               0x0

#define   IQM_COMM_INT_REQ_AF_REQ__B                                        0
#define   IQM_COMM_INT_REQ_AF_REQ__W                                        1
#define   IQM_COMM_INT_REQ_AF_REQ__M                                        0x1
#define   IQM_COMM_INT_REQ_AF_REQ__PRE                                      0x0

#define   IQM_COMM_INT_REQ_CF_REQ__B                                        1
#define   IQM_COMM_INT_REQ_CF_REQ__W                                        1
#define   IQM_COMM_INT_REQ_CF_REQ__M                                        0x2
#define   IQM_COMM_INT_REQ_CF_REQ__PRE                                      0x0

#define IQM_COMM_INT_STA__A                                                 0x1800005
#define IQM_COMM_INT_STA__W                                                 16
#define IQM_COMM_INT_STA__M                                                 0xFFFF
#define IQM_COMM_INT_STA__PRE                                               0x0
#define IQM_COMM_INT_MSK__A                                                 0x1800006
#define IQM_COMM_INT_MSK__W                                                 16
#define IQM_COMM_INT_MSK__M                                                 0xFFFF
#define IQM_COMM_INT_MSK__PRE                                               0x0
#define IQM_COMM_INT_STM__A                                                 0x1800007
#define IQM_COMM_INT_STM__W                                                 16
#define IQM_COMM_INT_STM__M                                                 0xFFFF
#define IQM_COMM_INT_STM__PRE                                               0x0

#define IQM_FS_COMM_EXEC__A                                                 0x1820000
#define IQM_FS_COMM_EXEC__W                                                 2
#define IQM_FS_COMM_EXEC__M                                                 0x3
#define IQM_FS_COMM_EXEC__PRE                                               0x0
#define   IQM_FS_COMM_EXEC_STOP                                             0x0
#define   IQM_FS_COMM_EXEC_ACTIVE                                           0x1
#define   IQM_FS_COMM_EXEC_HOLD                                             0x2

#define IQM_FS_COMM_MB__A                                                   0x1820002
#define IQM_FS_COMM_MB__W                                                   2
#define IQM_FS_COMM_MB__M                                                   0x3
#define IQM_FS_COMM_MB__PRE                                                 0x0
#define   IQM_FS_COMM_MB_CTL__B                                             0
#define   IQM_FS_COMM_MB_CTL__W                                             1
#define   IQM_FS_COMM_MB_CTL__M                                             0x1
#define   IQM_FS_COMM_MB_CTL__PRE                                           0x0
#define     IQM_FS_COMM_MB_CTL_CTL_OFF                                      0x0
#define     IQM_FS_COMM_MB_CTL_CTL_ON                                       0x1
#define   IQM_FS_COMM_MB_OBS__B                                             1
#define   IQM_FS_COMM_MB_OBS__W                                             1
#define   IQM_FS_COMM_MB_OBS__M                                             0x2
#define   IQM_FS_COMM_MB_OBS__PRE                                           0x0
#define     IQM_FS_COMM_MB_OBS_OBS_OFF                                      0x0
#define     IQM_FS_COMM_MB_OBS_OBS_ON                                       0x2

#define IQM_FS_RATE_OFS_LO__A                                               0x1820010
#define IQM_FS_RATE_OFS_LO__W                                               16
#define IQM_FS_RATE_OFS_LO__M                                               0xFFFF
#define IQM_FS_RATE_OFS_LO__PRE                                             0x0
#define IQM_FS_RATE_OFS_HI__A                                               0x1820011
#define IQM_FS_RATE_OFS_HI__W                                               12
#define IQM_FS_RATE_OFS_HI__M                                               0xFFF
#define IQM_FS_RATE_OFS_HI__PRE                                             0x0
#define IQM_FS_RATE_LO__A                                                   0x1820012
#define IQM_FS_RATE_LO__W                                                   16
#define IQM_FS_RATE_LO__M                                                   0xFFFF
#define IQM_FS_RATE_LO__PRE                                                 0x0
#define IQM_FS_RATE_HI__A                                                   0x1820013
#define IQM_FS_RATE_HI__W                                                   12
#define IQM_FS_RATE_HI__M                                                   0xFFF
#define IQM_FS_RATE_HI__PRE                                                 0x0

#define IQM_FS_ADJ_SEL__A                                                   0x1820014
#define IQM_FS_ADJ_SEL__W                                                   2
#define IQM_FS_ADJ_SEL__M                                                   0x3
#define IQM_FS_ADJ_SEL__PRE                                                 0x0
#define   IQM_FS_ADJ_SEL_OFF                                                0x0
#define   IQM_FS_ADJ_SEL_QAM                                                0x1
#define   IQM_FS_ADJ_SEL_VSB                                                0x2

#define IQM_FD_COMM_EXEC__A                                                 0x1830000
#define IQM_FD_COMM_EXEC__W                                                 2
#define IQM_FD_COMM_EXEC__M                                                 0x3
#define IQM_FD_COMM_EXEC__PRE                                               0x0
#define   IQM_FD_COMM_EXEC_STOP                                             0x0
#define   IQM_FD_COMM_EXEC_ACTIVE                                           0x1
#define   IQM_FD_COMM_EXEC_HOLD                                             0x2

#define IQM_FD_COMM_MB__A                                                   0x1830002
#define IQM_FD_COMM_MB__W                                                   2
#define IQM_FD_COMM_MB__M                                                   0x3
#define IQM_FD_COMM_MB__PRE                                                 0x0
#define   IQM_FD_COMM_MB_CTL__B                                             0
#define   IQM_FD_COMM_MB_CTL__W                                             1
#define   IQM_FD_COMM_MB_CTL__M                                             0x1
#define   IQM_FD_COMM_MB_CTL__PRE                                           0x0
#define     IQM_FD_COMM_MB_CTL_CTL_OFF                                      0x0
#define     IQM_FD_COMM_MB_CTL_CTL_ON                                       0x1
#define   IQM_FD_COMM_MB_OBS__B                                             1
#define   IQM_FD_COMM_MB_OBS__W                                             1
#define   IQM_FD_COMM_MB_OBS__M                                             0x2
#define   IQM_FD_COMM_MB_OBS__PRE                                           0x0
#define     IQM_FD_COMM_MB_OBS_OBS_OFF                                      0x0
#define     IQM_FD_COMM_MB_OBS_OBS_ON                                       0x2

#define IQM_RC_COMM_EXEC__A                                                 0x1840000
#define IQM_RC_COMM_EXEC__W                                                 2
#define IQM_RC_COMM_EXEC__M                                                 0x3
#define IQM_RC_COMM_EXEC__PRE                                               0x0
#define   IQM_RC_COMM_EXEC_STOP                                             0x0
#define   IQM_RC_COMM_EXEC_ACTIVE                                           0x1
#define   IQM_RC_COMM_EXEC_HOLD                                             0x2

#define IQM_RC_COMM_MB__A                                                   0x1840002
#define IQM_RC_COMM_MB__W                                                   2
#define IQM_RC_COMM_MB__M                                                   0x3
#define IQM_RC_COMM_MB__PRE                                                 0x0
#define   IQM_RC_COMM_MB_CTL__B                                             0
#define   IQM_RC_COMM_MB_CTL__W                                             1
#define   IQM_RC_COMM_MB_CTL__M                                             0x1
#define   IQM_RC_COMM_MB_CTL__PRE                                           0x0
#define     IQM_RC_COMM_MB_CTL_CTL_OFF                                      0x0
#define     IQM_RC_COMM_MB_CTL_CTL_ON                                       0x1
#define   IQM_RC_COMM_MB_OBS__B                                             1
#define   IQM_RC_COMM_MB_OBS__W                                             1
#define   IQM_RC_COMM_MB_OBS__M                                             0x2
#define   IQM_RC_COMM_MB_OBS__PRE                                           0x0
#define     IQM_RC_COMM_MB_OBS_OBS_OFF                                      0x0
#define     IQM_RC_COMM_MB_OBS_OBS_ON                                       0x2

#define IQM_RC_RATE_OFS_LO__A                                               0x1840010
#define IQM_RC_RATE_OFS_LO__W                                               16
#define IQM_RC_RATE_OFS_LO__M                                               0xFFFF
#define IQM_RC_RATE_OFS_LO__PRE                                             0x0
#define IQM_RC_RATE_OFS_HI__A                                               0x1840011
#define IQM_RC_RATE_OFS_HI__W                                               8
#define IQM_RC_RATE_OFS_HI__M                                               0xFF
#define IQM_RC_RATE_OFS_HI__PRE                                             0x0
#define IQM_RC_RATE_LO__A                                                   0x1840012
#define IQM_RC_RATE_LO__W                                                   16
#define IQM_RC_RATE_LO__M                                                   0xFFFF
#define IQM_RC_RATE_LO__PRE                                                 0x0
#define IQM_RC_RATE_HI__A                                                   0x1840013
#define IQM_RC_RATE_HI__W                                                   8
#define IQM_RC_RATE_HI__M                                                   0xFF
#define IQM_RC_RATE_HI__PRE                                                 0x0

#define IQM_RC_ADJ_SEL__A                                                   0x1840014
#define IQM_RC_ADJ_SEL__W                                                   2
#define IQM_RC_ADJ_SEL__M                                                   0x3
#define IQM_RC_ADJ_SEL__PRE                                                 0x0
#define   IQM_RC_ADJ_SEL_OFF                                                0x0
#define   IQM_RC_ADJ_SEL_QAM                                                0x1
#define   IQM_RC_ADJ_SEL_VSB                                                0x2

#define IQM_RC_CROUT_ENA__A                                                 0x1840015
#define IQM_RC_CROUT_ENA__W                                                 1
#define IQM_RC_CROUT_ENA__M                                                 0x1
#define IQM_RC_CROUT_ENA__PRE                                               0x0

#define   IQM_RC_CROUT_ENA_ENA__B                                           0
#define   IQM_RC_CROUT_ENA_ENA__W                                           1
#define   IQM_RC_CROUT_ENA_ENA__M                                           0x1
#define   IQM_RC_CROUT_ENA_ENA__PRE                                         0x0

#define IQM_RC_STRETCH__A                                                   0x1840016
#define IQM_RC_STRETCH__W                                                   5
#define IQM_RC_STRETCH__M                                                   0x1F
#define IQM_RC_STRETCH__PRE                                                 0x0
#define   IQM_RC_STRETCH_QAM_B_64                                           0x1E
#define   IQM_RC_STRETCH_QAM_B_256                                          0x1C
#define   IQM_RC_STRETCH_ATV                                                0xF

#define IQM_RT_COMM_EXEC__A                                                 0x1850000
#define IQM_RT_COMM_EXEC__W                                                 2
#define IQM_RT_COMM_EXEC__M                                                 0x3
#define IQM_RT_COMM_EXEC__PRE                                               0x0
#define   IQM_RT_COMM_EXEC_STOP                                             0x0
#define   IQM_RT_COMM_EXEC_ACTIVE                                           0x1
#define   IQM_RT_COMM_EXEC_HOLD                                             0x2

#define IQM_RT_COMM_MB__A                                                   0x1850002
#define IQM_RT_COMM_MB__W                                                   2
#define IQM_RT_COMM_MB__M                                                   0x3
#define IQM_RT_COMM_MB__PRE                                                 0x0
#define   IQM_RT_COMM_MB_CTL__B                                             0
#define   IQM_RT_COMM_MB_CTL__W                                             1
#define   IQM_RT_COMM_MB_CTL__M                                             0x1
#define   IQM_RT_COMM_MB_CTL__PRE                                           0x0
#define     IQM_RT_COMM_MB_CTL_CTL_OFF                                      0x0
#define     IQM_RT_COMM_MB_CTL_CTL_ON                                       0x1
#define   IQM_RT_COMM_MB_OBS__B                                             1
#define   IQM_RT_COMM_MB_OBS__W                                             1
#define   IQM_RT_COMM_MB_OBS__M                                             0x2
#define   IQM_RT_COMM_MB_OBS__PRE                                           0x0
#define     IQM_RT_COMM_MB_OBS_OBS_OFF                                      0x0
#define     IQM_RT_COMM_MB_OBS_OBS_ON                                       0x2

#define IQM_RT_ACTIVE__A                                                    0x1850010
#define IQM_RT_ACTIVE__W                                                    2
#define IQM_RT_ACTIVE__M                                                    0x3
#define IQM_RT_ACTIVE__PRE                                                  0x0

#define   IQM_RT_ACTIVE_ACTIVE_RT__B                                        0
#define   IQM_RT_ACTIVE_ACTIVE_RT__W                                        1
#define   IQM_RT_ACTIVE_ACTIVE_RT__M                                        0x1
#define   IQM_RT_ACTIVE_ACTIVE_RT__PRE                                      0x0
#define     IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF                             0x0
#define     IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON                              0x1

#define   IQM_RT_ACTIVE_ACTIVE_CR__B                                        1
#define   IQM_RT_ACTIVE_ACTIVE_CR__W                                        1
#define   IQM_RT_ACTIVE_ACTIVE_CR__M                                        0x2
#define   IQM_RT_ACTIVE_ACTIVE_CR__PRE                                      0x0
#define     IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF                              0x0
#define     IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON                               0x2

#define IQM_RT_LO_INCR__A                                                   0x1850011
#define IQM_RT_LO_INCR__W                                                   12
#define IQM_RT_LO_INCR__M                                                   0xFFF
#define IQM_RT_LO_INCR__PRE                                                 0x588
#define   IQM_RT_LO_INCR_FM                                                 0x0
#define   IQM_RT_LO_INCR_MN                                                 0x588

#define IQM_RT_ROT_BP__A                                                    0x1850012
#define IQM_RT_ROT_BP__W                                                    2
#define IQM_RT_ROT_BP__M                                                    0x3
#define IQM_RT_ROT_BP__PRE                                                  0x0

#define   IQM_RT_ROT_BP_ROT_OFF__B                                          0
#define   IQM_RT_ROT_BP_ROT_OFF__W                                          1
#define   IQM_RT_ROT_BP_ROT_OFF__M                                          0x1
#define   IQM_RT_ROT_BP_ROT_OFF__PRE                                        0x0
#define     IQM_RT_ROT_BP_ROT_OFF_ACTIVE                                    0x0
#define     IQM_RT_ROT_BP_ROT_OFF_OFF                                       0x1

#define   IQM_RT_ROT_BP_ROT_BPF__B                                          1
#define   IQM_RT_ROT_BP_ROT_BPF__W                                          1
#define   IQM_RT_ROT_BP_ROT_BPF__M                                          0x2
#define   IQM_RT_ROT_BP_ROT_BPF__PRE                                        0x0

#define IQM_RT_LP_BP__A                                                     0x1850013
#define IQM_RT_LP_BP__W                                                     1
#define IQM_RT_LP_BP__M                                                     0x1
#define IQM_RT_LP_BP__PRE                                                   0x0

#define IQM_RT_DELAY__A                                                     0x1850014
#define IQM_RT_DELAY__W                                                     7
#define IQM_RT_DELAY__M                                                     0x7F
#define IQM_RT_DELAY__PRE                                                   0x45

#define IQM_CF_COMM_EXEC__A                                                 0x1860000
#define IQM_CF_COMM_EXEC__W                                                 2
#define IQM_CF_COMM_EXEC__M                                                 0x3
#define IQM_CF_COMM_EXEC__PRE                                               0x0
#define   IQM_CF_COMM_EXEC_STOP                                             0x0
#define   IQM_CF_COMM_EXEC_ACTIVE                                           0x1
#define   IQM_CF_COMM_EXEC_HOLD                                             0x2

#define IQM_CF_COMM_MB__A                                                   0x1860002
#define IQM_CF_COMM_MB__W                                                   2
#define IQM_CF_COMM_MB__M                                                   0x3
#define IQM_CF_COMM_MB__PRE                                                 0x0
#define   IQM_CF_COMM_MB_CTL__B                                             0
#define   IQM_CF_COMM_MB_CTL__W                                             1
#define   IQM_CF_COMM_MB_CTL__M                                             0x1
#define   IQM_CF_COMM_MB_CTL__PRE                                           0x0
#define     IQM_CF_COMM_MB_CTL_CTL_OFF                                      0x0
#define     IQM_CF_COMM_MB_CTL_CTL_ON                                       0x1
#define   IQM_CF_COMM_MB_OBS__B                                             1
#define   IQM_CF_COMM_MB_OBS__W                                             1
#define   IQM_CF_COMM_MB_OBS__M                                             0x2
#define   IQM_CF_COMM_MB_OBS__PRE                                           0x0
#define     IQM_CF_COMM_MB_OBS_OBS_OFF                                      0x0
#define     IQM_CF_COMM_MB_OBS_OBS_ON                                       0x2

#define IQM_CF_COMM_INT_REQ__A                                              0x1860003
#define IQM_CF_COMM_INT_REQ__W                                              1
#define IQM_CF_COMM_INT_REQ__M                                              0x1
#define IQM_CF_COMM_INT_REQ__PRE                                            0x0
#define IQM_CF_COMM_INT_STA__A                                              0x1860005
#define IQM_CF_COMM_INT_STA__W                                              1
#define IQM_CF_COMM_INT_STA__M                                              0x1
#define IQM_CF_COMM_INT_STA__PRE                                            0x0
#define   IQM_CF_COMM_INT_STA_PM__B                                         0
#define   IQM_CF_COMM_INT_STA_PM__W                                         1
#define   IQM_CF_COMM_INT_STA_PM__M                                         0x1
#define   IQM_CF_COMM_INT_STA_PM__PRE                                       0x0

#define IQM_CF_COMM_INT_MSK__A                                              0x1860006
#define IQM_CF_COMM_INT_MSK__W                                              1
#define IQM_CF_COMM_INT_MSK__M                                              0x1
#define IQM_CF_COMM_INT_MSK__PRE                                            0x0
#define   IQM_CF_COMM_INT_MSK_PM__B                                         0
#define   IQM_CF_COMM_INT_MSK_PM__W                                         1
#define   IQM_CF_COMM_INT_MSK_PM__M                                         0x1
#define   IQM_CF_COMM_INT_MSK_PM__PRE                                       0x0

#define IQM_CF_COMM_INT_STM__A                                              0x1860007
#define IQM_CF_COMM_INT_STM__W                                              1
#define IQM_CF_COMM_INT_STM__M                                              0x1
#define IQM_CF_COMM_INT_STM__PRE                                            0x0
#define   IQM_CF_COMM_INT_STM_PM__B                                         0
#define   IQM_CF_COMM_INT_STM_PM__W                                         1
#define   IQM_CF_COMM_INT_STM_PM__M                                         0x1
#define   IQM_CF_COMM_INT_STM_PM__PRE                                       0x0

#define IQM_CF_SYMMETRIC__A                                                 0x1860010
#define IQM_CF_SYMMETRIC__W                                                 2
#define IQM_CF_SYMMETRIC__M                                                 0x3
#define IQM_CF_SYMMETRIC__PRE                                               0x0

#define   IQM_CF_SYMMETRIC_RE__B                                            0
#define   IQM_CF_SYMMETRIC_RE__W                                            1
#define   IQM_CF_SYMMETRIC_RE__M                                            0x1
#define   IQM_CF_SYMMETRIC_RE__PRE                                          0x0

#define   IQM_CF_SYMMETRIC_IM__B                                            1
#define   IQM_CF_SYMMETRIC_IM__W                                            1
#define   IQM_CF_SYMMETRIC_IM__M                                            0x2
#define   IQM_CF_SYMMETRIC_IM__PRE                                          0x0

#define IQM_CF_MIDTAP__A                                                    0x1860011
#define IQM_CF_MIDTAP__W                                                    2
#define IQM_CF_MIDTAP__M                                                    0x3
#define IQM_CF_MIDTAP__PRE                                                  0x3

#define   IQM_CF_MIDTAP_RE__B                                               0
#define   IQM_CF_MIDTAP_RE__W                                               1
#define   IQM_CF_MIDTAP_RE__M                                               0x1
#define   IQM_CF_MIDTAP_RE__PRE                                             0x1

#define   IQM_CF_MIDTAP_IM__B                                               1
#define   IQM_CF_MIDTAP_IM__W                                               1
#define   IQM_CF_MIDTAP_IM__M                                               0x2
#define   IQM_CF_MIDTAP_IM__PRE                                             0x2

#define IQM_CF_OUT_ENA__A                                                   0x1860012
#define IQM_CF_OUT_ENA__W                                                   3
#define IQM_CF_OUT_ENA__M                                                   0x7
#define IQM_CF_OUT_ENA__PRE                                                 0x0

#define   IQM_CF_OUT_ENA_ATV__B                                             0
#define   IQM_CF_OUT_ENA_ATV__W                                             1
#define   IQM_CF_OUT_ENA_ATV__M                                             0x1
#define   IQM_CF_OUT_ENA_ATV__PRE                                           0x0

#define   IQM_CF_OUT_ENA_QAM__B                                             1
#define   IQM_CF_OUT_ENA_QAM__W                                             1
#define   IQM_CF_OUT_ENA_QAM__M                                             0x2
#define   IQM_CF_OUT_ENA_QAM__PRE                                           0x0

#define   IQM_CF_OUT_ENA_VSB__B                                             2
#define   IQM_CF_OUT_ENA_VSB__W                                             1
#define   IQM_CF_OUT_ENA_VSB__M                                             0x4
#define   IQM_CF_OUT_ENA_VSB__PRE                                           0x0

#define IQM_CF_ADJ_SEL__A                                                   0x1860013
#define IQM_CF_ADJ_SEL__W                                                   2
#define IQM_CF_ADJ_SEL__M                                                   0x3
#define IQM_CF_ADJ_SEL__PRE                                                 0x0
#define IQM_CF_SCALE__A                                                     0x1860014
#define IQM_CF_SCALE__W                                                     14
#define IQM_CF_SCALE__M                                                     0x3FFF
#define IQM_CF_SCALE__PRE                                                   0x400

#define IQM_CF_SCALE_SH__A                                                  0x1860015
#define IQM_CF_SCALE_SH__W                                                  2
#define IQM_CF_SCALE_SH__M                                                  0x3
#define IQM_CF_SCALE_SH__PRE                                                0x0

#define IQM_CF_AMP__A                                                       0x1860016
#define IQM_CF_AMP__W                                                       14
#define IQM_CF_AMP__M                                                       0x3FFF
#define IQM_CF_AMP__PRE                                                     0x0

#define IQM_CF_POW_MEAS_LEN__A                                              0x1860017
#define IQM_CF_POW_MEAS_LEN__W                                              3
#define IQM_CF_POW_MEAS_LEN__M                                              0x7
#define IQM_CF_POW_MEAS_LEN__PRE                                            0x2
#define   IQM_CF_POW_MEAS_LEN_QAM_B_64                                      0x1
#define   IQM_CF_POW_MEAS_LEN_QAM_B_256                                     0x1

#define IQM_CF_POW__A                                                       0x1860018
#define IQM_CF_POW__W                                                       16
#define IQM_CF_POW__M                                                       0xFFFF
#define IQM_CF_POW__PRE                                                     0x2
#define IQM_CF_TAP_RE0__A                                                   0x1860020
#define IQM_CF_TAP_RE0__W                                                   7
#define IQM_CF_TAP_RE0__M                                                   0x7F
#define IQM_CF_TAP_RE0__PRE                                                 0x2
#define IQM_CF_TAP_RE1__A                                                   0x1860021
#define IQM_CF_TAP_RE1__W                                                   7
#define IQM_CF_TAP_RE1__M                                                   0x7F
#define IQM_CF_TAP_RE1__PRE                                                 0x2
#define IQM_CF_TAP_RE2__A                                                   0x1860022
#define IQM_CF_TAP_RE2__W                                                   7
#define IQM_CF_TAP_RE2__M                                                   0x7F
#define IQM_CF_TAP_RE2__PRE                                                 0x2
#define IQM_CF_TAP_RE3__A                                                   0x1860023
#define IQM_CF_TAP_RE3__W                                                   7
#define IQM_CF_TAP_RE3__M                                                   0x7F
#define IQM_CF_TAP_RE3__PRE                                                 0x2
#define IQM_CF_TAP_RE4__A                                                   0x1860024
#define IQM_CF_TAP_RE4__W                                                   7
#define IQM_CF_TAP_RE4__M                                                   0x7F
#define IQM_CF_TAP_RE4__PRE                                                 0x2
#define IQM_CF_TAP_RE5__A                                                   0x1860025
#define IQM_CF_TAP_RE5__W                                                   7
#define IQM_CF_TAP_RE5__M                                                   0x7F
#define IQM_CF_TAP_RE5__PRE                                                 0x2
#define IQM_CF_TAP_RE6__A                                                   0x1860026
#define IQM_CF_TAP_RE6__W                                                   7
#define IQM_CF_TAP_RE6__M                                                   0x7F
#define IQM_CF_TAP_RE6__PRE                                                 0x2
#define IQM_CF_TAP_RE7__A                                                   0x1860027
#define IQM_CF_TAP_RE7__W                                                   9
#define IQM_CF_TAP_RE7__M                                                   0x1FF
#define IQM_CF_TAP_RE7__PRE                                                 0x2
#define IQM_CF_TAP_RE8__A                                                   0x1860028
#define IQM_CF_TAP_RE8__W                                                   9
#define IQM_CF_TAP_RE8__M                                                   0x1FF
#define IQM_CF_TAP_RE8__PRE                                                 0x2
#define IQM_CF_TAP_RE9__A                                                   0x1860029
#define IQM_CF_TAP_RE9__W                                                   9
#define IQM_CF_TAP_RE9__M                                                   0x1FF
#define IQM_CF_TAP_RE9__PRE                                                 0x2
#define IQM_CF_TAP_RE10__A                                                  0x186002A
#define IQM_CF_TAP_RE10__W                                                  9
#define IQM_CF_TAP_RE10__M                                                  0x1FF
#define IQM_CF_TAP_RE10__PRE                                                0x2
#define IQM_CF_TAP_RE11__A                                                  0x186002B
#define IQM_CF_TAP_RE11__W                                                  9
#define IQM_CF_TAP_RE11__M                                                  0x1FF
#define IQM_CF_TAP_RE11__PRE                                                0x2
#define IQM_CF_TAP_RE12__A                                                  0x186002C
#define IQM_CF_TAP_RE12__W                                                  9
#define IQM_CF_TAP_RE12__M                                                  0x1FF
#define IQM_CF_TAP_RE12__PRE                                                0x2
#define IQM_CF_TAP_RE13__A                                                  0x186002D
#define IQM_CF_TAP_RE13__W                                                  9
#define IQM_CF_TAP_RE13__M                                                  0x1FF
#define IQM_CF_TAP_RE13__PRE                                                0x2
#define IQM_CF_TAP_RE14__A                                                  0x186002E
#define IQM_CF_TAP_RE14__W                                                  9
#define IQM_CF_TAP_RE14__M                                                  0x1FF
#define IQM_CF_TAP_RE14__PRE                                                0x2
#define IQM_CF_TAP_RE15__A                                                  0x186002F
#define IQM_CF_TAP_RE15__W                                                  9
#define IQM_CF_TAP_RE15__M                                                  0x1FF
#define IQM_CF_TAP_RE15__PRE                                                0x2
#define IQM_CF_TAP_RE16__A                                                  0x1860030
#define IQM_CF_TAP_RE16__W                                                  9
#define IQM_CF_TAP_RE16__M                                                  0x1FF
#define IQM_CF_TAP_RE16__PRE                                                0x2
#define IQM_CF_TAP_RE17__A                                                  0x1860031
#define IQM_CF_TAP_RE17__W                                                  9
#define IQM_CF_TAP_RE17__M                                                  0x1FF
#define IQM_CF_TAP_RE17__PRE                                                0x2
#define IQM_CF_TAP_RE18__A                                                  0x1860032
#define IQM_CF_TAP_RE18__W                                                  9
#define IQM_CF_TAP_RE18__M                                                  0x1FF
#define IQM_CF_TAP_RE18__PRE                                                0x2
#define IQM_CF_TAP_RE19__A                                                  0x1860033
#define IQM_CF_TAP_RE19__W                                                  9
#define IQM_CF_TAP_RE19__M                                                  0x1FF
#define IQM_CF_TAP_RE19__PRE                                                0x2
#define IQM_CF_TAP_RE20__A                                                  0x1860034
#define IQM_CF_TAP_RE20__W                                                  9
#define IQM_CF_TAP_RE20__M                                                  0x1FF
#define IQM_CF_TAP_RE20__PRE                                                0x2
#define IQM_CF_TAP_RE21__A                                                  0x1860035
#define IQM_CF_TAP_RE21__W                                                  11
#define IQM_CF_TAP_RE21__M                                                  0x7FF
#define IQM_CF_TAP_RE21__PRE                                                0x2
#define IQM_CF_TAP_RE22__A                                                  0x1860036
#define IQM_CF_TAP_RE22__W                                                  11
#define IQM_CF_TAP_RE22__M                                                  0x7FF
#define IQM_CF_TAP_RE22__PRE                                                0x2
#define IQM_CF_TAP_RE23__A                                                  0x1860037
#define IQM_CF_TAP_RE23__W                                                  11
#define IQM_CF_TAP_RE23__M                                                  0x7FF
#define IQM_CF_TAP_RE23__PRE                                                0x2
#define IQM_CF_TAP_RE24__A                                                  0x1860038
#define IQM_CF_TAP_RE24__W                                                  11
#define IQM_CF_TAP_RE24__M                                                  0x7FF
#define IQM_CF_TAP_RE24__PRE                                                0x2
#define IQM_CF_TAP_RE25__A                                                  0x1860039
#define IQM_CF_TAP_RE25__W                                                  11
#define IQM_CF_TAP_RE25__M                                                  0x7FF
#define IQM_CF_TAP_RE25__PRE                                                0x2
#define IQM_CF_TAP_RE26__A                                                  0x186003A
#define IQM_CF_TAP_RE26__W                                                  11
#define IQM_CF_TAP_RE26__M                                                  0x7FF
#define IQM_CF_TAP_RE26__PRE                                                0x2
#define IQM_CF_TAP_RE27__A                                                  0x186003B
#define IQM_CF_TAP_RE27__W                                                  11
#define IQM_CF_TAP_RE27__M                                                  0x7FF
#define IQM_CF_TAP_RE27__PRE                                                0x2
#define IQM_CF_TAP_IM0__A                                                   0x1860040
#define IQM_CF_TAP_IM0__W                                                   7
#define IQM_CF_TAP_IM0__M                                                   0x7F
#define IQM_CF_TAP_IM0__PRE                                                 0x2
#define IQM_CF_TAP_IM1__A                                                   0x1860041
#define IQM_CF_TAP_IM1__W                                                   7
#define IQM_CF_TAP_IM1__M                                                   0x7F
#define IQM_CF_TAP_IM1__PRE                                                 0x2
#define IQM_CF_TAP_IM2__A                                                   0x1860042
#define IQM_CF_TAP_IM2__W                                                   7
#define IQM_CF_TAP_IM2__M                                                   0x7F
#define IQM_CF_TAP_IM2__PRE                                                 0x2
#define IQM_CF_TAP_IM3__A                                                   0x1860043
#define IQM_CF_TAP_IM3__W                                                   7
#define IQM_CF_TAP_IM3__M                                                   0x7F
#define IQM_CF_TAP_IM3__PRE                                                 0x2
#define IQM_CF_TAP_IM4__A                                                   0x1860044
#define IQM_CF_TAP_IM4__W                                                   7
#define IQM_CF_TAP_IM4__M                                                   0x7F
#define IQM_CF_TAP_IM4__PRE                                                 0x2
#define IQM_CF_TAP_IM5__A                                                   0x1860045
#define IQM_CF_TAP_IM5__W                                                   7
#define IQM_CF_TAP_IM5__M                                                   0x7F
#define IQM_CF_TAP_IM5__PRE                                                 0x2
#define IQM_CF_TAP_IM6__A                                                   0x1860046
#define IQM_CF_TAP_IM6__W                                                   7
#define IQM_CF_TAP_IM6__M                                                   0x7F
#define IQM_CF_TAP_IM6__PRE                                                 0x2
#define IQM_CF_TAP_IM7__A                                                   0x1860047
#define IQM_CF_TAP_IM7__W                                                   9
#define IQM_CF_TAP_IM7__M                                                   0x1FF
#define IQM_CF_TAP_IM7__PRE                                                 0x2
#define IQM_CF_TAP_IM8__A                                                   0x1860048
#define IQM_CF_TAP_IM8__W                                                   9
#define IQM_CF_TAP_IM8__M                                                   0x1FF
#define IQM_CF_TAP_IM8__PRE                                                 0x2
#define IQM_CF_TAP_IM9__A                                                   0x1860049
#define IQM_CF_TAP_IM9__W                                                   9
#define IQM_CF_TAP_IM9__M                                                   0x1FF
#define IQM_CF_TAP_IM9__PRE                                                 0x2
#define IQM_CF_TAP_IM10__A                                                  0x186004A
#define IQM_CF_TAP_IM10__W                                                  9
#define IQM_CF_TAP_IM10__M                                                  0x1FF
#define IQM_CF_TAP_IM10__PRE                                                0x2
#define IQM_CF_TAP_IM11__A                                                  0x186004B
#define IQM_CF_TAP_IM11__W                                                  9
#define IQM_CF_TAP_IM11__M                                                  0x1FF
#define IQM_CF_TAP_IM11__PRE                                                0x2
#define IQM_CF_TAP_IM12__A                                                  0x186004C
#define IQM_CF_TAP_IM12__W                                                  9
#define IQM_CF_TAP_IM12__M                                                  0x1FF
#define IQM_CF_TAP_IM12__PRE                                                0x2
#define IQM_CF_TAP_IM13__A                                                  0x186004D
#define IQM_CF_TAP_IM13__W                                                  9
#define IQM_CF_TAP_IM13__M                                                  0x1FF
#define IQM_CF_TAP_IM13__PRE                                                0x2
#define IQM_CF_TAP_IM14__A                                                  0x186004E
#define IQM_CF_TAP_IM14__W                                                  9
#define IQM_CF_TAP_IM14__M                                                  0x1FF
#define IQM_CF_TAP_IM14__PRE                                                0x2
#define IQM_CF_TAP_IM15__A                                                  0x186004F
#define IQM_CF_TAP_IM15__W                                                  9
#define IQM_CF_TAP_IM15__M                                                  0x1FF
#define IQM_CF_TAP_IM15__PRE                                                0x2
#define IQM_CF_TAP_IM16__A                                                  0x1860050
#define IQM_CF_TAP_IM16__W                                                  9
#define IQM_CF_TAP_IM16__M                                                  0x1FF
#define IQM_CF_TAP_IM16__PRE                                                0x2
#define IQM_CF_TAP_IM17__A                                                  0x1860051
#define IQM_CF_TAP_IM17__W                                                  9
#define IQM_CF_TAP_IM17__M                                                  0x1FF
#define IQM_CF_TAP_IM17__PRE                                                0x2
#define IQM_CF_TAP_IM18__A                                                  0x1860052
#define IQM_CF_TAP_IM18__W                                                  9
#define IQM_CF_TAP_IM18__M                                                  0x1FF
#define IQM_CF_TAP_IM18__PRE                                                0x2
#define IQM_CF_TAP_IM19__A                                                  0x1860053
#define IQM_CF_TAP_IM19__W                                                  9
#define IQM_CF_TAP_IM19__M                                                  0x1FF
#define IQM_CF_TAP_IM19__PRE                                                0x2
#define IQM_CF_TAP_IM20__A                                                  0x1860054
#define IQM_CF_TAP_IM20__W                                                  9
#define IQM_CF_TAP_IM20__M                                                  0x1FF
#define IQM_CF_TAP_IM20__PRE                                                0x2
#define IQM_CF_TAP_IM21__A                                                  0x1860055
#define IQM_CF_TAP_IM21__W                                                  11
#define IQM_CF_TAP_IM21__M                                                  0x7FF
#define IQM_CF_TAP_IM21__PRE                                                0x2
#define IQM_CF_TAP_IM22__A                                                  0x1860056
#define IQM_CF_TAP_IM22__W                                                  11
#define IQM_CF_TAP_IM22__M                                                  0x7FF
#define IQM_CF_TAP_IM22__PRE                                                0x2
#define IQM_CF_TAP_IM23__A                                                  0x1860057
#define IQM_CF_TAP_IM23__W                                                  11
#define IQM_CF_TAP_IM23__M                                                  0x7FF
#define IQM_CF_TAP_IM23__PRE                                                0x2
#define IQM_CF_TAP_IM24__A                                                  0x1860058
#define IQM_CF_TAP_IM24__W                                                  11
#define IQM_CF_TAP_IM24__M                                                  0x7FF
#define IQM_CF_TAP_IM24__PRE                                                0x2
#define IQM_CF_TAP_IM25__A                                                  0x1860059
#define IQM_CF_TAP_IM25__W                                                  11
#define IQM_CF_TAP_IM25__M                                                  0x7FF
#define IQM_CF_TAP_IM25__PRE                                                0x2
#define IQM_CF_TAP_IM26__A                                                  0x186005A
#define IQM_CF_TAP_IM26__W                                                  11
#define IQM_CF_TAP_IM26__M                                                  0x7FF
#define IQM_CF_TAP_IM26__PRE                                                0x2
#define IQM_CF_TAP_IM27__A                                                  0x186005B
#define IQM_CF_TAP_IM27__W                                                  11
#define IQM_CF_TAP_IM27__M                                                  0x7FF
#define IQM_CF_TAP_IM27__PRE                                                0x2

#define IQM_AF_COMM_EXEC__A                                                 0x1870000
#define IQM_AF_COMM_EXEC__W                                                 2
#define IQM_AF_COMM_EXEC__M                                                 0x3
#define IQM_AF_COMM_EXEC__PRE                                               0x0
#define   IQM_AF_COMM_EXEC_STOP                                             0x0
#define   IQM_AF_COMM_EXEC_ACTIVE                                           0x1
#define   IQM_AF_COMM_EXEC_HOLD                                             0x2

#define IQM_AF_COMM_MB__A                                                   0x1870002
#define IQM_AF_COMM_MB__W                                                   8
#define IQM_AF_COMM_MB__M                                                   0xFF
#define IQM_AF_COMM_MB__PRE                                                 0x0
#define   IQM_AF_COMM_MB_CTL__B                                             0
#define   IQM_AF_COMM_MB_CTL__W                                             1
#define   IQM_AF_COMM_MB_CTL__M                                             0x1
#define   IQM_AF_COMM_MB_CTL__PRE                                           0x0
#define     IQM_AF_COMM_MB_CTL_CTL_OFF                                      0x0
#define     IQM_AF_COMM_MB_CTL_CTL_ON                                       0x1
#define   IQM_AF_COMM_MB_OBS__B                                             1
#define   IQM_AF_COMM_MB_OBS__W                                             1
#define   IQM_AF_COMM_MB_OBS__M                                             0x2
#define   IQM_AF_COMM_MB_OBS__PRE                                           0x0
#define     IQM_AF_COMM_MB_OBS_OBS_OFF                                      0x0
#define     IQM_AF_COMM_MB_OBS_OBS_ON                                       0x2
#define   IQM_AF_COMM_MB_MUX_CTRL__B                                        2
#define   IQM_AF_COMM_MB_MUX_CTRL__W                                        3
#define   IQM_AF_COMM_MB_MUX_CTRL__M                                        0x1C
#define   IQM_AF_COMM_MB_MUX_CTRL__PRE                                      0x0
#define     IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT                           0x0
#define     IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT                             0x4
#define     IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT                          0x8
#define     IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT                           0xC
#define     IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT                           0x10
#define   IQM_AF_COMM_MB_MUX_OBS__B                                         5
#define   IQM_AF_COMM_MB_MUX_OBS__W                                         3
#define   IQM_AF_COMM_MB_MUX_OBS__M                                         0xE0
#define   IQM_AF_COMM_MB_MUX_OBS__PRE                                       0x0
#define     IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT                            0x0
#define     IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT                              0x20
#define     IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT                           0x40
#define     IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT                            0x60
#define     IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT                            0x80

#define IQM_AF_COMM_INT_REQ__A                                              0x1870003
#define IQM_AF_COMM_INT_REQ__W                                              1
#define IQM_AF_COMM_INT_REQ__M                                              0x1
#define IQM_AF_COMM_INT_REQ__PRE                                            0x0
#define IQM_AF_COMM_INT_STA__A                                              0x1870005
#define IQM_AF_COMM_INT_STA__W                                              2
#define IQM_AF_COMM_INT_STA__M                                              0x3
#define IQM_AF_COMM_INT_STA__PRE                                            0x0
#define   IQM_AF_COMM_INT_STA_CLP_INT_STA__B                                0
#define   IQM_AF_COMM_INT_STA_CLP_INT_STA__W                                1
#define   IQM_AF_COMM_INT_STA_CLP_INT_STA__M                                0x1
#define   IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE                              0x0
#define   IQM_AF_COMM_INT_STA_SNS_INT_STA__B                                1
#define   IQM_AF_COMM_INT_STA_SNS_INT_STA__W                                1
#define   IQM_AF_COMM_INT_STA_SNS_INT_STA__M                                0x2
#define   IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE                              0x0

#define IQM_AF_COMM_INT_MSK__A                                              0x1870006
#define IQM_AF_COMM_INT_MSK__W                                              2
#define IQM_AF_COMM_INT_MSK__M                                              0x3
#define IQM_AF_COMM_INT_MSK__PRE                                            0x0
#define   IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B                                0
#define   IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W                                1
#define   IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M                                0x1
#define   IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE                              0x0
#define   IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B                                1
#define   IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W                                1
#define   IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M                                0x2
#define   IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE                              0x0

#define IQM_AF_COMM_INT_STM__A                                              0x1870007
#define IQM_AF_COMM_INT_STM__W                                              2
#define IQM_AF_COMM_INT_STM__M                                              0x3
#define IQM_AF_COMM_INT_STM__PRE                                            0x0
#define   IQM_AF_COMM_INT_STM_CLP_INT_STA__B                                0
#define   IQM_AF_COMM_INT_STM_CLP_INT_STA__W                                1
#define   IQM_AF_COMM_INT_STM_CLP_INT_STA__M                                0x1
#define   IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE                              0x0
#define   IQM_AF_COMM_INT_STM_SNS_INT_STA__B                                1
#define   IQM_AF_COMM_INT_STM_SNS_INT_STA__W                                1
#define   IQM_AF_COMM_INT_STM_SNS_INT_STA__M                                0x2
#define   IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE                              0x0

#define IQM_AF_FDB_SEL__A                                                   0x1870010
#define IQM_AF_FDB_SEL__W                                                   1
#define IQM_AF_FDB_SEL__M                                                   0x1
#define IQM_AF_FDB_SEL__PRE                                                 0x0

#define IQM_AF_INVEXT__A                                                    0x1870011
#define IQM_AF_INVEXT__W                                                    1
#define IQM_AF_INVEXT__M                                                    0x1
#define IQM_AF_INVEXT__PRE                                                  0x0
#define IQM_AF_CLKNEG__A                                                    0x1870012
#define IQM_AF_CLKNEG__W                                                    2
#define IQM_AF_CLKNEG__M                                                    0x3
#define IQM_AF_CLKNEG__PRE                                                  0x0

#define   IQM_AF_CLKNEG_CLKNEGPEAK__B                                       0
#define   IQM_AF_CLKNEG_CLKNEGPEAK__W                                       1
#define   IQM_AF_CLKNEG_CLKNEGPEAK__M                                       0x1
#define   IQM_AF_CLKNEG_CLKNEGPEAK__PRE                                     0x0
#define     IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS                       0x0
#define     IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG                       0x1

#define   IQM_AF_CLKNEG_CLKNEGDATA__B                                       1
#define   IQM_AF_CLKNEG_CLKNEGDATA__W                                       1
#define   IQM_AF_CLKNEG_CLKNEGDATA__M                                       0x2
#define   IQM_AF_CLKNEG_CLKNEGDATA__PRE                                     0x0
#define     IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS                       0x0
#define     IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG                       0x2

#define IQM_AF_MON_IN_MUX__A                                                0x1870013
#define IQM_AF_MON_IN_MUX__W                                                2
#define IQM_AF_MON_IN_MUX__M                                                0x3
#define IQM_AF_MON_IN_MUX__PRE                                              0x0

#define IQM_AF_MON_IN5__A                                                   0x1870014
#define IQM_AF_MON_IN5__W                                                   10
#define IQM_AF_MON_IN5__M                                                   0x3FF
#define IQM_AF_MON_IN5__PRE                                                 0x0

#define IQM_AF_MON_IN4__A                                                   0x1870015
#define IQM_AF_MON_IN4__W                                                   10
#define IQM_AF_MON_IN4__M                                                   0x3FF
#define IQM_AF_MON_IN4__PRE                                                 0x0

#define IQM_AF_MON_IN3__A                                                   0x1870016
#define IQM_AF_MON_IN3__W                                                   10
#define IQM_AF_MON_IN3__M                                                   0x3FF
#define IQM_AF_MON_IN3__PRE                                                 0x0

#define IQM_AF_MON_IN2__A                                                   0x1870017
#define IQM_AF_MON_IN2__W                                                   10
#define IQM_AF_MON_IN2__M                                                   0x3FF
#define IQM_AF_MON_IN2__PRE                                                 0x0

#define IQM_AF_MON_IN1__A                                                   0x1870018
#define IQM_AF_MON_IN1__W                                                   10
#define IQM_AF_MON_IN1__M                                                   0x3FF
#define IQM_AF_MON_IN1__PRE                                                 0x0

#define IQM_AF_MON_IN0__A                                                   0x1870019
#define IQM_AF_MON_IN0__W                                                   10
#define IQM_AF_MON_IN0__M                                                   0x3FF
#define IQM_AF_MON_IN0__PRE                                                 0x0

#define IQM_AF_MON_IN_VAL__A                                                0x187001A
#define IQM_AF_MON_IN_VAL__W                                                1
#define IQM_AF_MON_IN_VAL__M                                                0x1
#define IQM_AF_MON_IN_VAL__PRE                                              0x0

#define IQM_AF_START_LOCK__A                                                0x187001B
#define IQM_AF_START_LOCK__W                                                1
#define IQM_AF_START_LOCK__M                                                0x1
#define IQM_AF_START_LOCK__PRE                                              0x0

#define IQM_AF_PHASE0__A                                                    0x187001C
#define IQM_AF_PHASE0__W                                                    7
#define IQM_AF_PHASE0__M                                                    0x7F
#define IQM_AF_PHASE0__PRE                                                  0x0

#define IQM_AF_PHASE1__A                                                    0x187001D
#define IQM_AF_PHASE1__W                                                    7
#define IQM_AF_PHASE1__M                                                    0x7F
#define IQM_AF_PHASE1__PRE                                                  0x0

#define IQM_AF_PHASE2__A                                                    0x187001E
#define IQM_AF_PHASE2__W                                                    7
#define IQM_AF_PHASE2__M                                                    0x7F
#define IQM_AF_PHASE2__PRE                                                  0x0

#define IQM_AF_SCU_PHASE__A                                                 0x187001F
#define IQM_AF_SCU_PHASE__W                                                 2
#define IQM_AF_SCU_PHASE__M                                                 0x3
#define IQM_AF_SCU_PHASE__PRE                                               0x0

#define IQM_AF_SYNC_SEL__A                                                  0x1870020
#define IQM_AF_SYNC_SEL__W                                                  2
#define IQM_AF_SYNC_SEL__M                                                  0x3
#define IQM_AF_SYNC_SEL__PRE                                                0x0
#define IQM_AF_ADC_CONF__A                                                  0x1870021
#define IQM_AF_ADC_CONF__W                                                  4
#define IQM_AF_ADC_CONF__M                                                  0xF
#define IQM_AF_ADC_CONF__PRE                                                0x0

#define   IQM_AF_ADC_CONF_ADC_SIGN__B                                       0
#define   IQM_AF_ADC_CONF_ADC_SIGN__W                                       1
#define   IQM_AF_ADC_CONF_ADC_SIGN__M                                       0x1
#define   IQM_AF_ADC_CONF_ADC_SIGN__PRE                                     0x0
#define     IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED                             0x0
#define     IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED                           0x1

#define   IQM_AF_ADC_CONF_BITREVERSE_ADC__B                                 1
#define   IQM_AF_ADC_CONF_BITREVERSE_ADC__W                                 1
#define   IQM_AF_ADC_CONF_BITREVERSE_ADC__M                                 0x2
#define   IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE                               0x0
#define     IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL                       0x0
#define     IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED                  0x2

#define   IQM_AF_ADC_CONF_BITREVERSE_NSSI__B                                2
#define   IQM_AF_ADC_CONF_BITREVERSE_NSSI__W                                1
#define   IQM_AF_ADC_CONF_BITREVERSE_NSSI__M                                0x4
#define   IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE                              0x0
#define     IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL                0x0
#define     IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED           0x4

#define   IQM_AF_ADC_CONF_BITREVERSE_NSSR__B                                3
#define   IQM_AF_ADC_CONF_BITREVERSE_NSSR__W                                1
#define   IQM_AF_ADC_CONF_BITREVERSE_NSSR__M                                0x8
#define   IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE                              0x0
#define     IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL                0x0
#define     IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED           0x8

#define IQM_AF_CLP_CLIP__A                                                  0x1870022
#define IQM_AF_CLP_CLIP__W                                                  16
#define IQM_AF_CLP_CLIP__M                                                  0xFFFF
#define IQM_AF_CLP_CLIP__PRE                                                0x0

#define IQM_AF_CLP_LEN__A                                                   0x1870023
#define IQM_AF_CLP_LEN__W                                                   16
#define IQM_AF_CLP_LEN__M                                                   0xFFFF
#define IQM_AF_CLP_LEN__PRE                                                 0x0
#define   IQM_AF_CLP_LEN_QAM_B_64                                           0x400
#define   IQM_AF_CLP_LEN_QAM_B_256                                          0x400
#define   IQM_AF_CLP_LEN_ATV                                                0x0

#define IQM_AF_CLP_TH__A                                                    0x1870024
#define IQM_AF_CLP_TH__W                                                    9
#define IQM_AF_CLP_TH__M                                                    0x1FF
#define IQM_AF_CLP_TH__PRE                                                  0x0
#define   IQM_AF_CLP_TH_QAM_B_64                                            0x80
#define   IQM_AF_CLP_TH_QAM_B_256                                           0x80
#define   IQM_AF_CLP_TH_ATV                                                 0x1C0

#define IQM_AF_DCF_BYPASS__A                                                0x1870025
#define IQM_AF_DCF_BYPASS__W                                                1
#define IQM_AF_DCF_BYPASS__M                                                0x1
#define IQM_AF_DCF_BYPASS__PRE                                              0x0
#define   IQM_AF_DCF_BYPASS_ACTIVE                                          0x0
#define   IQM_AF_DCF_BYPASS_BYPASS                                          0x1

#define IQM_AF_SNS_LEN__A                                                   0x1870026
#define IQM_AF_SNS_LEN__W                                                   16
#define IQM_AF_SNS_LEN__M                                                   0xFFFF
#define IQM_AF_SNS_LEN__PRE                                                 0x0
#define   IQM_AF_SNS_LEN_QAM_B_64                                           0x400
#define   IQM_AF_SNS_LEN_QAM_B_256                                          0x400
#define   IQM_AF_SNS_LEN_ATV                                                0x0

#define IQM_AF_SNS_SENSE__A                                                 0x1870027
#define IQM_AF_SNS_SENSE__W                                                 16
#define IQM_AF_SNS_SENSE__M                                                 0xFFFF
#define IQM_AF_SNS_SENSE__PRE                                               0x0

#define IQM_AF_AGC_IF__A                                                    0x1870028
#define IQM_AF_AGC_IF__W                                                    15
#define IQM_AF_AGC_IF__M                                                    0x7FFF
#define IQM_AF_AGC_IF__PRE                                                  0x0

#define IQM_AF_AGC_RF__A                                                    0x1870029
#define IQM_AF_AGC_RF__W                                                    15
#define IQM_AF_AGC_RF__M                                                    0x7FFF
#define IQM_AF_AGC_RF__PRE                                                  0x0

#define IQM_AF_PGA_GAIN__A                                                  0x187002A
#define IQM_AF_PGA_GAIN__W                                                  4
#define IQM_AF_PGA_GAIN__M                                                  0xF
#define IQM_AF_PGA_GAIN__PRE                                                0x0

#define IQM_AF_PDREF__A                                                     0x187002B
#define IQM_AF_PDREF__W                                                     5
#define IQM_AF_PDREF__M                                                     0x1F
#define IQM_AF_PDREF__PRE                                                   0x0
#define   IQM_AF_PDREF_QAM_B_64                                             0xF
#define   IQM_AF_PDREF_QAM_B_256                                            0xF
#define   IQM_AF_PDREF_ATV                                                  0xF

#define IQM_AF_STDBY__A                                                     0x187002C
#define IQM_AF_STDBY__W                                                     6
#define IQM_AF_STDBY__M                                                     0x3F
#define IQM_AF_STDBY__PRE                                                   0x0

#define   IQM_AF_STDBY_STDBY_BIAS__B                                        0
#define   IQM_AF_STDBY_STDBY_BIAS__W                                        1
#define   IQM_AF_STDBY_STDBY_BIAS__M                                        0x1
#define   IQM_AF_STDBY_STDBY_BIAS__PRE                                      0x0
#define     IQM_AF_STDBY_STDBY_BIAS_ACTIVE                                  0x0
#define     IQM_AF_STDBY_STDBY_BIAS_STANDBY                                 0x1

#define   IQM_AF_STDBY_STDBY_ADC__B                                         1
#define   IQM_AF_STDBY_STDBY_ADC__W                                         1
#define   IQM_AF_STDBY_STDBY_ADC__M                                         0x2
#define   IQM_AF_STDBY_STDBY_ADC__PRE                                       0x0
#define     IQM_AF_STDBY_STDBY_ADC_A1_ACTIVE                                0x0
#define     IQM_AF_STDBY_STDBY_ADC_A1_STANDBY                               0x2
#define     IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE                                0x2
#define     IQM_AF_STDBY_STDBY_ADC_A2_STANDBY                               0x0

#define   IQM_AF_STDBY_STDBY_AMP__B                                         2
#define   IQM_AF_STDBY_STDBY_AMP__W                                         1
#define   IQM_AF_STDBY_STDBY_AMP__M                                         0x4
#define   IQM_AF_STDBY_STDBY_AMP__PRE                                       0x0
#define     IQM_AF_STDBY_STDBY_AMP_A1_ACTIVE                                0x0
#define     IQM_AF_STDBY_STDBY_AMP_A1_STANDBY                               0x4
#define     IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE                                0x4
#define     IQM_AF_STDBY_STDBY_AMP_A2_STANDBY                               0x0

#define   IQM_AF_STDBY_STDBY_PD__B                                          3
#define   IQM_AF_STDBY_STDBY_PD__W                                          1
#define   IQM_AF_STDBY_STDBY_PD__M                                          0x8
#define   IQM_AF_STDBY_STDBY_PD__PRE                                        0x0
#define     IQM_AF_STDBY_STDBY_PD_A1_ACTIVE                                 0x0
#define     IQM_AF_STDBY_STDBY_PD_A1_STANDBY                                0x8
#define     IQM_AF_STDBY_STDBY_PD_A2_ACTIVE                                 0x8
#define     IQM_AF_STDBY_STDBY_PD_A2_STANDBY                                0x0

#define   IQM_AF_STDBY_STDBY_TAGC_IF__B                                     4
#define   IQM_AF_STDBY_STDBY_TAGC_IF__W                                     1
#define   IQM_AF_STDBY_STDBY_TAGC_IF__M                                     0x10
#define   IQM_AF_STDBY_STDBY_TAGC_IF__PRE                                   0x0
#define     IQM_AF_STDBY_STDBY_TAGC_IF_A1_ACTIVE                            0x0
#define     IQM_AF_STDBY_STDBY_TAGC_IF_A1_STANDBY                           0x10
#define     IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE                            0x10
#define     IQM_AF_STDBY_STDBY_TAGC_IF_A2_STANDBY                           0x0

#define   IQM_AF_STDBY_STDBY_TAGC_RF__B                                     5
#define   IQM_AF_STDBY_STDBY_TAGC_RF__W                                     1
#define   IQM_AF_STDBY_STDBY_TAGC_RF__M                                     0x20
#define   IQM_AF_STDBY_STDBY_TAGC_RF__PRE                                   0x0
#define     IQM_AF_STDBY_STDBY_TAGC_RF_A1_ACTIVE                            0x0
#define     IQM_AF_STDBY_STDBY_TAGC_RF_A1_STANDBY                           0x20
#define     IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE                            0x20
#define     IQM_AF_STDBY_STDBY_TAGC_RF_A2_STANDBY                           0x0

#define IQM_AF_AMUX__A                                                      0x187002D
#define IQM_AF_AMUX__W                                                      2
#define IQM_AF_AMUX__M                                                      0x3
#define IQM_AF_AMUX__PRE                                                    0x0

#define IQM_AF_TST_AFEMAIN__A                                               0x187002E
#define IQM_AF_TST_AFEMAIN__W                                               8
#define IQM_AF_TST_AFEMAIN__M                                               0xFF
#define IQM_AF_TST_AFEMAIN__PRE                                             0x0

#define IQM_RT_RAM__A                                                       0x1880000

#define   IQM_RT_RAM_DLY__B                                                 0
#define   IQM_RT_RAM_DLY__W                                                 13
#define   IQM_RT_RAM_DLY__M                                                 0x1FFF
#define   IQM_RT_RAM_DLY__PRE                                               0x0

#define ORX_COMM_EXEC__A                                                    0x2000000
#define ORX_COMM_EXEC__W                                                    2
#define ORX_COMM_EXEC__M                                                    0x3
#define ORX_COMM_EXEC__PRE                                                  0x0
#define   ORX_COMM_EXEC_STOP                                                0x0
#define   ORX_COMM_EXEC_ACTIVE                                              0x1
#define   ORX_COMM_EXEC_HOLD                                                0x2

#define ORX_COMM_STATE__A                                                   0x2000001
#define ORX_COMM_STATE__W                                                   16
#define ORX_COMM_STATE__M                                                   0xFFFF
#define ORX_COMM_STATE__PRE                                                 0x0
#define ORX_COMM_MB__A                                                      0x2000002
#define ORX_COMM_MB__W                                                      16
#define ORX_COMM_MB__M                                                      0xFFFF
#define ORX_COMM_MB__PRE                                                    0x0
#define ORX_COMM_INT_REQ__A                                                 0x2000003
#define ORX_COMM_INT_REQ__W                                                 16
#define ORX_COMM_INT_REQ__M                                                 0xFFFF
#define ORX_COMM_INT_REQ__PRE                                               0x0
#define   ORX_COMM_INT_REQ_EQU_REQ__B                                       0
#define   ORX_COMM_INT_REQ_EQU_REQ__W                                       1
#define   ORX_COMM_INT_REQ_EQU_REQ__M                                       0x1
#define   ORX_COMM_INT_REQ_EQU_REQ__PRE                                     0x0
#define   ORX_COMM_INT_REQ_DDC_REQ__B                                       1
#define   ORX_COMM_INT_REQ_DDC_REQ__W                                       1
#define   ORX_COMM_INT_REQ_DDC_REQ__M                                       0x2
#define   ORX_COMM_INT_REQ_DDC_REQ__PRE                                     0x0
#define   ORX_COMM_INT_REQ_FWP_REQ__B                                       2
#define   ORX_COMM_INT_REQ_FWP_REQ__W                                       1
#define   ORX_COMM_INT_REQ_FWP_REQ__M                                       0x4
#define   ORX_COMM_INT_REQ_FWP_REQ__PRE                                     0x0
#define   ORX_COMM_INT_REQ_CON_REQ__B                                       3
#define   ORX_COMM_INT_REQ_CON_REQ__W                                       1
#define   ORX_COMM_INT_REQ_CON_REQ__M                                       0x8
#define   ORX_COMM_INT_REQ_CON_REQ__PRE                                     0x0
#define   ORX_COMM_INT_REQ_NSU_REQ__B                                       4
#define   ORX_COMM_INT_REQ_NSU_REQ__W                                       1
#define   ORX_COMM_INT_REQ_NSU_REQ__M                                       0x10
#define   ORX_COMM_INT_REQ_NSU_REQ__PRE                                     0x0

#define ORX_COMM_INT_STA__A                                                 0x2000005
#define ORX_COMM_INT_STA__W                                                 16
#define ORX_COMM_INT_STA__M                                                 0xFFFF
#define ORX_COMM_INT_STA__PRE                                               0x0
#define ORX_COMM_INT_MSK__A                                                 0x2000006
#define ORX_COMM_INT_MSK__W                                                 16
#define ORX_COMM_INT_MSK__M                                                 0xFFFF
#define ORX_COMM_INT_MSK__PRE                                               0x0
#define ORX_COMM_INT_STM__A                                                 0x2000007
#define ORX_COMM_INT_STM__W                                                 16
#define ORX_COMM_INT_STM__M                                                 0xFFFF
#define ORX_COMM_INT_STM__PRE                                               0x0

#define ORX_TOP_COMM_EXEC__A                                                0x2010000
#define ORX_TOP_COMM_EXEC__W                                                2
#define ORX_TOP_COMM_EXEC__M                                                0x3
#define ORX_TOP_COMM_EXEC__PRE                                              0x0
#define   ORX_TOP_COMM_EXEC_STOP                                            0x0
#define   ORX_TOP_COMM_EXEC_ACTIVE                                          0x1
#define   ORX_TOP_COMM_EXEC_HOLD                                            0x2

#define ORX_TOP_COMM_KEY__A                                                 0x201000F
#define ORX_TOP_COMM_KEY__W                                                 16
#define ORX_TOP_COMM_KEY__M                                                 0xFFFF
#define ORX_TOP_COMM_KEY__PRE                                               0x0
#define   ORX_TOP_COMM_KEY_KEY                                              0xFABA

#define ORX_TOP_MDE_W__A                                                    0x2010010
#define ORX_TOP_MDE_W__W                                                    2
#define ORX_TOP_MDE_W__M                                                    0x3
#define ORX_TOP_MDE_W__PRE                                                  0x2
#define   ORX_TOP_MDE_W_RATE_1544KBPS                                       0x0
#define   ORX_TOP_MDE_W_RATE_3088KBPS                                       0x1
#define   ORX_TOP_MDE_W_RATE_2048KBPS_SQRT                                  0x2
#define   ORX_TOP_MDE_W_RATE_2048KBPS_RO                                    0x3

#define ORX_TOP_AIF_CTRL_W__A                                               0x2010011
#define ORX_TOP_AIF_CTRL_W__W                                               3
#define ORX_TOP_AIF_CTRL_W__M                                               0x7
#define ORX_TOP_AIF_CTRL_W__PRE                                             0x0
#define   ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__B                                0
#define   ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__W                                1
#define   ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__M                                0x1
#define   ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__PRE                              0x0
#define     ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_POS_CLK_EDGE       0x0
#define     ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_NEG_CLK_EDGE       0x1
#define   ORX_TOP_AIF_CTRL_W_BIT_REVERSE__B                                 1
#define   ORX_TOP_AIF_CTRL_W_BIT_REVERSE__W                                 1
#define   ORX_TOP_AIF_CTRL_W_BIT_REVERSE__M                                 0x2
#define   ORX_TOP_AIF_CTRL_W_BIT_REVERSE__PRE                               0x0
#define     ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REGULAR_BIT_ORDER_ADC            0x0
#define     ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REVERSAL_BIT_ORDER_ADC           0x2
#define   ORX_TOP_AIF_CTRL_W_INV_MSB__B                                     2
#define   ORX_TOP_AIF_CTRL_W_INV_MSB__W                                     1
#define   ORX_TOP_AIF_CTRL_W_INV_MSB__M                                     0x4
#define   ORX_TOP_AIF_CTRL_W_INV_MSB__PRE                                   0x0
#define     ORX_TOP_AIF_CTRL_W_INV_MSB_NO_MSB_INVERSION_ADC                 0x0
#define     ORX_TOP_AIF_CTRL_W_INV_MSB_MSB_INVERSION_ADC                    0x4

#define ORX_FWP_COMM_EXEC__A                                                0x2020000
#define ORX_FWP_COMM_EXEC__W                                                2
#define ORX_FWP_COMM_EXEC__M                                                0x3
#define ORX_FWP_COMM_EXEC__PRE                                              0x0
#define   ORX_FWP_COMM_EXEC_STOP                                            0x0
#define   ORX_FWP_COMM_EXEC_ACTIVE                                          0x1
#define   ORX_FWP_COMM_EXEC_HOLD                                            0x2

#define ORX_FWP_COMM_MB__A                                                  0x2020002
#define ORX_FWP_COMM_MB__W                                                  8
#define ORX_FWP_COMM_MB__M                                                  0xFF
#define ORX_FWP_COMM_MB__PRE                                                0x0
#define   ORX_FWP_COMM_MB_CTL__B                                            0
#define   ORX_FWP_COMM_MB_CTL__W                                            1
#define   ORX_FWP_COMM_MB_CTL__M                                            0x1
#define   ORX_FWP_COMM_MB_CTL__PRE                                          0x0
#define     ORX_FWP_COMM_MB_CTL_OFF                                         0x0
#define     ORX_FWP_COMM_MB_CTL_ON                                          0x1
#define   ORX_FWP_COMM_MB_OBS__B                                            1
#define   ORX_FWP_COMM_MB_OBS__W                                            1
#define   ORX_FWP_COMM_MB_OBS__M                                            0x2
#define   ORX_FWP_COMM_MB_OBS__PRE                                          0x0
#define     ORX_FWP_COMM_MB_OBS_OFF                                         0x0
#define     ORX_FWP_COMM_MB_OBS_ON                                          0x2

#define   ORX_FWP_COMM_MB_CTL_MUX__B                                        2
#define   ORX_FWP_COMM_MB_CTL_MUX__W                                        3
#define   ORX_FWP_COMM_MB_CTL_MUX__M                                        0x1C
#define   ORX_FWP_COMM_MB_CTL_MUX__PRE                                      0x0

#define   ORX_FWP_COMM_MB_OBS_MUX__B                                        5
#define   ORX_FWP_COMM_MB_OBS_MUX__W                                        3
#define   ORX_FWP_COMM_MB_OBS_MUX__M                                        0xE0
#define   ORX_FWP_COMM_MB_OBS_MUX__PRE                                      0x0

#define ORX_FWP_AAG_LEN_W__A                                                0x2020010
#define ORX_FWP_AAG_LEN_W__W                                                16
#define ORX_FWP_AAG_LEN_W__M                                                0xFFFF
#define ORX_FWP_AAG_LEN_W__PRE                                              0x800

#define ORX_FWP_AAG_THR_W__A                                                0x2020011
#define ORX_FWP_AAG_THR_W__W                                                8
#define ORX_FWP_AAG_THR_W__M                                                0xFF
#define ORX_FWP_AAG_THR_W__PRE                                              0x50

#define ORX_FWP_AAG_THR_CNT_R__A                                            0x2020012
#define ORX_FWP_AAG_THR_CNT_R__W                                            16
#define ORX_FWP_AAG_THR_CNT_R__M                                            0xFFFF
#define ORX_FWP_AAG_THR_CNT_R__PRE                                          0x0

#define ORX_FWP_AAG_SNS_CNT_R__A                                            0x2020013
#define ORX_FWP_AAG_SNS_CNT_R__W                                            16
#define ORX_FWP_AAG_SNS_CNT_R__M                                            0xFFFF
#define ORX_FWP_AAG_SNS_CNT_R__PRE                                          0x0

#define ORX_FWP_PFI_A_W__A                                                  0x2020014
#define ORX_FWP_PFI_A_W__W                                                  8
#define ORX_FWP_PFI_A_W__M                                                  0xFF
#define ORX_FWP_PFI_A_W__PRE                                                0xB0
#define   ORX_FWP_PFI_A_W_RATE_2048KBPS                                     0xB0
#define   ORX_FWP_PFI_A_W_RATE_1544KBPS                                     0xA4
#define   ORX_FWP_PFI_A_W_RATE_3088KBPS                                     0xC0

#define ORX_FWP_PFI_B_W__A                                                  0x2020015
#define ORX_FWP_PFI_B_W__W                                                  8
#define ORX_FWP_PFI_B_W__M                                                  0xFF
#define ORX_FWP_PFI_B_W__PRE                                                0x9E
#define   ORX_FWP_PFI_B_W_RATE_2048KBPS                                     0x9E
#define   ORX_FWP_PFI_B_W_RATE_1544KBPS                                     0x94
#define   ORX_FWP_PFI_B_W_RATE_3088KBPS                                     0xB0

#define ORX_FWP_PFI_C_W__A                                                  0x2020016
#define ORX_FWP_PFI_C_W__W                                                  8
#define ORX_FWP_PFI_C_W__M                                                  0xFF
#define ORX_FWP_PFI_C_W__PRE                                                0x5C
#define   ORX_FWP_PFI_C_W_RATE_2048KBPS                                     0x5C
#define   ORX_FWP_PFI_C_W_RATE_1544KBPS                                     0x64
#define   ORX_FWP_PFI_C_W_RATE_3088KBPS                                     0x50

#define ORX_FWP_KR1_AMP_R__A                                                0x2020017
#define ORX_FWP_KR1_AMP_R__W                                                9
#define ORX_FWP_KR1_AMP_R__M                                                0x1FF
#define ORX_FWP_KR1_AMP_R__PRE                                              0x0

#define ORX_FWP_KR1_LDT_W__A                                                0x2020018
#define ORX_FWP_KR1_LDT_W__W                                                3
#define ORX_FWP_KR1_LDT_W__M                                                0x7
#define ORX_FWP_KR1_LDT_W__PRE                                              0x2
#define ORX_FWP_SRC_DGN_W__A                                                0x2020019
#define ORX_FWP_SRC_DGN_W__W                                                16
#define ORX_FWP_SRC_DGN_W__M                                                0xFFFF
#define ORX_FWP_SRC_DGN_W__PRE                                              0x1FF

#define   ORX_FWP_SRC_DGN_W_MANT__B                                         0
#define   ORX_FWP_SRC_DGN_W_MANT__W                                         9
#define   ORX_FWP_SRC_DGN_W_MANT__M                                         0x1FF
#define   ORX_FWP_SRC_DGN_W_MANT__PRE                                       0x1FF

#define   ORX_FWP_SRC_DGN_W_EXP__B                                          12
#define   ORX_FWP_SRC_DGN_W_EXP__W                                          4
#define   ORX_FWP_SRC_DGN_W_EXP__M                                          0xF000
#define   ORX_FWP_SRC_DGN_W_EXP__PRE                                        0x0

#define ORX_FWP_NYQ_ADR_W__A                                                0x202001A
#define ORX_FWP_NYQ_ADR_W__W                                                5
#define ORX_FWP_NYQ_ADR_W__M                                                0x1F
#define ORX_FWP_NYQ_ADR_W__PRE                                              0x1F

#define ORX_FWP_NYQ_COF_RW__A                                               0x202001B
#define ORX_FWP_NYQ_COF_RW__W                                               10
#define ORX_FWP_NYQ_COF_RW__M                                               0x3FF
#define ORX_FWP_NYQ_COF_RW__PRE                                             0x0

#define ORX_FWP_IQM_FRQ_W__A                                                0x202001C
#define ORX_FWP_IQM_FRQ_W__W                                                16
#define ORX_FWP_IQM_FRQ_W__M                                                0xFFFF
#define ORX_FWP_IQM_FRQ_W__PRE                                              0x4301

#define ORX_EQU_COMM_EXEC__A                                                0x2030000
#define ORX_EQU_COMM_EXEC__W                                                2
#define ORX_EQU_COMM_EXEC__M                                                0x3
#define ORX_EQU_COMM_EXEC__PRE                                              0x0
#define   ORX_EQU_COMM_EXEC_STOP                                            0x0
#define   ORX_EQU_COMM_EXEC_ACTIVE                                          0x1
#define   ORX_EQU_COMM_EXEC_HOLD                                            0x2

#define ORX_EQU_COMM_MB__A                                                  0x2030002
#define ORX_EQU_COMM_MB__W                                                  8
#define ORX_EQU_COMM_MB__M                                                  0xFF
#define ORX_EQU_COMM_MB__PRE                                                0x0
#define   ORX_EQU_COMM_MB_CTL__B                                            0
#define   ORX_EQU_COMM_MB_CTL__W                                            1
#define   ORX_EQU_COMM_MB_CTL__M                                            0x1
#define   ORX_EQU_COMM_MB_CTL__PRE                                          0x0
#define     ORX_EQU_COMM_MB_CTL_OFF                                         0x0
#define     ORX_EQU_COMM_MB_CTL_ON                                          0x1
#define   ORX_EQU_COMM_MB_OBS__B                                            1
#define   ORX_EQU_COMM_MB_OBS__W                                            1
#define   ORX_EQU_COMM_MB_OBS__M                                            0x2
#define   ORX_EQU_COMM_MB_OBS__PRE                                          0x0
#define     ORX_EQU_COMM_MB_OBS_OFF                                         0x0
#define     ORX_EQU_COMM_MB_OBS_ON                                          0x2

#define   ORX_EQU_COMM_MB_CTL_MUX__B                                        2
#define   ORX_EQU_COMM_MB_CTL_MUX__W                                        3
#define   ORX_EQU_COMM_MB_CTL_MUX__M                                        0x1C
#define   ORX_EQU_COMM_MB_CTL_MUX__PRE                                      0x0

#define   ORX_EQU_COMM_MB_OBS_MUX__B                                        5
#define   ORX_EQU_COMM_MB_OBS_MUX__W                                        3
#define   ORX_EQU_COMM_MB_OBS_MUX__M                                        0xE0
#define   ORX_EQU_COMM_MB_OBS_MUX__PRE                                      0x0

#define ORX_EQU_COMM_INT_REQ__A                                             0x2030003
#define ORX_EQU_COMM_INT_REQ__W                                             1
#define ORX_EQU_COMM_INT_REQ__M                                             0x1
#define ORX_EQU_COMM_INT_REQ__PRE                                           0x0
#define ORX_EQU_COMM_INT_STA__A                                             0x2030005
#define ORX_EQU_COMM_INT_STA__W                                             2
#define ORX_EQU_COMM_INT_STA__M                                             0x3
#define ORX_EQU_COMM_INT_STA__PRE                                           0x0

#define   ORX_EQU_COMM_INT_STA_FFF_READ__B                                  0
#define   ORX_EQU_COMM_INT_STA_FFF_READ__W                                  1
#define   ORX_EQU_COMM_INT_STA_FFF_READ__M                                  0x1
#define   ORX_EQU_COMM_INT_STA_FFF_READ__PRE                                0x0

#define   ORX_EQU_COMM_INT_STA_FBF_READ__B                                  1
#define   ORX_EQU_COMM_INT_STA_FBF_READ__W                                  1
#define   ORX_EQU_COMM_INT_STA_FBF_READ__M                                  0x2
#define   ORX_EQU_COMM_INT_STA_FBF_READ__PRE                                0x0

#define ORX_EQU_COMM_INT_MSK__A                                             0x2030006
#define ORX_EQU_COMM_INT_MSK__W                                             2
#define ORX_EQU_COMM_INT_MSK__M                                             0x3
#define ORX_EQU_COMM_INT_MSK__PRE                                           0x0
#define   ORX_EQU_COMM_INT_MSK_FFF_READ__B                                  0
#define   ORX_EQU_COMM_INT_MSK_FFF_READ__W                                  1
#define   ORX_EQU_COMM_INT_MSK_FFF_READ__M                                  0x1
#define   ORX_EQU_COMM_INT_MSK_FFF_READ__PRE                                0x0
#define   ORX_EQU_COMM_INT_MSK_FBF_READ__B                                  1
#define   ORX_EQU_COMM_INT_MSK_FBF_READ__W                                  1
#define   ORX_EQU_COMM_INT_MSK_FBF_READ__M                                  0x2
#define   ORX_EQU_COMM_INT_MSK_FBF_READ__PRE                                0x0

#define ORX_EQU_COMM_INT_STM__A                                             0x2030007
#define ORX_EQU_COMM_INT_STM__W                                             2
#define ORX_EQU_COMM_INT_STM__M                                             0x3
#define ORX_EQU_COMM_INT_STM__PRE                                           0x0
#define   ORX_EQU_COMM_INT_STM_FFF_READ__B                                  0
#define   ORX_EQU_COMM_INT_STM_FFF_READ__W                                  1
#define   ORX_EQU_COMM_INT_STM_FFF_READ__M                                  0x1
#define   ORX_EQU_COMM_INT_STM_FFF_READ__PRE                                0x0
#define   ORX_EQU_COMM_INT_STM_FBF_READ__B                                  1
#define   ORX_EQU_COMM_INT_STM_FBF_READ__W                                  1
#define   ORX_EQU_COMM_INT_STM_FBF_READ__M                                  0x2
#define   ORX_EQU_COMM_INT_STM_FBF_READ__PRE                                0x0

#define ORX_EQU_FFF_SCL_W__A                                                0x2030010
#define ORX_EQU_FFF_SCL_W__W                                                1
#define ORX_EQU_FFF_SCL_W__M                                                0x1
#define ORX_EQU_FFF_SCL_W__PRE                                              0x0
#define   ORX_EQU_FFF_SCL_W_SCALE_GAIN_1                                    0x0
#define   ORX_EQU_FFF_SCL_W_SCALE_GAIN_2                                    0x1

#define ORX_EQU_FFF_UPD_W__A                                                0x2030011
#define ORX_EQU_FFF_UPD_W__W                                                1
#define ORX_EQU_FFF_UPD_W__M                                                0x1
#define ORX_EQU_FFF_UPD_W__PRE                                              0x0
#define   ORX_EQU_FFF_UPD_W_NO_UPDATE                                       0x0
#define   ORX_EQU_FFF_UPD_W_LMS_UPDATE                                      0x1

#define ORX_EQU_FFF_STP_W__A                                                0x2030012
#define ORX_EQU_FFF_STP_W__W                                                3
#define ORX_EQU_FFF_STP_W__M                                                0x7
#define ORX_EQU_FFF_STP_W__PRE                                              0x2

#define ORX_EQU_FFF_LEA_W__A                                                0x2030013
#define ORX_EQU_FFF_LEA_W__W                                                4
#define ORX_EQU_FFF_LEA_W__M                                                0xF
#define ORX_EQU_FFF_LEA_W__PRE                                              0x4

#define ORX_EQU_FFF_RWT_W__A                                                0x2030014
#define ORX_EQU_FFF_RWT_W__W                                                2
#define ORX_EQU_FFF_RWT_W__M                                                0x3
#define ORX_EQU_FFF_RWT_W__PRE                                              0x0

#define ORX_EQU_FFF_C0RE_RW__A                                              0x2030015
#define ORX_EQU_FFF_C0RE_RW__W                                              12
#define ORX_EQU_FFF_C0RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C0RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C0IM_RW__A                                              0x2030016
#define ORX_EQU_FFF_C0IM_RW__W                                              12
#define ORX_EQU_FFF_C0IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C0IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C1RE_RW__A                                              0x2030017
#define ORX_EQU_FFF_C1RE_RW__W                                              12
#define ORX_EQU_FFF_C1RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C1RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C1IM_RW__A                                              0x2030018
#define ORX_EQU_FFF_C1IM_RW__W                                              12
#define ORX_EQU_FFF_C1IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C1IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C2RE_RW__A                                              0x2030019
#define ORX_EQU_FFF_C2RE_RW__W                                              12
#define ORX_EQU_FFF_C2RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C2RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C2IM_RW__A                                              0x203001A
#define ORX_EQU_FFF_C2IM_RW__W                                              12
#define ORX_EQU_FFF_C2IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C2IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C3RE_RW__A                                              0x203001B
#define ORX_EQU_FFF_C3RE_RW__W                                              12
#define ORX_EQU_FFF_C3RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C3RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C3IM_RW__A                                              0x203001C
#define ORX_EQU_FFF_C3IM_RW__W                                              12
#define ORX_EQU_FFF_C3IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C3IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C4RE_RW__A                                              0x203001D
#define ORX_EQU_FFF_C4RE_RW__W                                              12
#define ORX_EQU_FFF_C4RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C4RE_RW__PRE                                            0x400

#define ORX_EQU_FFF_C4IM_RW__A                                              0x203001E
#define ORX_EQU_FFF_C4IM_RW__W                                              12
#define ORX_EQU_FFF_C4IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C4IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C5RE_RW__A                                              0x203001F
#define ORX_EQU_FFF_C5RE_RW__W                                              12
#define ORX_EQU_FFF_C5RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C5RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C5IM_RW__A                                              0x2030020
#define ORX_EQU_FFF_C5IM_RW__W                                              12
#define ORX_EQU_FFF_C5IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C5IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C6RE_RW__A                                              0x2030021
#define ORX_EQU_FFF_C6RE_RW__W                                              12
#define ORX_EQU_FFF_C6RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C6RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C6IM_RW__A                                              0x2030022
#define ORX_EQU_FFF_C6IM_RW__W                                              12
#define ORX_EQU_FFF_C6IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C6IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C7RE_RW__A                                              0x2030023
#define ORX_EQU_FFF_C7RE_RW__W                                              12
#define ORX_EQU_FFF_C7RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C7RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C7IM_RW__A                                              0x2030024
#define ORX_EQU_FFF_C7IM_RW__W                                              12
#define ORX_EQU_FFF_C7IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C7IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C8RE_RW__A                                              0x2030025
#define ORX_EQU_FFF_C8RE_RW__W                                              12
#define ORX_EQU_FFF_C8RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C8RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C8IM_RW__A                                              0x2030026
#define ORX_EQU_FFF_C8IM_RW__W                                              12
#define ORX_EQU_FFF_C8IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C8IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C9RE_RW__A                                              0x2030027
#define ORX_EQU_FFF_C9RE_RW__W                                              12
#define ORX_EQU_FFF_C9RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C9RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C9IM_RW__A                                              0x2030028
#define ORX_EQU_FFF_C9IM_RW__W                                              12
#define ORX_EQU_FFF_C9IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C9IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C10RE_RW__A                                             0x2030029
#define ORX_EQU_FFF_C10RE_RW__W                                             12
#define ORX_EQU_FFF_C10RE_RW__M                                             0xFFF
#define ORX_EQU_FFF_C10RE_RW__PRE                                           0x0

#define ORX_EQU_FFF_C10IM_RW__A                                             0x203002A
#define ORX_EQU_FFF_C10IM_RW__W                                             12
#define ORX_EQU_FFF_C10IM_RW__M                                             0xFFF
#define ORX_EQU_FFF_C10IM_RW__PRE                                           0x0

#define ORX_EQU_MXB_SEL_W__A                                                0x203002B
#define ORX_EQU_MXB_SEL_W__W                                                1
#define ORX_EQU_MXB_SEL_W__M                                                0x1
#define ORX_EQU_MXB_SEL_W__PRE                                              0x0
#define   ORX_EQU_MXB_SEL_W_UNDECIDED_SYMBOLS                               0x0
#define   ORX_EQU_MXB_SEL_W_DECIDED_SYMBOLS                                 0x1

#define ORX_EQU_FBF_UPD_W__A                                                0x203002C
#define ORX_EQU_FBF_UPD_W__W                                                1
#define ORX_EQU_FBF_UPD_W__M                                                0x1
#define ORX_EQU_FBF_UPD_W__PRE                                              0x0
#define   ORX_EQU_FBF_UPD_W_NO_UPDATE                                       0x0
#define   ORX_EQU_FBF_UPD_W_LMS_UPDATE                                      0x1

#define ORX_EQU_FBF_STP_W__A                                                0x203002D
#define ORX_EQU_FBF_STP_W__W                                                3
#define ORX_EQU_FBF_STP_W__M                                                0x7
#define ORX_EQU_FBF_STP_W__PRE                                              0x2

#define ORX_EQU_FBF_LEA_W__A                                                0x203002E
#define ORX_EQU_FBF_LEA_W__W                                                4
#define ORX_EQU_FBF_LEA_W__M                                                0xF
#define ORX_EQU_FBF_LEA_W__PRE                                              0x4

#define ORX_EQU_FBF_RWT_W__A                                                0x203002F
#define ORX_EQU_FBF_RWT_W__W                                                2
#define ORX_EQU_FBF_RWT_W__M                                                0x3
#define ORX_EQU_FBF_RWT_W__PRE                                              0x0

#define ORX_EQU_FBF_C0RE_RW__A                                              0x2030030
#define ORX_EQU_FBF_C0RE_RW__W                                              12
#define ORX_EQU_FBF_C0RE_RW__M                                              0xFFF
#define ORX_EQU_FBF_C0RE_RW__PRE                                            0x0

#define ORX_EQU_FBF_C0IM_RW__A                                              0x2030031
#define ORX_EQU_FBF_C0IM_RW__W                                              12
#define ORX_EQU_FBF_C0IM_RW__M                                              0xFFF
#define ORX_EQU_FBF_C0IM_RW__PRE                                            0x0

#define ORX_EQU_FBF_C1RE_RW__A                                              0x2030032
#define ORX_EQU_FBF_C1RE_RW__W                                              12
#define ORX_EQU_FBF_C1RE_RW__M                                              0xFFF
#define ORX_EQU_FBF_C1RE_RW__PRE                                            0x0

#define ORX_EQU_FBF_C1IM_RW__A                                              0x2030033
#define ORX_EQU_FBF_C1IM_RW__W                                              12
#define ORX_EQU_FBF_C1IM_RW__M                                              0xFFF
#define ORX_EQU_FBF_C1IM_RW__PRE                                            0x0

#define ORX_EQU_FBF_C2RE_RW__A                                              0x2030034
#define ORX_EQU_FBF_C2RE_RW__W                                              12
#define ORX_EQU_FBF_C2RE_RW__M                                              0xFFF
#define ORX_EQU_FBF_C2RE_RW__PRE                                            0x0

#define ORX_EQU_FBF_C2IM_RW__A                                              0x2030035
#define ORX_EQU_FBF_C2IM_RW__W                                              12
#define ORX_EQU_FBF_C2IM_RW__M                                              0xFFF
#define ORX_EQU_FBF_C2IM_RW__PRE                                            0x0

#define ORX_EQU_FBF_C3RE_RW__A                                              0x2030036
#define ORX_EQU_FBF_C3RE_RW__W                                              12
#define ORX_EQU_FBF_C3RE_RW__M                                              0xFFF
#define ORX_EQU_FBF_C3RE_RW__PRE                                            0x0

#define ORX_EQU_FBF_C3IM_RW__A                                              0x2030037
#define ORX_EQU_FBF_C3IM_RW__W                                              12
#define ORX_EQU_FBF_C3IM_RW__M                                              0xFFF
#define ORX_EQU_FBF_C3IM_RW__PRE                                            0x0

#define ORX_EQU_FBF_C4RE_RW__A                                              0x2030038
#define ORX_EQU_FBF_C4RE_RW__W                                              12
#define ORX_EQU_FBF_C4RE_RW__M                                              0xFFF
#define ORX_EQU_FBF_C4RE_RW__PRE                                            0x0

#define ORX_EQU_FBF_C4IM_RW__A                                              0x2030039
#define ORX_EQU_FBF_C4IM_RW__W                                              12
#define ORX_EQU_FBF_C4IM_RW__M                                              0xFFF
#define ORX_EQU_FBF_C4IM_RW__PRE                                            0x0

#define ORX_EQU_FBF_C5RE_RW__A                                              0x203003A
#define ORX_EQU_FBF_C5RE_RW__W                                              12
#define ORX_EQU_FBF_C5RE_RW__M                                              0xFFF
#define ORX_EQU_FBF_C5RE_RW__PRE                                            0x0

#define ORX_EQU_FBF_C5IM_RW__A                                              0x203003B
#define ORX_EQU_FBF_C5IM_RW__W                                              12
#define ORX_EQU_FBF_C5IM_RW__M                                              0xFFF
#define ORX_EQU_FBF_C5IM_RW__PRE                                            0x0

#define ORX_EQU_ERR_SEL_W__A                                                0x203003C
#define ORX_EQU_ERR_SEL_W__W                                                1
#define ORX_EQU_ERR_SEL_W__M                                                0x1
#define ORX_EQU_ERR_SEL_W__PRE                                              0x0
#define   ORX_EQU_ERR_SEL_W_CMA_ERROR                                       0x0
#define   ORX_EQU_ERR_SEL_W_DDA_ERROR                                       0x1

#define ORX_EQU_ERR_TIS_W__A                                                0x203003D
#define ORX_EQU_ERR_TIS_W__W                                                1
#define ORX_EQU_ERR_TIS_W__M                                                0x1
#define ORX_EQU_ERR_TIS_W__PRE                                              0x0
#define   ORX_EQU_ERR_TIS_W_CMA_SIGNALS                                     0x0
#define   ORX_EQU_ERR_TIS_W_DDA_SIGNALS                                     0x1

#define ORX_EQU_ERR_EDI_R__A                                                0x203003E
#define ORX_EQU_ERR_EDI_R__W                                                5
#define ORX_EQU_ERR_EDI_R__M                                                0x1F
#define ORX_EQU_ERR_EDI_R__PRE                                              0xF

#define ORX_EQU_ERR_EDQ_R__A                                                0x203003F
#define ORX_EQU_ERR_EDQ_R__W                                                5
#define ORX_EQU_ERR_EDQ_R__M                                                0x1F
#define ORX_EQU_ERR_EDQ_R__PRE                                              0xF

#define ORX_EQU_ERR_ECI_R__A                                                0x2030040
#define ORX_EQU_ERR_ECI_R__W                                                5
#define ORX_EQU_ERR_ECI_R__M                                                0x1F
#define ORX_EQU_ERR_ECI_R__PRE                                              0xF

#define ORX_EQU_ERR_ECQ_R__A                                                0x2030041
#define ORX_EQU_ERR_ECQ_R__W                                                5
#define ORX_EQU_ERR_ECQ_R__M                                                0x1F
#define ORX_EQU_ERR_ECQ_R__PRE                                              0xF

#define ORX_EQU_MER_MER_R__A                                                0x2030042
#define ORX_EQU_MER_MER_R__W                                                6
#define ORX_EQU_MER_MER_R__M                                                0x3F
#define ORX_EQU_MER_MER_R__PRE                                              0x3F

#define ORX_EQU_MER_LDT_W__A                                                0x2030043
#define ORX_EQU_MER_LDT_W__W                                                3
#define ORX_EQU_MER_LDT_W__M                                                0x7
#define ORX_EQU_MER_LDT_W__PRE                                              0x4

#define ORX_EQU_SYN_LEN_W__A                                                0x2030044
#define ORX_EQU_SYN_LEN_W__W                                                16
#define ORX_EQU_SYN_LEN_W__M                                                0xFFFF
#define ORX_EQU_SYN_LEN_W__PRE                                              0x0

#define ORX_DDC_COMM_EXEC__A                                                0x2040000
#define ORX_DDC_COMM_EXEC__W                                                2
#define ORX_DDC_COMM_EXEC__M                                                0x3
#define ORX_DDC_COMM_EXEC__PRE                                              0x0
#define   ORX_DDC_COMM_EXEC_STOP                                            0x0
#define   ORX_DDC_COMM_EXEC_ACTIVE                                          0x1
#define   ORX_DDC_COMM_EXEC_HOLD                                            0x2

#define ORX_DDC_COMM_MB__A                                                  0x2040002
#define ORX_DDC_COMM_MB__W                                                  6
#define ORX_DDC_COMM_MB__M                                                  0x3F
#define ORX_DDC_COMM_MB__PRE                                                0x0
#define   ORX_DDC_COMM_MB_CTL__B                                            0
#define   ORX_DDC_COMM_MB_CTL__W                                            1
#define   ORX_DDC_COMM_MB_CTL__M                                            0x1
#define   ORX_DDC_COMM_MB_CTL__PRE                                          0x0
#define     ORX_DDC_COMM_MB_CTL_OFF                                         0x0
#define     ORX_DDC_COMM_MB_CTL_ON                                          0x1
#define   ORX_DDC_COMM_MB_OBS__B                                            1
#define   ORX_DDC_COMM_MB_OBS__W                                            1
#define   ORX_DDC_COMM_MB_OBS__M                                            0x2
#define   ORX_DDC_COMM_MB_OBS__PRE                                          0x0
#define     ORX_DDC_COMM_MB_OBS_OFF                                         0x0
#define     ORX_DDC_COMM_MB_OBS_ON                                          0x2

#define   ORX_DDC_COMM_MB_CTL_MUX__B                                        2
#define   ORX_DDC_COMM_MB_CTL_MUX__W                                        2
#define   ORX_DDC_COMM_MB_CTL_MUX__M                                        0xC
#define   ORX_DDC_COMM_MB_CTL_MUX__PRE                                      0x0

#define   ORX_DDC_COMM_MB_OBS_MUX__B                                        4
#define   ORX_DDC_COMM_MB_OBS_MUX__W                                        2
#define   ORX_DDC_COMM_MB_OBS_MUX__M                                        0x30
#define   ORX_DDC_COMM_MB_OBS_MUX__PRE                                      0x0

#define ORX_DDC_COMM_INT_REQ__A                                             0x2040003
#define ORX_DDC_COMM_INT_REQ__W                                             1
#define ORX_DDC_COMM_INT_REQ__M                                             0x1
#define ORX_DDC_COMM_INT_REQ__PRE                                           0x0
#define ORX_DDC_COMM_INT_STA__A                                             0x2040005
#define ORX_DDC_COMM_INT_STA__W                                             1
#define ORX_DDC_COMM_INT_STA__M                                             0x1
#define ORX_DDC_COMM_INT_STA__PRE                                           0x0
#define ORX_DDC_COMM_INT_MSK__A                                             0x2040006
#define ORX_DDC_COMM_INT_MSK__W                                             1
#define ORX_DDC_COMM_INT_MSK__M                                             0x1
#define ORX_DDC_COMM_INT_MSK__PRE                                           0x0
#define ORX_DDC_COMM_INT_STM__A                                             0x2040007
#define ORX_DDC_COMM_INT_STM__W                                             1
#define ORX_DDC_COMM_INT_STM__M                                             0x1
#define ORX_DDC_COMM_INT_STM__PRE                                           0x0
#define ORX_DDC_DEC_MAP_W__A                                                0x2040010
#define ORX_DDC_DEC_MAP_W__W                                                9
#define ORX_DDC_DEC_MAP_W__M                                                0x1FF
#define ORX_DDC_DEC_MAP_W__PRE                                              0x178

#define   ORX_DDC_DEC_MAP_W_QUADR0__B                                       0
#define   ORX_DDC_DEC_MAP_W_QUADR0__W                                       2
#define   ORX_DDC_DEC_MAP_W_QUADR0__M                                       0x3
#define   ORX_DDC_DEC_MAP_W_QUADR0__PRE                                     0x0
#define     ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_DEFAULT                         0x0
#define     ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_ALTERNATE                       0x0

#define   ORX_DDC_DEC_MAP_W_QUADR1__B                                       2
#define   ORX_DDC_DEC_MAP_W_QUADR1__W                                       2
#define   ORX_DDC_DEC_MAP_W_QUADR1__M                                       0xC
#define   ORX_DDC_DEC_MAP_W_QUADR1__PRE                                     0x8
#define     ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_DEFAULT                         0x8
#define     ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_ALTERNATE                       0x4

#define   ORX_DDC_DEC_MAP_W_QUADR2__B                                       4
#define   ORX_DDC_DEC_MAP_W_QUADR2__W                                       2
#define   ORX_DDC_DEC_MAP_W_QUADR2__M                                       0x30
#define   ORX_DDC_DEC_MAP_W_QUADR2__PRE                                     0x30
#define     ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_DEFAULT                         0x30
#define     ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_ALTERNATE                       0x30

#define   ORX_DDC_DEC_MAP_W_QUADR3__B                                       6
#define   ORX_DDC_DEC_MAP_W_QUADR3__W                                       2
#define   ORX_DDC_DEC_MAP_W_QUADR3__M                                       0xC0
#define   ORX_DDC_DEC_MAP_W_QUADR3__PRE                                     0x40
#define     ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_DEFAULT                         0x40
#define     ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_ALTERNATE                       0x80
#define   ORX_DDC_DEC_MAP_W_DIFF_DECOD__B                                   8
#define   ORX_DDC_DEC_MAP_W_DIFF_DECOD__W                                   1
#define   ORX_DDC_DEC_MAP_W_DIFF_DECOD__M                                   0x100
#define   ORX_DDC_DEC_MAP_W_DIFF_DECOD__PRE                                 0x100
#define     ORX_DDC_DEC_MAP_W_DIFF_DECOD_COHERENT_DECODING                  0x0
#define     ORX_DDC_DEC_MAP_W_DIFF_DECOD_DIFF_DECODING                      0x100

#define ORX_DDC_OFO_SET_W__A                                                0x2040011
#define ORX_DDC_OFO_SET_W__W                                                16
#define ORX_DDC_OFO_SET_W__M                                                0xFFFF
#define ORX_DDC_OFO_SET_W__PRE                                              0x1402

#define   ORX_DDC_OFO_SET_W_PHASE__B                                        0
#define   ORX_DDC_OFO_SET_W_PHASE__W                                        7
#define   ORX_DDC_OFO_SET_W_PHASE__M                                        0x7F
#define   ORX_DDC_OFO_SET_W_PHASE__PRE                                      0x2

#define   ORX_DDC_OFO_SET_W_CRXHITIME__B                                    7
#define   ORX_DDC_OFO_SET_W_CRXHITIME__W                                    7
#define   ORX_DDC_OFO_SET_W_CRXHITIME__M                                    0x3F80
#define   ORX_DDC_OFO_SET_W_CRXHITIME__PRE                                  0x1400

#define   ORX_DDC_OFO_SET_W_CRXINV__B                                       14
#define   ORX_DDC_OFO_SET_W_CRXINV__W                                       1
#define   ORX_DDC_OFO_SET_W_CRXINV__M                                       0x4000
#define   ORX_DDC_OFO_SET_W_CRXINV__PRE                                     0x0

#define   ORX_DDC_OFO_SET_W_DISABLE__B                                      15
#define   ORX_DDC_OFO_SET_W_DISABLE__W                                      1
#define   ORX_DDC_OFO_SET_W_DISABLE__M                                      0x8000
#define   ORX_DDC_OFO_SET_W_DISABLE__PRE                                    0x0

#define ORX_CON_COMM_EXEC__A                                                0x2050000
#define ORX_CON_COMM_EXEC__W                                                2
#define ORX_CON_COMM_EXEC__M                                                0x3
#define ORX_CON_COMM_EXEC__PRE                                              0x0
#define   ORX_CON_COMM_EXEC_STOP                                            0x0
#define   ORX_CON_COMM_EXEC_ACTIVE                                          0x1
#define   ORX_CON_COMM_EXEC_HOLD                                            0x2

#define ORX_CON_LDT_W__A                                                    0x2050010
#define ORX_CON_LDT_W__W                                                    3
#define ORX_CON_LDT_W__M                                                    0x7
#define ORX_CON_LDT_W__PRE                                                  0x3

#define   ORX_CON_LDT_W_CON_LDT_W__B                                        0
#define   ORX_CON_LDT_W_CON_LDT_W__W                                        3
#define   ORX_CON_LDT_W_CON_LDT_W__M                                        0x7
#define   ORX_CON_LDT_W_CON_LDT_W__PRE                                      0x3

#define ORX_CON_RST_W__A                                                    0x2050011
#define ORX_CON_RST_W__W                                                    4
#define ORX_CON_RST_W__M                                                    0xF
#define ORX_CON_RST_W__PRE                                                  0x0

#define   ORX_CON_RST_W_CPH__B                                              0
#define   ORX_CON_RST_W_CPH__W                                              1
#define   ORX_CON_RST_W_CPH__M                                              0x1
#define   ORX_CON_RST_W_CPH__PRE                                            0x0

#define   ORX_CON_RST_W_CTI__B                                              1
#define   ORX_CON_RST_W_CTI__W                                              1
#define   ORX_CON_RST_W_CTI__M                                              0x2
#define   ORX_CON_RST_W_CTI__PRE                                            0x0

#define   ORX_CON_RST_W_KRN__B                                              2
#define   ORX_CON_RST_W_KRN__W                                              1
#define   ORX_CON_RST_W_KRN__M                                              0x4
#define   ORX_CON_RST_W_KRN__PRE                                            0x0

#define   ORX_CON_RST_W_KRP__B                                              3
#define   ORX_CON_RST_W_KRP__W                                              1
#define   ORX_CON_RST_W_KRP__M                                              0x8
#define   ORX_CON_RST_W_KRP__PRE                                            0x0

#define ORX_CON_CPH_PHI_R__A                                                0x2050012
#define ORX_CON_CPH_PHI_R__W                                                16
#define ORX_CON_CPH_PHI_R__M                                                0xFFFF
#define ORX_CON_CPH_PHI_R__PRE                                              0x0

#define ORX_CON_CPH_FRQ_R__A                                                0x2050013
#define ORX_CON_CPH_FRQ_R__W                                                16
#define ORX_CON_CPH_FRQ_R__M                                                0xFFFF
#define ORX_CON_CPH_FRQ_R__PRE                                              0x0

#define ORX_CON_CPH_AMP_R__A                                                0x2050014
#define ORX_CON_CPH_AMP_R__W                                                16
#define ORX_CON_CPH_AMP_R__M                                                0xFFFF
#define ORX_CON_CPH_AMP_R__PRE                                              0x0

#define ORX_CON_CPH_KDF_W__A                                                0x2050015
#define ORX_CON_CPH_KDF_W__W                                                4
#define ORX_CON_CPH_KDF_W__M                                                0xF
#define ORX_CON_CPH_KDF_W__PRE                                              0x0

#define ORX_CON_CPH_KPF_W__A                                                0x2050016
#define ORX_CON_CPH_KPF_W__W                                                4
#define ORX_CON_CPH_KPF_W__M                                                0xF
#define ORX_CON_CPH_KPF_W__PRE                                              0x0

#define ORX_CON_CPH_KIF_W__A                                                0x2050017
#define ORX_CON_CPH_KIF_W__W                                                4
#define ORX_CON_CPH_KIF_W__M                                                0xF
#define ORX_CON_CPH_KIF_W__PRE                                              0x0
#define ORX_CON_CPH_APT_W__A                                                0x2050018
#define ORX_CON_CPH_APT_W__W                                                16
#define ORX_CON_CPH_APT_W__M                                                0xFFFF
#define ORX_CON_CPH_APT_W__PRE                                              0x804

#define   ORX_CON_CPH_APT_W_PTH__B                                          0
#define   ORX_CON_CPH_APT_W_PTH__W                                          8
#define   ORX_CON_CPH_APT_W_PTH__M                                          0xFF
#define   ORX_CON_CPH_APT_W_PTH__PRE                                        0x4

#define   ORX_CON_CPH_APT_W_ATH__B                                          8
#define   ORX_CON_CPH_APT_W_ATH__W                                          8
#define   ORX_CON_CPH_APT_W_ATH__M                                          0xFF00
#define   ORX_CON_CPH_APT_W_ATH__PRE                                        0x800

#define ORX_CON_CPH_WLC_W__A                                                0x2050019
#define ORX_CON_CPH_WLC_W__W                                                8
#define ORX_CON_CPH_WLC_W__M                                                0xFF
#define ORX_CON_CPH_WLC_W__PRE                                              0x81

#define   ORX_CON_CPH_WLC_W_LATC__B                                         0
#define   ORX_CON_CPH_WLC_W_LATC__W                                         4
#define   ORX_CON_CPH_WLC_W_LATC__M                                         0xF
#define   ORX_CON_CPH_WLC_W_LATC__PRE                                       0x1

#define   ORX_CON_CPH_WLC_W_WLIM__B                                         4
#define   ORX_CON_CPH_WLC_W_WLIM__W                                         4
#define   ORX_CON_CPH_WLC_W_WLIM__M                                         0xF0
#define   ORX_CON_CPH_WLC_W_WLIM__PRE                                       0x80

#define ORX_CON_CPH_DLY_W__A                                                0x205001A
#define ORX_CON_CPH_DLY_W__W                                                3
#define ORX_CON_CPH_DLY_W__M                                                0x7
#define ORX_CON_CPH_DLY_W__PRE                                              0x4

#define ORX_CON_CPH_TCL_W__A                                                0x205001B
#define ORX_CON_CPH_TCL_W__W                                                3
#define ORX_CON_CPH_TCL_W__M                                                0x7
#define ORX_CON_CPH_TCL_W__PRE                                              0x3

#define ORX_CON_KRP_AMP_R__A                                                0x205001C
#define ORX_CON_KRP_AMP_R__W                                                9
#define ORX_CON_KRP_AMP_R__M                                                0x1FF
#define ORX_CON_KRP_AMP_R__PRE                                              0x0

#define ORX_CON_KRN_AMP_R__A                                                0x205001D
#define ORX_CON_KRN_AMP_R__W                                                9
#define ORX_CON_KRN_AMP_R__M                                                0x1FF
#define ORX_CON_KRN_AMP_R__PRE                                              0x0

#define ORX_CON_CTI_DTI_R__A                                                0x205001E
#define ORX_CON_CTI_DTI_R__W                                                16
#define ORX_CON_CTI_DTI_R__M                                                0xFFFF
#define ORX_CON_CTI_DTI_R__PRE                                              0x0

#define ORX_CON_CTI_KDT_W__A                                                0x205001F
#define ORX_CON_CTI_KDT_W__W                                                4
#define ORX_CON_CTI_KDT_W__M                                                0xF
#define ORX_CON_CTI_KDT_W__PRE                                              0x4

#define ORX_CON_CTI_KPT_W__A                                                0x2050020
#define ORX_CON_CTI_KPT_W__W                                                4
#define ORX_CON_CTI_KPT_W__M                                                0xF
#define ORX_CON_CTI_KPT_W__PRE                                              0x3

#define ORX_CON_CTI_KIT_W__A                                                0x2050021
#define ORX_CON_CTI_KIT_W__W                                                4
#define ORX_CON_CTI_KIT_W__M                                                0xF
#define ORX_CON_CTI_KIT_W__PRE                                              0xB

#define ORX_CON_CTI_TAT_W__A                                                0x2050022
#define ORX_CON_CTI_TAT_W__W                                                4
#define ORX_CON_CTI_TAT_W__M                                                0xF
#define ORX_CON_CTI_TAT_W__PRE                                              0x3

#define ORX_NSU_COMM_EXEC__A                                                0x2060000
#define ORX_NSU_COMM_EXEC__W                                                2
#define ORX_NSU_COMM_EXEC__M                                                0x3
#define ORX_NSU_COMM_EXEC__PRE                                              0x0
#define   ORX_NSU_COMM_EXEC_STOP                                            0x0
#define   ORX_NSU_COMM_EXEC_ACTIVE                                          0x1
#define   ORX_NSU_COMM_EXEC_HOLD                                            0x2

#define ORX_NSU_AOX_STDBY_W__A                                              0x2060010
#define ORX_NSU_AOX_STDBY_W__W                                              8
#define ORX_NSU_AOX_STDBY_W__M                                              0xFF
#define ORX_NSU_AOX_STDBY_W__PRE                                            0x0

#define   ORX_NSU_AOX_STDBY_W_STDBYADC__B                                   0
#define   ORX_NSU_AOX_STDBY_W_STDBYADC__W                                   1
#define   ORX_NSU_AOX_STDBY_W_STDBYADC__M                                   0x1
#define   ORX_NSU_AOX_STDBY_W_STDBYADC__PRE                                 0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYADC_A1_ON                              0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYADC_A1_OFF                             0x1
#define     ORX_NSU_AOX_STDBY_W_STDBYADC_A2_OFF                             0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON                              0x1

#define   ORX_NSU_AOX_STDBY_W_STDBYAMP__B                                   1
#define   ORX_NSU_AOX_STDBY_W_STDBYAMP__W                                   1
#define   ORX_NSU_AOX_STDBY_W_STDBYAMP__M                                   0x2
#define   ORX_NSU_AOX_STDBY_W_STDBYAMP__PRE                                 0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_ON                              0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_OFF                             0x2
#define     ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_OFF                             0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON                              0x2

#define   ORX_NSU_AOX_STDBY_W_STDBYBIAS__B                                  2
#define   ORX_NSU_AOX_STDBY_W_STDBYBIAS__W                                  1
#define   ORX_NSU_AOX_STDBY_W_STDBYBIAS__M                                  0x4
#define   ORX_NSU_AOX_STDBY_W_STDBYBIAS__PRE                                0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_ON                             0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_OFF                            0x4
#define     ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_OFF                            0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON                             0x4

#define   ORX_NSU_AOX_STDBY_W_STDBYPLL__B                                   3
#define   ORX_NSU_AOX_STDBY_W_STDBYPLL__W                                   1
#define   ORX_NSU_AOX_STDBY_W_STDBYPLL__M                                   0x8
#define   ORX_NSU_AOX_STDBY_W_STDBYPLL__PRE                                 0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_ON                              0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_OFF                             0x8
#define     ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_OFF                             0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON                              0x8

#define   ORX_NSU_AOX_STDBY_W_STDBYPD__B                                    4
#define   ORX_NSU_AOX_STDBY_W_STDBYPD__W                                    1
#define   ORX_NSU_AOX_STDBY_W_STDBYPD__M                                    0x10
#define   ORX_NSU_AOX_STDBY_W_STDBYPD__PRE                                  0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYPD_A1_ON                               0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYPD_A1_OFF                              0x10
#define     ORX_NSU_AOX_STDBY_W_STDBYPD_A2_OFF                              0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON                               0x10

#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__B                               5
#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__W                               1
#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__M                               0x20
#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__PRE                             0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_ON                          0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_OFF                         0x20
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_OFF                         0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON                          0x20

#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__B                               6
#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__W                               1
#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__M                               0x40
#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__PRE                             0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_ON                          0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_OFF                         0x40
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_OFF                         0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON                          0x40

#define   ORX_NSU_AOX_STDBY_W_STDBYFLT__B                                   7
#define   ORX_NSU_AOX_STDBY_W_STDBYFLT__W                                   1
#define   ORX_NSU_AOX_STDBY_W_STDBYFLT__M                                   0x80
#define   ORX_NSU_AOX_STDBY_W_STDBYFLT__PRE                                 0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_ON                              0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_OFF                             0x80
#define     ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_OFF                             0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON                              0x80

#define ORX_NSU_AOX_LOFRQ_W__A                                              0x2060011
#define ORX_NSU_AOX_LOFRQ_W__W                                              16
#define ORX_NSU_AOX_LOFRQ_W__M                                              0xFFFF
#define ORX_NSU_AOX_LOFRQ_W__PRE                                            0x0
#define ORX_NSU_AOX_LOMDE_W__A                                              0x2060012
#define ORX_NSU_AOX_LOMDE_W__W                                              16
#define ORX_NSU_AOX_LOMDE_W__M                                              0xFFFF
#define ORX_NSU_AOX_LOMDE_W__PRE                                            0x0

#define   ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__B                              0
#define   ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__W                              8
#define   ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__M                              0xFF
#define   ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__PRE                            0x0

#define   ORX_NSU_AOX_LOMDE_W_RESET_VCO__B                                  13
#define   ORX_NSU_AOX_LOMDE_W_RESET_VCO__W                                  1
#define   ORX_NSU_AOX_LOMDE_W_RESET_VCO__M                                  0x2000
#define   ORX_NSU_AOX_LOMDE_W_RESET_VCO__PRE                                0x0

#define   ORX_NSU_AOX_LOMDE_W_PLL_DIV__B                                    14
#define   ORX_NSU_AOX_LOMDE_W_PLL_DIV__W                                    2
#define   ORX_NSU_AOX_LOMDE_W_PLL_DIV__M                                    0xC000
#define   ORX_NSU_AOX_LOMDE_W_PLL_DIV__PRE                                  0x0

#define ORX_NSU_AOX_LOPOW_W__A                                              0x2060013
#define ORX_NSU_AOX_LOPOW_W__W                                              2
#define ORX_NSU_AOX_LOPOW_W__M                                              0x3
#define ORX_NSU_AOX_LOPOW_W__PRE                                            0x0
#define   ORX_NSU_AOX_LOPOW_W_POWER_MINUS0DB                                0x0
#define   ORX_NSU_AOX_LOPOW_W_POWER_MINUS5DB                                0x1
#define   ORX_NSU_AOX_LOPOW_W_POWER_MINUS10DB                               0x2
#define   ORX_NSU_AOX_LOPOW_W_POWER_MINUS15DB                               0x3

#define ORX_NSU_AOX_STHR_W__A                                               0x2060014
#define ORX_NSU_AOX_STHR_W__W                                               5
#define ORX_NSU_AOX_STHR_W__M                                               0x1F
#define ORX_NSU_AOX_STHR_W__PRE                                             0x0

#define ORX_NSU_TUN_RFGAIN_W__A                                             0x2060015
#define ORX_NSU_TUN_RFGAIN_W__W                                             15
#define ORX_NSU_TUN_RFGAIN_W__M                                             0x7FFF
#define ORX_NSU_TUN_RFGAIN_W__PRE                                           0x0

#define ORX_NSU_TUN_IFGAIN_W__A                                             0x2060016
#define ORX_NSU_TUN_IFGAIN_W__W                                             15
#define ORX_NSU_TUN_IFGAIN_W__M                                             0x7FFF
#define ORX_NSU_TUN_IFGAIN_W__PRE                                           0x0

#define ORX_NSU_TUN_BPF_W__A                                                0x2060017
#define ORX_NSU_TUN_BPF_W__W                                                15
#define ORX_NSU_TUN_BPF_W__M                                                0x7FFF
#define ORX_NSU_TUN_BPF_W__PRE                                              0x1F9
#define ORX_NSU_NSS_BITSWAP_W__A                                            0x2060018
#define ORX_NSU_NSS_BITSWAP_W__W                                            3
#define ORX_NSU_NSS_BITSWAP_W__M                                            0x7
#define ORX_NSU_NSS_BITSWAP_W__PRE                                          0x0

#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__B                           0
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__W                           1
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__M                           0x1
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__PRE                         0x0

#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__B                           1
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__W                           1
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__M                           0x2
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__PRE                         0x0

#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__B                           2
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__W                           1
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__M                           0x4
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__PRE                         0x0

#define ORX_TST_COMM_EXEC__A                                                0x23F0000
#define ORX_TST_COMM_EXEC__W                                                2
#define ORX_TST_COMM_EXEC__M                                                0x3
#define ORX_TST_COMM_EXEC__PRE                                              0x0
#define   ORX_TST_COMM_EXEC_STOP                                            0x0
#define   ORX_TST_COMM_EXEC_ACTIVE                                          0x1
#define   ORX_TST_COMM_EXEC_HOLD                                            0x2

#define ORX_TST_AOX_TST_W__A                                                0x23F0010
#define ORX_TST_AOX_TST_W__W                                                8
#define ORX_TST_AOX_TST_W__M                                                0xFF
#define ORX_TST_AOX_TST_W__PRE                                              0x0

#define QAM_COMM_EXEC__A                                                    0x1400000
#define QAM_COMM_EXEC__W                                                    2
#define QAM_COMM_EXEC__M                                                    0x3
#define QAM_COMM_EXEC__PRE                                                  0x0
#define   QAM_COMM_EXEC_STOP                                                0x0
#define   QAM_COMM_EXEC_ACTIVE                                              0x1
#define   QAM_COMM_EXEC_HOLD                                                0x2

#define QAM_COMM_MB__A                                                      0x1400002
#define QAM_COMM_MB__W                                                      16
#define QAM_COMM_MB__M                                                      0xFFFF
#define QAM_COMM_MB__PRE                                                    0x0
#define QAM_COMM_INT_REQ__A                                                 0x1400003
#define QAM_COMM_INT_REQ__W                                                 16
#define QAM_COMM_INT_REQ__M                                                 0xFFFF
#define QAM_COMM_INT_REQ__PRE                                               0x0

#define   QAM_COMM_INT_REQ_SL_REQ__B                                        0
#define   QAM_COMM_INT_REQ_SL_REQ__W                                        1
#define   QAM_COMM_INT_REQ_SL_REQ__M                                        0x1
#define   QAM_COMM_INT_REQ_SL_REQ__PRE                                      0x0

#define   QAM_COMM_INT_REQ_LC_REQ__B                                        1
#define   QAM_COMM_INT_REQ_LC_REQ__W                                        1
#define   QAM_COMM_INT_REQ_LC_REQ__M                                        0x2
#define   QAM_COMM_INT_REQ_LC_REQ__PRE                                      0x0

#define   QAM_COMM_INT_REQ_VD_REQ__B                                        2
#define   QAM_COMM_INT_REQ_VD_REQ__W                                        1
#define   QAM_COMM_INT_REQ_VD_REQ__M                                        0x4
#define   QAM_COMM_INT_REQ_VD_REQ__PRE                                      0x0

#define   QAM_COMM_INT_REQ_SY_REQ__B                                        3
#define   QAM_COMM_INT_REQ_SY_REQ__W                                        1
#define   QAM_COMM_INT_REQ_SY_REQ__M                                        0x8
#define   QAM_COMM_INT_REQ_SY_REQ__PRE                                      0x0

#define QAM_COMM_INT_STA__A                                                 0x1400005
#define QAM_COMM_INT_STA__W                                                 16
#define QAM_COMM_INT_STA__M                                                 0xFFFF
#define QAM_COMM_INT_STA__PRE                                               0x0
#define QAM_COMM_INT_MSK__A                                                 0x1400006
#define QAM_COMM_INT_MSK__W                                                 16
#define QAM_COMM_INT_MSK__M                                                 0xFFFF
#define QAM_COMM_INT_MSK__PRE                                               0x0
#define QAM_COMM_INT_STM__A                                                 0x1400007
#define QAM_COMM_INT_STM__W                                                 16
#define QAM_COMM_INT_STM__M                                                 0xFFFF
#define QAM_COMM_INT_STM__PRE                                               0x0

#define QAM_TOP_COMM_EXEC__A                                                0x1410000
#define QAM_TOP_COMM_EXEC__W                                                2
#define QAM_TOP_COMM_EXEC__M                                                0x3
#define QAM_TOP_COMM_EXEC__PRE                                              0x0
#define   QAM_TOP_COMM_EXEC_STOP                                            0x0
#define   QAM_TOP_COMM_EXEC_ACTIVE                                          0x1
#define   QAM_TOP_COMM_EXEC_HOLD                                            0x2

#define QAM_TOP_ANNEX__A                                                    0x1410010
#define QAM_TOP_ANNEX__W                                                    2
#define QAM_TOP_ANNEX__M                                                    0x3
#define QAM_TOP_ANNEX__PRE                                                  0x1
#define   QAM_TOP_ANNEX_A                                                   0x0
#define   QAM_TOP_ANNEX_B                                                   0x1
#define   QAM_TOP_ANNEX_C                                                   0x2
#define   QAM_TOP_ANNEX_D                                                   0x3

#define QAM_TOP_CONSTELLATION__A                                            0x1410011
#define QAM_TOP_CONSTELLATION__W                                            3
#define QAM_TOP_CONSTELLATION__M                                            0x7
#define QAM_TOP_CONSTELLATION__PRE                                          0x5
#define   QAM_TOP_CONSTELLATION_NONE                                        0x0
#define   QAM_TOP_CONSTELLATION_QPSK                                        0x1
#define   QAM_TOP_CONSTELLATION_QAM8                                        0x2
#define   QAM_TOP_CONSTELLATION_QAM16                                       0x3
#define   QAM_TOP_CONSTELLATION_QAM32                                       0x4
#define   QAM_TOP_CONSTELLATION_QAM64                                       0x5
#define   QAM_TOP_CONSTELLATION_QAM128                                      0x6
#define   QAM_TOP_CONSTELLATION_QAM256                                      0x7

#define QAM_FQ_COMM_EXEC__A                                                 0x1420000
#define QAM_FQ_COMM_EXEC__W                                                 2
#define QAM_FQ_COMM_EXEC__M                                                 0x3
#define QAM_FQ_COMM_EXEC__PRE                                               0x0
#define   QAM_FQ_COMM_EXEC_STOP                                             0x0
#define   QAM_FQ_COMM_EXEC_ACTIVE                                           0x1
#define   QAM_FQ_COMM_EXEC_HOLD                                             0x2

#define QAM_FQ_MODE__A                                                      0x1420010
#define QAM_FQ_MODE__W                                                      3
#define QAM_FQ_MODE__M                                                      0x7
#define QAM_FQ_MODE__PRE                                                    0x0

#define   QAM_FQ_MODE_TAPRESET__B                                           0
#define   QAM_FQ_MODE_TAPRESET__W                                           1
#define   QAM_FQ_MODE_TAPRESET__M                                           0x1
#define   QAM_FQ_MODE_TAPRESET__PRE                                         0x0
#define     QAM_FQ_MODE_TAPRESET_RST                                        0x1

#define   QAM_FQ_MODE_TAPLMS__B                                             1
#define   QAM_FQ_MODE_TAPLMS__W                                             1
#define   QAM_FQ_MODE_TAPLMS__M                                             0x2
#define   QAM_FQ_MODE_TAPLMS__PRE                                           0x0
#define     QAM_FQ_MODE_TAPLMS_UPD                                          0x2

#define   QAM_FQ_MODE_TAPDRAIN__B                                           2
#define   QAM_FQ_MODE_TAPDRAIN__W                                           1
#define   QAM_FQ_MODE_TAPDRAIN__M                                           0x4
#define   QAM_FQ_MODE_TAPDRAIN__PRE                                         0x0
#define     QAM_FQ_MODE_TAPDRAIN_DRAIN                                      0x4

#define QAM_FQ_MU_FACTOR__A                                                 0x1420011
#define QAM_FQ_MU_FACTOR__W                                                 3
#define QAM_FQ_MU_FACTOR__M                                                 0x7
#define QAM_FQ_MU_FACTOR__PRE                                               0x0

#define QAM_FQ_LA_FACTOR__A                                                 0x1420012
#define QAM_FQ_LA_FACTOR__W                                                 4
#define QAM_FQ_LA_FACTOR__M                                                 0xF
#define QAM_FQ_LA_FACTOR__PRE                                               0xC
#define QAM_FQ_CENTTAP_IDX__A                                               0x1420016
#define QAM_FQ_CENTTAP_IDX__W                                               5
#define QAM_FQ_CENTTAP_IDX__M                                               0x1F
#define QAM_FQ_CENTTAP_IDX__PRE                                             0x13

#define   QAM_FQ_CENTTAP_IDX_IDX__B                                         0
#define   QAM_FQ_CENTTAP_IDX_IDX__W                                         5
#define   QAM_FQ_CENTTAP_IDX_IDX__M                                         0x1F
#define   QAM_FQ_CENTTAP_IDX_IDX__PRE                                       0x13

#define QAM_FQ_CENTTAP_VALUE__A                                             0x1420017
#define QAM_FQ_CENTTAP_VALUE__W                                             12
#define QAM_FQ_CENTTAP_VALUE__M                                             0xFFF
#define QAM_FQ_CENTTAP_VALUE__PRE                                           0x600

#define   QAM_FQ_CENTTAP_VALUE_TAP__B                                       0
#define   QAM_FQ_CENTTAP_VALUE_TAP__W                                       12
#define   QAM_FQ_CENTTAP_VALUE_TAP__M                                       0xFFF
#define   QAM_FQ_CENTTAP_VALUE_TAP__PRE                                     0x600

#define QAM_FQ_TAP_RE_EL0__A                                                0x1420020
#define QAM_FQ_TAP_RE_EL0__W                                                12
#define QAM_FQ_TAP_RE_EL0__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL0__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL0_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL0_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL0_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL0_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL0__A                                                0x1420021
#define QAM_FQ_TAP_IM_EL0__W                                                12
#define QAM_FQ_TAP_IM_EL0__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL0__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL0_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL0_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL0_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL0_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL1__A                                                0x1420022
#define QAM_FQ_TAP_RE_EL1__W                                                12
#define QAM_FQ_TAP_RE_EL1__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL1__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL1_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL1_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL1_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL1_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL1__A                                                0x1420023
#define QAM_FQ_TAP_IM_EL1__W                                                12
#define QAM_FQ_TAP_IM_EL1__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL1__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL1_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL1_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL1_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL1_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL2__A                                                0x1420024
#define QAM_FQ_TAP_RE_EL2__W                                                12
#define QAM_FQ_TAP_RE_EL2__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL2__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL2_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL2_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL2_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL2_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL2__A                                                0x1420025
#define QAM_FQ_TAP_IM_EL2__W                                                12
#define QAM_FQ_TAP_IM_EL2__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL2__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL2_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL2_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL2_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL2_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL3__A                                                0x1420026
#define QAM_FQ_TAP_RE_EL3__W                                                12
#define QAM_FQ_TAP_RE_EL3__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL3__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL3_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL3_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL3_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL3_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL3__A                                                0x1420027
#define QAM_FQ_TAP_IM_EL3__W                                                12
#define QAM_FQ_TAP_IM_EL3__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL3__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL3_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL3_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL3_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL3_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL4__A                                                0x1420028
#define QAM_FQ_TAP_RE_EL4__W                                                12
#define QAM_FQ_TAP_RE_EL4__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL4__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL4_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL4_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL4_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL4_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL4__A                                                0x1420029
#define QAM_FQ_TAP_IM_EL4__W                                                12
#define QAM_FQ_TAP_IM_EL4__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL4__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL4_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL4_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL4_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL4_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL5__A                                                0x142002A
#define QAM_FQ_TAP_RE_EL5__W                                                12
#define QAM_FQ_TAP_RE_EL5__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL5__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL5_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL5_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL5_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL5_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL5__A                                                0x142002B
#define QAM_FQ_TAP_IM_EL5__W                                                12
#define QAM_FQ_TAP_IM_EL5__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL5__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL5_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL5_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL5_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL5_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL6__A                                                0x142002C
#define QAM_FQ_TAP_RE_EL6__W                                                12
#define QAM_FQ_TAP_RE_EL6__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL6__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL6_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL6_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL6_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL6_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL6__A                                                0x142002D
#define QAM_FQ_TAP_IM_EL6__W                                                12
#define QAM_FQ_TAP_IM_EL6__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL6__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL6_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL6_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL6_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL6_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL7__A                                                0x142002E
#define QAM_FQ_TAP_RE_EL7__W                                                12
#define QAM_FQ_TAP_RE_EL7__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL7__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL7_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL7_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL7_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL7_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL7__A                                                0x142002F
#define QAM_FQ_TAP_IM_EL7__W                                                12
#define QAM_FQ_TAP_IM_EL7__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL7__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL7_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL7_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL7_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL7_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL8__A                                                0x1420030
#define QAM_FQ_TAP_RE_EL8__W                                                12
#define QAM_FQ_TAP_RE_EL8__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL8__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL8_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL8_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL8_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL8_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL8__A                                                0x1420031
#define QAM_FQ_TAP_IM_EL8__W                                                12
#define QAM_FQ_TAP_IM_EL8__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL8__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL8_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL8_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL8_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL8_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL9__A                                                0x1420032
#define QAM_FQ_TAP_RE_EL9__W                                                12
#define QAM_FQ_TAP_RE_EL9__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL9__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL9_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL9_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL9_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL9_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL9__A                                                0x1420033
#define QAM_FQ_TAP_IM_EL9__W                                                12
#define QAM_FQ_TAP_IM_EL9__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL9__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL9_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL9_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL9_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL9_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL10__A                                               0x1420034
#define QAM_FQ_TAP_RE_EL10__W                                               12
#define QAM_FQ_TAP_RE_EL10__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL10__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL10_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL10_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL10_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL10_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL10__A                                               0x1420035
#define QAM_FQ_TAP_IM_EL10__W                                               12
#define QAM_FQ_TAP_IM_EL10__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL10__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL10_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL10_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL10_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL10_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL11__A                                               0x1420036
#define QAM_FQ_TAP_RE_EL11__W                                               12
#define QAM_FQ_TAP_RE_EL11__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL11__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL11_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL11_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL11_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL11_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL11__A                                               0x1420037
#define QAM_FQ_TAP_IM_EL11__W                                               12
#define QAM_FQ_TAP_IM_EL11__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL11__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL11_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL11_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL11_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL11_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL12__A                                               0x1420038
#define QAM_FQ_TAP_RE_EL12__W                                               12
#define QAM_FQ_TAP_RE_EL12__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL12__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL12_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL12_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL12_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL12_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL12__A                                               0x1420039
#define QAM_FQ_TAP_IM_EL12__W                                               12
#define QAM_FQ_TAP_IM_EL12__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL12__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL12_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL12_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL12_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL12_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL13__A                                               0x142003A
#define QAM_FQ_TAP_RE_EL13__W                                               12
#define QAM_FQ_TAP_RE_EL13__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL13__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL13_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL13_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL13_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL13_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL13__A                                               0x142003B
#define QAM_FQ_TAP_IM_EL13__W                                               12
#define QAM_FQ_TAP_IM_EL13__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL13__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL13_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL13_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL13_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL13_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL14__A                                               0x142003C
#define QAM_FQ_TAP_RE_EL14__W                                               12
#define QAM_FQ_TAP_RE_EL14__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL14__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL14_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL14_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL14_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL14_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL14__A                                               0x142003D
#define QAM_FQ_TAP_IM_EL14__W                                               12
#define QAM_FQ_TAP_IM_EL14__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL14__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL14_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL14_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL14_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL14_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL15__A                                               0x142003E
#define QAM_FQ_TAP_RE_EL15__W                                               12
#define QAM_FQ_TAP_RE_EL15__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL15__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL15_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL15_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL15_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL15_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL15__A                                               0x142003F
#define QAM_FQ_TAP_IM_EL15__W                                               12
#define QAM_FQ_TAP_IM_EL15__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL15__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL15_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL15_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL15_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL15_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL16__A                                               0x1420040
#define QAM_FQ_TAP_RE_EL16__W                                               12
#define QAM_FQ_TAP_RE_EL16__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL16__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL16_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL16_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL16_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL16_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL16__A                                               0x1420041
#define QAM_FQ_TAP_IM_EL16__W                                               12
#define QAM_FQ_TAP_IM_EL16__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL16__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL16_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL16_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL16_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL16_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL17__A                                               0x1420042
#define QAM_FQ_TAP_RE_EL17__W                                               12
#define QAM_FQ_TAP_RE_EL17__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL17__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL17_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL17_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL17_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL17_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL17__A                                               0x1420043
#define QAM_FQ_TAP_IM_EL17__W                                               12
#define QAM_FQ_TAP_IM_EL17__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL17__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL17_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL17_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL17_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL17_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL18__A                                               0x1420044
#define QAM_FQ_TAP_RE_EL18__W                                               12
#define QAM_FQ_TAP_RE_EL18__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL18__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL18_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL18_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL18_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL18_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL18__A                                               0x1420045
#define QAM_FQ_TAP_IM_EL18__W                                               12
#define QAM_FQ_TAP_IM_EL18__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL18__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL18_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL18_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL18_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL18_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL19__A                                               0x1420046
#define QAM_FQ_TAP_RE_EL19__W                                               12
#define QAM_FQ_TAP_RE_EL19__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL19__PRE                                             0x600

#define   QAM_FQ_TAP_RE_EL19_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL19_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL19_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL19_TAP__PRE                                       0x600

#define QAM_FQ_TAP_IM_EL19__A                                               0x1420047
#define QAM_FQ_TAP_IM_EL19__W                                               12
#define QAM_FQ_TAP_IM_EL19__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL19__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL19_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL19_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL19_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL19_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL20__A                                               0x1420048
#define QAM_FQ_TAP_RE_EL20__W                                               12
#define QAM_FQ_TAP_RE_EL20__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL20__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL20_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL20_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL20_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL20_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL20__A                                               0x1420049
#define QAM_FQ_TAP_IM_EL20__W                                               12
#define QAM_FQ_TAP_IM_EL20__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL20__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL20_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL20_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL20_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL20_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL21__A                                               0x142004A
#define QAM_FQ_TAP_RE_EL21__W                                               12
#define QAM_FQ_TAP_RE_EL21__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL21__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL21_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL21_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL21_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL21_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL21__A                                               0x142004B
#define QAM_FQ_TAP_IM_EL21__W                                               12
#define QAM_FQ_TAP_IM_EL21__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL21__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL21_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL21_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL21_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL21_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL22__A                                               0x142004C
#define QAM_FQ_TAP_RE_EL22__W                                               12
#define QAM_FQ_TAP_RE_EL22__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL22__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL22_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL22_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL22_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL22_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL22__A                                               0x142004D
#define QAM_FQ_TAP_IM_EL22__W                                               12
#define QAM_FQ_TAP_IM_EL22__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL22__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL22_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL22_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL22_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL22_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL23__A                                               0x142004E
#define QAM_FQ_TAP_RE_EL23__W                                               12
#define QAM_FQ_TAP_RE_EL23__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL23__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL23_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL23_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL23_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL23_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL23__A                                               0x142004F
#define QAM_FQ_TAP_IM_EL23__W                                               12
#define QAM_FQ_TAP_IM_EL23__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL23__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL23_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL23_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL23_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL23_TAP__PRE                                       0x2

#define QAM_SL_COMM_EXEC__A                                                 0x1430000
#define QAM_SL_COMM_EXEC__W                                                 2
#define QAM_SL_COMM_EXEC__M                                                 0x3
#define QAM_SL_COMM_EXEC__PRE                                               0x0
#define   QAM_SL_COMM_EXEC_STOP                                             0x0
#define   QAM_SL_COMM_EXEC_ACTIVE                                           0x1
#define   QAM_SL_COMM_EXEC_HOLD                                             0x2

#define QAM_SL_COMM_MB__A                                                   0x1430002
#define QAM_SL_COMM_MB__W                                                   4
#define QAM_SL_COMM_MB__M                                                   0xF
#define QAM_SL_COMM_MB__PRE                                                 0x0
#define   QAM_SL_COMM_MB_CTL__B                                             0
#define   QAM_SL_COMM_MB_CTL__W                                             1
#define   QAM_SL_COMM_MB_CTL__M                                             0x1
#define   QAM_SL_COMM_MB_CTL__PRE                                           0x0
#define     QAM_SL_COMM_MB_CTL_OFF                                          0x0
#define     QAM_SL_COMM_MB_CTL_ON                                           0x1
#define   QAM_SL_COMM_MB_OBS__B                                             1
#define   QAM_SL_COMM_MB_OBS__W                                             1
#define   QAM_SL_COMM_MB_OBS__M                                             0x2
#define   QAM_SL_COMM_MB_OBS__PRE                                           0x0
#define     QAM_SL_COMM_MB_OBS_OFF                                          0x0
#define     QAM_SL_COMM_MB_OBS_ON                                           0x2
#define   QAM_SL_COMM_MB_MUX_OBS__B                                         2
#define   QAM_SL_COMM_MB_MUX_OBS__W                                         2
#define   QAM_SL_COMM_MB_MUX_OBS__M                                         0xC
#define   QAM_SL_COMM_MB_MUX_OBS__PRE                                       0x0
#define     QAM_SL_COMM_MB_MUX_OBS_CONST_CORR                               0x0
#define     QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O                               0x4
#define     QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O                               0x8
#define     QAM_SL_COMM_MB_MUX_OBS_VDEC_O                                   0xC

#define QAM_SL_COMM_INT_REQ__A                                              0x1430003
#define QAM_SL_COMM_INT_REQ__W                                              1
#define QAM_SL_COMM_INT_REQ__M                                              0x1
#define QAM_SL_COMM_INT_REQ__PRE                                            0x0
#define QAM_SL_COMM_INT_STA__A                                              0x1430005
#define QAM_SL_COMM_INT_STA__W                                              2
#define QAM_SL_COMM_INT_STA__M                                              0x3
#define QAM_SL_COMM_INT_STA__PRE                                            0x0

#define   QAM_SL_COMM_INT_STA_MED_ERR_INT__B                                0
#define   QAM_SL_COMM_INT_STA_MED_ERR_INT__W                                1
#define   QAM_SL_COMM_INT_STA_MED_ERR_INT__M                                0x1
#define   QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE                              0x0

#define   QAM_SL_COMM_INT_STA_MER_INT__B                                    1
#define   QAM_SL_COMM_INT_STA_MER_INT__W                                    1
#define   QAM_SL_COMM_INT_STA_MER_INT__M                                    0x2
#define   QAM_SL_COMM_INT_STA_MER_INT__PRE                                  0x0

#define QAM_SL_COMM_INT_MSK__A                                              0x1430006
#define QAM_SL_COMM_INT_MSK__W                                              2
#define QAM_SL_COMM_INT_MSK__M                                              0x3
#define QAM_SL_COMM_INT_MSK__PRE                                            0x0
#define   QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B                                0
#define   QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W                                1
#define   QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M                                0x1
#define   QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE                              0x0
#define   QAM_SL_COMM_INT_MSK_MER_MSK__B                                    1
#define   QAM_SL_COMM_INT_MSK_MER_MSK__W                                    1
#define   QAM_SL_COMM_INT_MSK_MER_MSK__M                                    0x2
#define   QAM_SL_COMM_INT_MSK_MER_MSK__PRE                                  0x0

#define QAM_SL_COMM_INT_STM__A                                              0x1430007
#define QAM_SL_COMM_INT_STM__W                                              2
#define QAM_SL_COMM_INT_STM__M                                              0x3
#define QAM_SL_COMM_INT_STM__PRE                                            0x0
#define   QAM_SL_COMM_INT_STM_MED_ERR_STM__B                                0
#define   QAM_SL_COMM_INT_STM_MED_ERR_STM__W                                1
#define   QAM_SL_COMM_INT_STM_MED_ERR_STM__M                                0x1
#define   QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE                              0x0
#define   QAM_SL_COMM_INT_STM_MER_STM__B                                    1
#define   QAM_SL_COMM_INT_STM_MER_STM__W                                    1
#define   QAM_SL_COMM_INT_STM_MER_STM__M                                    0x2
#define   QAM_SL_COMM_INT_STM_MER_STM__PRE                                  0x0

#define QAM_SL_MODE__A                                                      0x1430010
#define QAM_SL_MODE__W                                                      11
#define QAM_SL_MODE__M                                                      0x7FF
#define QAM_SL_MODE__PRE                                                    0x0

#define   QAM_SL_MODE_SLICER4LC__B                                          0
#define   QAM_SL_MODE_SLICER4LC__W                                          2
#define   QAM_SL_MODE_SLICER4LC__M                                          0x3
#define   QAM_SL_MODE_SLICER4LC__PRE                                        0x0
#define     QAM_SL_MODE_SLICER4LC_RECT                                      0x0
#define     QAM_SL_MODE_SLICER4LC_ONET                                      0x1
#define     QAM_SL_MODE_SLICER4LC_RAD                                       0x2

#define   QAM_SL_MODE_SLICER4DQ__B                                          2
#define   QAM_SL_MODE_SLICER4DQ__W                                          2
#define   QAM_SL_MODE_SLICER4DQ__M                                          0xC
#define   QAM_SL_MODE_SLICER4DQ__PRE                                        0x0
#define     QAM_SL_MODE_SLICER4DQ_RECT                                      0x0
#define     QAM_SL_MODE_SLICER4DQ_ONET                                      0x4
#define     QAM_SL_MODE_SLICER4DQ_RAD                                       0x8

#define   QAM_SL_MODE_SLICER4VD__B                                          4
#define   QAM_SL_MODE_SLICER4VD__W                                          2
#define   QAM_SL_MODE_SLICER4VD__M                                          0x30
#define   QAM_SL_MODE_SLICER4VD__PRE                                        0x0
#define     QAM_SL_MODE_SLICER4VD_RECT                                      0x0
#define     QAM_SL_MODE_SLICER4VD_ONET                                      0x10
#define     QAM_SL_MODE_SLICER4VD_RAD                                       0x20

#define   QAM_SL_MODE_ROT_DIS__B                                            6
#define   QAM_SL_MODE_ROT_DIS__W                                            1
#define   QAM_SL_MODE_ROT_DIS__M                                            0x40
#define   QAM_SL_MODE_ROT_DIS__PRE                                          0x0

#define   QAM_SL_MODE_DQROT_DIS__B                                          7
#define   QAM_SL_MODE_DQROT_DIS__W                                          1
#define   QAM_SL_MODE_DQROT_DIS__M                                          0x80
#define   QAM_SL_MODE_DQROT_DIS__PRE                                        0x0

#define   QAM_SL_MODE_DFE_DIS__B                                            8
#define   QAM_SL_MODE_DFE_DIS__W                                            1
#define   QAM_SL_MODE_DFE_DIS__M                                            0x100
#define   QAM_SL_MODE_DFE_DIS__PRE                                          0x0

#define   QAM_SL_MODE_RADIUS_MIX__B                                         9
#define   QAM_SL_MODE_RADIUS_MIX__W                                         1
#define   QAM_SL_MODE_RADIUS_MIX__M                                         0x200
#define   QAM_SL_MODE_RADIUS_MIX__PRE                                       0x0

#define   QAM_SL_MODE_TILT_COMP__B                                          10
#define   QAM_SL_MODE_TILT_COMP__W                                          1
#define   QAM_SL_MODE_TILT_COMP__M                                          0x400
#define   QAM_SL_MODE_TILT_COMP__PRE                                        0x0

#define QAM_SL_K_FACTOR__A                                                  0x1430011
#define QAM_SL_K_FACTOR__W                                                  4
#define QAM_SL_K_FACTOR__M                                                  0xF
#define QAM_SL_K_FACTOR__PRE                                                0x0
#define QAM_SL_MEDIAN__A                                                    0x1430012
#define QAM_SL_MEDIAN__W                                                    14
#define QAM_SL_MEDIAN__M                                                    0x3FFF
#define QAM_SL_MEDIAN__PRE                                                  0x0

#define   QAM_SL_MEDIAN_LENGTH__B                                           0
#define   QAM_SL_MEDIAN_LENGTH__W                                           2
#define   QAM_SL_MEDIAN_LENGTH__M                                           0x3
#define   QAM_SL_MEDIAN_LENGTH__PRE                                         0x0

#define   QAM_SL_MEDIAN_CORRECT__B                                          2
#define   QAM_SL_MEDIAN_CORRECT__W                                          4
#define   QAM_SL_MEDIAN_CORRECT__M                                          0x3C
#define   QAM_SL_MEDIAN_CORRECT__PRE                                        0x0

#define   QAM_SL_MEDIAN_TOLERANCE__B                                        6
#define   QAM_SL_MEDIAN_TOLERANCE__W                                        7
#define   QAM_SL_MEDIAN_TOLERANCE__M                                        0x1FC0
#define   QAM_SL_MEDIAN_TOLERANCE__PRE                                      0x0

#define   QAM_SL_MEDIAN_FAST__B                                             13
#define   QAM_SL_MEDIAN_FAST__W                                             1
#define   QAM_SL_MEDIAN_FAST__M                                             0x2000
#define   QAM_SL_MEDIAN_FAST__PRE                                           0x0

#define QAM_SL_ALPHA__A                                                     0x1430013
#define QAM_SL_ALPHA__W                                                     3
#define QAM_SL_ALPHA__M                                                     0x7
#define QAM_SL_ALPHA__PRE                                                   0x0

#define QAM_SL_PHASELIMIT__A                                                0x1430014
#define QAM_SL_PHASELIMIT__W                                                9
#define QAM_SL_PHASELIMIT__M                                                0x1FF
#define QAM_SL_PHASELIMIT__PRE                                              0x0
#define QAM_SL_MTA_LENGTH__A                                                0x1430015
#define QAM_SL_MTA_LENGTH__W                                                2
#define QAM_SL_MTA_LENGTH__M                                                0x3
#define QAM_SL_MTA_LENGTH__PRE                                              0x1

#define   QAM_SL_MTA_LENGTH_LENGTH__B                                       0
#define   QAM_SL_MTA_LENGTH_LENGTH__W                                       2
#define   QAM_SL_MTA_LENGTH_LENGTH__M                                       0x3
#define   QAM_SL_MTA_LENGTH_LENGTH__PRE                                     0x1

#define QAM_SL_MEDIAN_ERROR__A                                              0x1430016
#define QAM_SL_MEDIAN_ERROR__W                                              10
#define QAM_SL_MEDIAN_ERROR__M                                              0x3FF
#define QAM_SL_MEDIAN_ERROR__PRE                                            0x0

#define   QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B                                 0
#define   QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W                                 10
#define   QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M                                 0x3FF
#define   QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE                               0x0

#define QAM_SL_ERR_POWER__A                                                 0x1430017
#define QAM_SL_ERR_POWER__W                                                 16
#define QAM_SL_ERR_POWER__M                                                 0xFFFF
#define QAM_SL_ERR_POWER__PRE                                               0x0

#define QAM_DQ_COMM_EXEC__A                                                 0x1440000
#define QAM_DQ_COMM_EXEC__W                                                 2
#define QAM_DQ_COMM_EXEC__M                                                 0x3
#define QAM_DQ_COMM_EXEC__PRE                                               0x0
#define   QAM_DQ_COMM_EXEC_STOP                                             0x0
#define   QAM_DQ_COMM_EXEC_ACTIVE                                           0x1
#define   QAM_DQ_COMM_EXEC_HOLD                                             0x2

#define QAM_DQ_MODE__A                                                      0x1440010
#define QAM_DQ_MODE__W                                                      5
#define QAM_DQ_MODE__M                                                      0x1F
#define QAM_DQ_MODE__PRE                                                    0x0

#define   QAM_DQ_MODE_TAPRESET__B                                           0
#define   QAM_DQ_MODE_TAPRESET__W                                           1
#define   QAM_DQ_MODE_TAPRESET__M                                           0x1
#define   QAM_DQ_MODE_TAPRESET__PRE                                         0x0
#define     QAM_DQ_MODE_TAPRESET_RST                                        0x1

#define   QAM_DQ_MODE_TAPLMS__B                                             1
#define   QAM_DQ_MODE_TAPLMS__W                                             1
#define   QAM_DQ_MODE_TAPLMS__M                                             0x2
#define   QAM_DQ_MODE_TAPLMS__PRE                                           0x0
#define     QAM_DQ_MODE_TAPLMS_UPD                                          0x2

#define   QAM_DQ_MODE_TAPDRAIN__B                                           2
#define   QAM_DQ_MODE_TAPDRAIN__W                                           1
#define   QAM_DQ_MODE_TAPDRAIN__M                                           0x4
#define   QAM_DQ_MODE_TAPDRAIN__PRE                                         0x0
#define     QAM_DQ_MODE_TAPDRAIN_DRAIN                                      0x4

#define   QAM_DQ_MODE_FB__B                                                 3
#define   QAM_DQ_MODE_FB__W                                                 2
#define   QAM_DQ_MODE_FB__M                                                 0x18
#define   QAM_DQ_MODE_FB__PRE                                               0x0
#define     QAM_DQ_MODE_FB_CMA                                              0x0
#define     QAM_DQ_MODE_FB_RADIUS                                           0x8
#define     QAM_DQ_MODE_FB_DFB                                              0x10
#define     QAM_DQ_MODE_FB_TRELLIS                                          0x18

#define QAM_DQ_MU_FACTOR__A                                                 0x1440011
#define QAM_DQ_MU_FACTOR__W                                                 3
#define QAM_DQ_MU_FACTOR__M                                                 0x7
#define QAM_DQ_MU_FACTOR__PRE                                               0x0

#define QAM_DQ_LA_FACTOR__A                                                 0x1440012
#define QAM_DQ_LA_FACTOR__W                                                 4
#define QAM_DQ_LA_FACTOR__M                                                 0xF
#define QAM_DQ_LA_FACTOR__PRE                                               0xC

#define QAM_DQ_CMA_RATIO__A                                                 0x1440013
#define QAM_DQ_CMA_RATIO__W                                                 14
#define QAM_DQ_CMA_RATIO__M                                                 0x3FFF
#define QAM_DQ_CMA_RATIO__PRE                                               0x3CF9
#define   QAM_DQ_CMA_RATIO_QPSK                                             0x2000
#define   QAM_DQ_CMA_RATIO_QAM16                                            0x34CD
#define   QAM_DQ_CMA_RATIO_QAM64                                            0x3A00
#define   QAM_DQ_CMA_RATIO_QAM256                                           0x3B4D
#define   QAM_DQ_CMA_RATIO_QAM1024                                          0x3BA0

#define QAM_DQ_QUAL_RADSEL__A                                               0x1440014
#define QAM_DQ_QUAL_RADSEL__W                                               3
#define QAM_DQ_QUAL_RADSEL__M                                               0x7
#define QAM_DQ_QUAL_RADSEL__PRE                                             0x0

#define   QAM_DQ_QUAL_RADSEL_BIT__B                                         0
#define   QAM_DQ_QUAL_RADSEL_BIT__W                                         3
#define   QAM_DQ_QUAL_RADSEL_BIT__M                                         0x7
#define   QAM_DQ_QUAL_RADSEL_BIT__PRE                                       0x0
#define     QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS                              0x0
#define     QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA                                 0x6

#define QAM_DQ_QUAL_ENA__A                                                  0x1440015
#define QAM_DQ_QUAL_ENA__W                                                  1
#define QAM_DQ_QUAL_ENA__M                                                  0x1
#define QAM_DQ_QUAL_ENA__PRE                                                0x0

#define   QAM_DQ_QUAL_ENA_ENA__B                                            0
#define   QAM_DQ_QUAL_ENA_ENA__W                                            1
#define   QAM_DQ_QUAL_ENA_ENA__M                                            0x1
#define   QAM_DQ_QUAL_ENA_ENA__PRE                                          0x0
#define     QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING                              0x1

#define QAM_DQ_QUAL_FUN0__A                                                 0x1440018
#define QAM_DQ_QUAL_FUN0__W                                                 6
#define QAM_DQ_QUAL_FUN0__M                                                 0x3F
#define QAM_DQ_QUAL_FUN0__PRE                                               0x4

#define   QAM_DQ_QUAL_FUN0_BIT__B                                           0
#define   QAM_DQ_QUAL_FUN0_BIT__W                                           6
#define   QAM_DQ_QUAL_FUN0_BIT__M                                           0x3F
#define   QAM_DQ_QUAL_FUN0_BIT__PRE                                         0x4

#define QAM_DQ_QUAL_FUN1__A                                                 0x1440019
#define QAM_DQ_QUAL_FUN1__W                                                 6
#define QAM_DQ_QUAL_FUN1__M                                                 0x3F
#define QAM_DQ_QUAL_FUN1__PRE                                               0x4

#define   QAM_DQ_QUAL_FUN1_BIT__B                                           0
#define   QAM_DQ_QUAL_FUN1_BIT__W                                           6
#define   QAM_DQ_QUAL_FUN1_BIT__M                                           0x3F
#define   QAM_DQ_QUAL_FUN1_BIT__PRE                                         0x4

#define QAM_DQ_QUAL_FUN2__A                                                 0x144001A
#define QAM_DQ_QUAL_FUN2__W                                                 6
#define QAM_DQ_QUAL_FUN2__M                                                 0x3F
#define QAM_DQ_QUAL_FUN2__PRE                                               0x4

#define   QAM_DQ_QUAL_FUN2_BIT__B                                           0
#define   QAM_DQ_QUAL_FUN2_BIT__W                                           6
#define   QAM_DQ_QUAL_FUN2_BIT__M                                           0x3F
#define   QAM_DQ_QUAL_FUN2_BIT__PRE                                         0x4

#define QAM_DQ_QUAL_FUN3__A                                                 0x144001B
#define QAM_DQ_QUAL_FUN3__W                                                 6
#define QAM_DQ_QUAL_FUN3__M                                                 0x3F
#define QAM_DQ_QUAL_FUN3__PRE                                               0x4

#define   QAM_DQ_QUAL_FUN3_BIT__B                                           0
#define   QAM_DQ_QUAL_FUN3_BIT__W                                           6
#define   QAM_DQ_QUAL_FUN3_BIT__M                                           0x3F
#define   QAM_DQ_QUAL_FUN3_BIT__PRE                                         0x4

#define QAM_DQ_QUAL_FUN4__A                                                 0x144001C
#define QAM_DQ_QUAL_FUN4__W                                                 6
#define QAM_DQ_QUAL_FUN4__M                                                 0x3F
#define QAM_DQ_QUAL_FUN4__PRE                                               0x6

#define   QAM_DQ_QUAL_FUN4_BIT__B                                           0
#define   QAM_DQ_QUAL_FUN4_BIT__W                                           6
#define   QAM_DQ_QUAL_FUN4_BIT__M                                           0x3F
#define   QAM_DQ_QUAL_FUN4_BIT__PRE                                         0x6

#define QAM_DQ_QUAL_FUN5__A                                                 0x144001D
#define QAM_DQ_QUAL_FUN5__W                                                 6
#define QAM_DQ_QUAL_FUN5__M                                                 0x3F
#define QAM_DQ_QUAL_FUN5__PRE                                               0x6

#define   QAM_DQ_QUAL_FUN5_BIT__B                                           0
#define   QAM_DQ_QUAL_FUN5_BIT__W                                           6
#define   QAM_DQ_QUAL_FUN5_BIT__M                                           0x3F
#define   QAM_DQ_QUAL_FUN5_BIT__PRE                                         0x6

#define QAM_DQ_RAW_LIM__A                                                   0x144001E
#define QAM_DQ_RAW_LIM__W                                                   5
#define QAM_DQ_RAW_LIM__M                                                   0x1F
#define QAM_DQ_RAW_LIM__PRE                                                 0x1F

#define   QAM_DQ_RAW_LIM_BIT__B                                             0
#define   QAM_DQ_RAW_LIM_BIT__W                                             5
#define   QAM_DQ_RAW_LIM_BIT__M                                             0x1F
#define   QAM_DQ_RAW_LIM_BIT__PRE                                           0x1F

#define QAM_DQ_TAP_RE_EL0__A                                                0x1440020
#define QAM_DQ_TAP_RE_EL0__W                                                12
#define QAM_DQ_TAP_RE_EL0__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL0__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL0_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL0_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL0_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL0_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL0__A                                                0x1440021
#define QAM_DQ_TAP_IM_EL0__W                                                12
#define QAM_DQ_TAP_IM_EL0__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL0__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL0_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL0_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL0_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL0_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL1__A                                                0x1440022
#define QAM_DQ_TAP_RE_EL1__W                                                12
#define QAM_DQ_TAP_RE_EL1__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL1__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL1_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL1_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL1_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL1_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL1__A                                                0x1440023
#define QAM_DQ_TAP_IM_EL1__W                                                12
#define QAM_DQ_TAP_IM_EL1__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL1__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL1_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL1_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL1_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL1_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL2__A                                                0x1440024
#define QAM_DQ_TAP_RE_EL2__W                                                12
#define QAM_DQ_TAP_RE_EL2__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL2__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL2_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL2_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL2_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL2_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL2__A                                                0x1440025
#define QAM_DQ_TAP_IM_EL2__W                                                12
#define QAM_DQ_TAP_IM_EL2__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL2__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL2_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL2_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL2_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL2_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL3__A                                                0x1440026
#define QAM_DQ_TAP_RE_EL3__W                                                12
#define QAM_DQ_TAP_RE_EL3__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL3__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL3_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL3_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL3_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL3_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL3__A                                                0x1440027
#define QAM_DQ_TAP_IM_EL3__W                                                12
#define QAM_DQ_TAP_IM_EL3__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL3__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL3_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL3_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL3_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL3_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL4__A                                                0x1440028
#define QAM_DQ_TAP_RE_EL4__W                                                12
#define QAM_DQ_TAP_RE_EL4__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL4__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL4_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL4_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL4_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL4_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL4__A                                                0x1440029
#define QAM_DQ_TAP_IM_EL4__W                                                12
#define QAM_DQ_TAP_IM_EL4__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL4__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL4_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL4_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL4_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL4_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL5__A                                                0x144002A
#define QAM_DQ_TAP_RE_EL5__W                                                12
#define QAM_DQ_TAP_RE_EL5__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL5__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL5_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL5_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL5_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL5_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL5__A                                                0x144002B
#define QAM_DQ_TAP_IM_EL5__W                                                12
#define QAM_DQ_TAP_IM_EL5__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL5__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL5_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL5_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL5_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL5_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL6__A                                                0x144002C
#define QAM_DQ_TAP_RE_EL6__W                                                12
#define QAM_DQ_TAP_RE_EL6__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL6__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL6_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL6_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL6_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL6_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL6__A                                                0x144002D
#define QAM_DQ_TAP_IM_EL6__W                                                12
#define QAM_DQ_TAP_IM_EL6__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL6__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL6_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL6_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL6_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL6_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL7__A                                                0x144002E
#define QAM_DQ_TAP_RE_EL7__W                                                12
#define QAM_DQ_TAP_RE_EL7__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL7__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL7_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL7_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL7_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL7_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL7__A                                                0x144002F
#define QAM_DQ_TAP_IM_EL7__W                                                12
#define QAM_DQ_TAP_IM_EL7__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL7__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL7_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL7_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL7_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL7_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL8__A                                                0x1440030
#define QAM_DQ_TAP_RE_EL8__W                                                12
#define QAM_DQ_TAP_RE_EL8__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL8__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL8_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL8_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL8_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL8_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL8__A                                                0x1440031
#define QAM_DQ_TAP_IM_EL8__W                                                12
#define QAM_DQ_TAP_IM_EL8__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL8__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL8_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL8_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL8_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL8_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL9__A                                                0x1440032
#define QAM_DQ_TAP_RE_EL9__W                                                12
#define QAM_DQ_TAP_RE_EL9__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL9__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL9_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL9_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL9_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL9_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL9__A                                                0x1440033
#define QAM_DQ_TAP_IM_EL9__W                                                12
#define QAM_DQ_TAP_IM_EL9__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL9__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL9_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL9_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL9_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL9_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL10__A                                               0x1440034
#define QAM_DQ_TAP_RE_EL10__W                                               12
#define QAM_DQ_TAP_RE_EL10__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL10__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL10_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL10_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL10_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL10_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL10__A                                               0x1440035
#define QAM_DQ_TAP_IM_EL10__W                                               12
#define QAM_DQ_TAP_IM_EL10__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL10__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL10_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL10_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL10_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL10_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL11__A                                               0x1440036
#define QAM_DQ_TAP_RE_EL11__W                                               12
#define QAM_DQ_TAP_RE_EL11__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL11__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL11_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL11_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL11_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL11_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL11__A                                               0x1440037
#define QAM_DQ_TAP_IM_EL11__W                                               12
#define QAM_DQ_TAP_IM_EL11__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL11__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL11_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL11_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL11_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL11_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL12__A                                               0x1440038
#define QAM_DQ_TAP_RE_EL12__W                                               12
#define QAM_DQ_TAP_RE_EL12__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL12__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL12_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL12_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL12_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL12_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL12__A                                               0x1440039
#define QAM_DQ_TAP_IM_EL12__W                                               12
#define QAM_DQ_TAP_IM_EL12__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL12__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL12_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL12_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL12_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL12_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL13__A                                               0x144003A
#define QAM_DQ_TAP_RE_EL13__W                                               12
#define QAM_DQ_TAP_RE_EL13__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL13__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL13_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL13_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL13_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL13_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL13__A                                               0x144003B
#define QAM_DQ_TAP_IM_EL13__W                                               12
#define QAM_DQ_TAP_IM_EL13__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL13__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL13_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL13_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL13_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL13_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL14__A                                               0x144003C
#define QAM_DQ_TAP_RE_EL14__W                                               12
#define QAM_DQ_TAP_RE_EL14__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL14__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL14_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL14_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL14_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL14_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL14__A                                               0x144003D
#define QAM_DQ_TAP_IM_EL14__W                                               12
#define QAM_DQ_TAP_IM_EL14__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL14__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL14_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL14_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL14_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL14_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL15__A                                               0x144003E
#define QAM_DQ_TAP_RE_EL15__W                                               12
#define QAM_DQ_TAP_RE_EL15__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL15__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL15_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL15_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL15_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL15_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL15__A                                               0x144003F
#define QAM_DQ_TAP_IM_EL15__W                                               12
#define QAM_DQ_TAP_IM_EL15__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL15__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL15_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL15_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL15_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL15_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL16__A                                               0x1440040
#define QAM_DQ_TAP_RE_EL16__W                                               12
#define QAM_DQ_TAP_RE_EL16__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL16__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL16_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL16_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL16_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL16_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL16__A                                               0x1440041
#define QAM_DQ_TAP_IM_EL16__W                                               12
#define QAM_DQ_TAP_IM_EL16__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL16__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL16_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL16_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL16_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL16_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL17__A                                               0x1440042
#define QAM_DQ_TAP_RE_EL17__W                                               12
#define QAM_DQ_TAP_RE_EL17__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL17__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL17_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL17_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL17_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL17_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL17__A                                               0x1440043
#define QAM_DQ_TAP_IM_EL17__W                                               12
#define QAM_DQ_TAP_IM_EL17__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL17__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL17_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL17_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL17_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL17_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL18__A                                               0x1440044
#define QAM_DQ_TAP_RE_EL18__W                                               12
#define QAM_DQ_TAP_RE_EL18__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL18__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL18_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL18_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL18_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL18_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL18__A                                               0x1440045
#define QAM_DQ_TAP_IM_EL18__W                                               12
#define QAM_DQ_TAP_IM_EL18__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL18__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL18_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL18_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL18_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL18_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL19__A                                               0x1440046
#define QAM_DQ_TAP_RE_EL19__W                                               12
#define QAM_DQ_TAP_RE_EL19__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL19__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL19_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL19_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL19_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL19_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL19__A                                               0x1440047
#define QAM_DQ_TAP_IM_EL19__W                                               12
#define QAM_DQ_TAP_IM_EL19__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL19__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL19_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL19_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL19_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL19_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL20__A                                               0x1440048
#define QAM_DQ_TAP_RE_EL20__W                                               12
#define QAM_DQ_TAP_RE_EL20__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL20__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL20_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL20_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL20_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL20_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL20__A                                               0x1440049
#define QAM_DQ_TAP_IM_EL20__W                                               12
#define QAM_DQ_TAP_IM_EL20__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL20__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL20_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL20_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL20_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL20_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL21__A                                               0x144004A
#define QAM_DQ_TAP_RE_EL21__W                                               12
#define QAM_DQ_TAP_RE_EL21__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL21__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL21_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL21_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL21_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL21_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL21__A                                               0x144004B
#define QAM_DQ_TAP_IM_EL21__W                                               12
#define QAM_DQ_TAP_IM_EL21__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL21__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL21_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL21_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL21_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL21_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL22__A                                               0x144004C
#define QAM_DQ_TAP_RE_EL22__W                                               12
#define QAM_DQ_TAP_RE_EL22__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL22__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL22_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL22_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL22_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL22_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL22__A                                               0x144004D
#define QAM_DQ_TAP_IM_EL22__W                                               12
#define QAM_DQ_TAP_IM_EL22__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL22__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL22_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL22_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL22_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL22_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL23__A                                               0x144004E
#define QAM_DQ_TAP_RE_EL23__W                                               12
#define QAM_DQ_TAP_RE_EL23__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL23__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL23_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL23_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL23_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL23_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL23__A                                               0x144004F
#define QAM_DQ_TAP_IM_EL23__W                                               12
#define QAM_DQ_TAP_IM_EL23__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL23__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL23_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL23_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL23_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL23_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL24__A                                               0x1440050
#define QAM_DQ_TAP_RE_EL24__W                                               12
#define QAM_DQ_TAP_RE_EL24__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL24__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL24_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL24_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL24_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL24_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL24__A                                               0x1440051
#define QAM_DQ_TAP_IM_EL24__W                                               12
#define QAM_DQ_TAP_IM_EL24__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL24__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL24_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL24_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL24_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL24_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL25__A                                               0x1440052
#define QAM_DQ_TAP_RE_EL25__W                                               12
#define QAM_DQ_TAP_RE_EL25__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL25__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL25_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL25_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL25_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL25_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL25__A                                               0x1440053
#define QAM_DQ_TAP_IM_EL25__W                                               12
#define QAM_DQ_TAP_IM_EL25__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL25__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL25_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL25_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL25_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL25_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL26__A                                               0x1440054
#define QAM_DQ_TAP_RE_EL26__W                                               12
#define QAM_DQ_TAP_RE_EL26__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL26__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL26_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL26_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL26_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL26_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL26__A                                               0x1440055
#define QAM_DQ_TAP_IM_EL26__W                                               12
#define QAM_DQ_TAP_IM_EL26__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL26__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL26_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL26_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL26_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL26_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL27__A                                               0x1440056
#define QAM_DQ_TAP_RE_EL27__W                                               12
#define QAM_DQ_TAP_RE_EL27__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL27__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL27_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL27_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL27_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL27_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL27__A                                               0x1440057
#define QAM_DQ_TAP_IM_EL27__W                                               12
#define QAM_DQ_TAP_IM_EL27__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL27__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL27_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL27_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL27_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL27_TAP__PRE                                       0x2

#define QAM_LC_COMM_EXEC__A                                                 0x1450000
#define QAM_LC_COMM_EXEC__W                                                 2
#define QAM_LC_COMM_EXEC__M                                                 0x3
#define QAM_LC_COMM_EXEC__PRE                                               0x0
#define   QAM_LC_COMM_EXEC_STOP                                             0x0
#define   QAM_LC_COMM_EXEC_ACTIVE                                           0x1
#define   QAM_LC_COMM_EXEC_HOLD                                             0x2

#define QAM_LC_COMM_MB__A                                                   0x1450002
#define QAM_LC_COMM_MB__W                                                   2
#define QAM_LC_COMM_MB__M                                                   0x3
#define QAM_LC_COMM_MB__PRE                                                 0x0
#define   QAM_LC_COMM_MB_CTL__B                                             0
#define   QAM_LC_COMM_MB_CTL__W                                             1
#define   QAM_LC_COMM_MB_CTL__M                                             0x1
#define   QAM_LC_COMM_MB_CTL__PRE                                           0x0
#define     QAM_LC_COMM_MB_CTL_OFF                                          0x0
#define     QAM_LC_COMM_MB_CTL_ON                                           0x1
#define   QAM_LC_COMM_MB_OBS__B                                             1
#define   QAM_LC_COMM_MB_OBS__W                                             1
#define   QAM_LC_COMM_MB_OBS__M                                             0x2
#define   QAM_LC_COMM_MB_OBS__PRE                                           0x0
#define     QAM_LC_COMM_MB_OBS_OFF                                          0x0
#define     QAM_LC_COMM_MB_OBS_ON                                           0x2

#define QAM_LC_COMM_INT_REQ__A                                              0x1450003
#define QAM_LC_COMM_INT_REQ__W                                              1
#define QAM_LC_COMM_INT_REQ__M                                              0x1
#define QAM_LC_COMM_INT_REQ__PRE                                            0x0
#define QAM_LC_COMM_INT_STA__A                                              0x1450005
#define QAM_LC_COMM_INT_STA__W                                              3
#define QAM_LC_COMM_INT_STA__M                                              0x7
#define QAM_LC_COMM_INT_STA__PRE                                            0x0

#define   QAM_LC_COMM_INT_STA_READY__B                                      0
#define   QAM_LC_COMM_INT_STA_READY__W                                      1
#define   QAM_LC_COMM_INT_STA_READY__M                                      0x1
#define   QAM_LC_COMM_INT_STA_READY__PRE                                    0x0

#define   QAM_LC_COMM_INT_STA_OVERFLOW__B                                   1
#define   QAM_LC_COMM_INT_STA_OVERFLOW__W                                   1
#define   QAM_LC_COMM_INT_STA_OVERFLOW__M                                   0x2
#define   QAM_LC_COMM_INT_STA_OVERFLOW__PRE                                 0x0

#define   QAM_LC_COMM_INT_STA_FREQ_WRAP__B                                  2
#define   QAM_LC_COMM_INT_STA_FREQ_WRAP__W                                  1
#define   QAM_LC_COMM_INT_STA_FREQ_WRAP__M                                  0x4
#define   QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE                                0x0

#define QAM_LC_COMM_INT_MSK__A                                              0x1450006
#define QAM_LC_COMM_INT_MSK__W                                              3
#define QAM_LC_COMM_INT_MSK__M                                              0x7
#define QAM_LC_COMM_INT_MSK__PRE                                            0x0
#define   QAM_LC_COMM_INT_MSK_READY__B                                      0
#define   QAM_LC_COMM_INT_MSK_READY__W                                      1
#define   QAM_LC_COMM_INT_MSK_READY__M                                      0x1
#define   QAM_LC_COMM_INT_MSK_READY__PRE                                    0x0
#define   QAM_LC_COMM_INT_MSK_OVERFLOW__B                                   1
#define   QAM_LC_COMM_INT_MSK_OVERFLOW__W                                   1
#define   QAM_LC_COMM_INT_MSK_OVERFLOW__M                                   0x2
#define   QAM_LC_COMM_INT_MSK_OVERFLOW__PRE                                 0x0
#define   QAM_LC_COMM_INT_MSK_FREQ_WRAP__B                                  2
#define   QAM_LC_COMM_INT_MSK_FREQ_WRAP__W                                  1
#define   QAM_LC_COMM_INT_MSK_FREQ_WRAP__M                                  0x4
#define   QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE                                0x0

#define QAM_LC_COMM_INT_STM__A                                              0x1450007
#define QAM_LC_COMM_INT_STM__W                                              3
#define QAM_LC_COMM_INT_STM__M                                              0x7
#define QAM_LC_COMM_INT_STM__PRE                                            0x0
#define   QAM_LC_COMM_INT_STM_READY__B                                      0
#define   QAM_LC_COMM_INT_STM_READY__W                                      1
#define   QAM_LC_COMM_INT_STM_READY__M                                      0x1
#define   QAM_LC_COMM_INT_STM_READY__PRE                                    0x0
#define   QAM_LC_COMM_INT_STM_OVERFLOW__B                                   1
#define   QAM_LC_COMM_INT_STM_OVERFLOW__W                                   1
#define   QAM_LC_COMM_INT_STM_OVERFLOW__M                                   0x2
#define   QAM_LC_COMM_INT_STM_OVERFLOW__PRE                                 0x0
#define   QAM_LC_COMM_INT_STM_FREQ_WRAP__B                                  2
#define   QAM_LC_COMM_INT_STM_FREQ_WRAP__W                                  1
#define   QAM_LC_COMM_INT_STM_FREQ_WRAP__M                                  0x4
#define   QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE                                0x0

#define QAM_LC_MODE__A                                                      0x1450010
#define QAM_LC_MODE__W                                                      3
#define QAM_LC_MODE__M                                                      0x7
#define QAM_LC_MODE__PRE                                                    0x7

#define   QAM_LC_MODE_ENABLE_A__B                                           0
#define   QAM_LC_MODE_ENABLE_A__W                                           1
#define   QAM_LC_MODE_ENABLE_A__M                                           0x1
#define   QAM_LC_MODE_ENABLE_A__PRE                                         0x1

#define   QAM_LC_MODE_ENABLE_F__B                                           1
#define   QAM_LC_MODE_ENABLE_F__W                                           1
#define   QAM_LC_MODE_ENABLE_F__M                                           0x2
#define   QAM_LC_MODE_ENABLE_F__PRE                                         0x2

#define   QAM_LC_MODE_ENABLE_R__B                                           2
#define   QAM_LC_MODE_ENABLE_R__W                                           1
#define   QAM_LC_MODE_ENABLE_R__M                                           0x4
#define   QAM_LC_MODE_ENABLE_R__PRE                                         0x4

#define QAM_LC_CA__A                                                        0x1450011
#define QAM_LC_CA__W                                                        6
#define QAM_LC_CA__M                                                        0x3F
#define QAM_LC_CA__PRE                                                      0x28

#define   QAM_LC_CA_COEF__B                                                 0
#define   QAM_LC_CA_COEF__W                                                 6
#define   QAM_LC_CA_COEF__M                                                 0x3F
#define   QAM_LC_CA_COEF__PRE                                               0x28

#define QAM_LC_CF__A                                                        0x1450012
#define QAM_LC_CF__W                                                        8
#define QAM_LC_CF__M                                                        0xFF
#define QAM_LC_CF__PRE                                                      0x8C

#define   QAM_LC_CF_COEF__B                                                 0
#define   QAM_LC_CF_COEF__W                                                 8
#define   QAM_LC_CF_COEF__M                                                 0xFF
#define   QAM_LC_CF_COEF__PRE                                               0x8C

#define QAM_LC_CF1__A                                                       0x1450013
#define QAM_LC_CF1__W                                                       8
#define QAM_LC_CF1__M                                                       0xFF
#define QAM_LC_CF1__PRE                                                     0x1E

#define   QAM_LC_CF1_COEF__B                                                0
#define   QAM_LC_CF1_COEF__W                                                8
#define   QAM_LC_CF1_COEF__M                                                0xFF
#define   QAM_LC_CF1_COEF__PRE                                              0x1E

#define QAM_LC_CP__A                                                        0x1450014
#define QAM_LC_CP__W                                                        8
#define QAM_LC_CP__M                                                        0xFF
#define QAM_LC_CP__PRE                                                      0x78

#define   QAM_LC_CP_COEF__B                                                 0
#define   QAM_LC_CP_COEF__W                                                 8
#define   QAM_LC_CP_COEF__M                                                 0xFF
#define   QAM_LC_CP_COEF__PRE                                               0x78

#define QAM_LC_CI__A                                                        0x1450015
#define QAM_LC_CI__W                                                        8
#define QAM_LC_CI__M                                                        0xFF
#define QAM_LC_CI__PRE                                                      0x46

#define   QAM_LC_CI_COEF__B                                                 0
#define   QAM_LC_CI_COEF__W                                                 8
#define   QAM_LC_CI_COEF__M                                                 0xFF
#define   QAM_LC_CI_COEF__PRE                                               0x46

#define QAM_LC_EP__A                                                        0x1450016
#define QAM_LC_EP__W                                                        6
#define QAM_LC_EP__M                                                        0x3F
#define QAM_LC_EP__PRE                                                      0x0

#define   QAM_LC_EP_COEF__B                                                 0
#define   QAM_LC_EP_COEF__W                                                 6
#define   QAM_LC_EP_COEF__M                                                 0x3F
#define   QAM_LC_EP_COEF__PRE                                               0x0

#define QAM_LC_EI__A                                                        0x1450017
#define QAM_LC_EI__W                                                        6
#define QAM_LC_EI__M                                                        0x3F
#define QAM_LC_EI__PRE                                                      0x0

#define   QAM_LC_EI_COEF__B                                                 0
#define   QAM_LC_EI_COEF__W                                                 6
#define   QAM_LC_EI_COEF__M                                                 0x3F
#define   QAM_LC_EI_COEF__PRE                                               0x0

#define QAM_LC_QUAL_TAB0__A                                                 0x1450018
#define QAM_LC_QUAL_TAB0__W                                                 5
#define QAM_LC_QUAL_TAB0__M                                                 0x1F
#define QAM_LC_QUAL_TAB0__PRE                                               0x1

#define   QAM_LC_QUAL_TAB0_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB0_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB0_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB0_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB1__A                                                 0x1450019
#define QAM_LC_QUAL_TAB1__W                                                 5
#define QAM_LC_QUAL_TAB1__M                                                 0x1F
#define QAM_LC_QUAL_TAB1__PRE                                               0x1

#define   QAM_LC_QUAL_TAB1_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB1_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB1_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB1_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB2__A                                                 0x145001A
#define QAM_LC_QUAL_TAB2__W                                                 5
#define QAM_LC_QUAL_TAB2__M                                                 0x1F
#define QAM_LC_QUAL_TAB2__PRE                                               0x1

#define   QAM_LC_QUAL_TAB2_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB2_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB2_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB2_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB3__A                                                 0x145001B
#define QAM_LC_QUAL_TAB3__W                                                 5
#define QAM_LC_QUAL_TAB3__M                                                 0x1F
#define QAM_LC_QUAL_TAB3__PRE                                               0x1

#define   QAM_LC_QUAL_TAB3_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB3_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB3_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB3_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB4__A                                                 0x145001C
#define QAM_LC_QUAL_TAB4__W                                                 5
#define QAM_LC_QUAL_TAB4__M                                                 0x1F
#define QAM_LC_QUAL_TAB4__PRE                                               0x1

#define   QAM_LC_QUAL_TAB4_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB4_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB4_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB4_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB5__A                                                 0x145001D
#define QAM_LC_QUAL_TAB5__W                                                 5
#define QAM_LC_QUAL_TAB5__M                                                 0x1F
#define QAM_LC_QUAL_TAB5__PRE                                               0x1

#define   QAM_LC_QUAL_TAB5_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB5_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB5_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB5_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB6__A                                                 0x145001E
#define QAM_LC_QUAL_TAB6__W                                                 5
#define QAM_LC_QUAL_TAB6__M                                                 0x1F
#define QAM_LC_QUAL_TAB6__PRE                                               0x1

#define   QAM_LC_QUAL_TAB6_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB6_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB6_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB6_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB8__A                                                 0x145001F
#define QAM_LC_QUAL_TAB8__W                                                 5
#define QAM_LC_QUAL_TAB8__M                                                 0x1F
#define QAM_LC_QUAL_TAB8__PRE                                               0x1

#define   QAM_LC_QUAL_TAB8_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB8_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB8_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB8_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB9__A                                                 0x1450020
#define QAM_LC_QUAL_TAB9__W                                                 5
#define QAM_LC_QUAL_TAB9__M                                                 0x1F
#define QAM_LC_QUAL_TAB9__PRE                                               0x1

#define   QAM_LC_QUAL_TAB9_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB9_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB9_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB9_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB10__A                                                0x1450021
#define QAM_LC_QUAL_TAB10__W                                                5
#define QAM_LC_QUAL_TAB10__M                                                0x1F
#define QAM_LC_QUAL_TAB10__PRE                                              0x1

#define   QAM_LC_QUAL_TAB10_VALUE__B                                        0
#define   QAM_LC_QUAL_TAB10_VALUE__W                                        5
#define   QAM_LC_QUAL_TAB10_VALUE__M                                        0x1F
#define   QAM_LC_QUAL_TAB10_VALUE__PRE                                      0x1

#define QAM_LC_QUAL_TAB12__A                                                0x1450022
#define QAM_LC_QUAL_TAB12__W                                                5
#define QAM_LC_QUAL_TAB12__M                                                0x1F
#define QAM_LC_QUAL_TAB12__PRE                                              0x1

#define   QAM_LC_QUAL_TAB12_VALUE__B                                        0
#define   QAM_LC_QUAL_TAB12_VALUE__W                                        5
#define   QAM_LC_QUAL_TAB12_VALUE__M                                        0x1F
#define   QAM_LC_QUAL_TAB12_VALUE__PRE                                      0x1

#define QAM_LC_QUAL_TAB15__A                                                0x1450023
#define QAM_LC_QUAL_TAB15__W                                                5
#define QAM_LC_QUAL_TAB15__M                                                0x1F
#define QAM_LC_QUAL_TAB15__PRE                                              0x1

#define   QAM_LC_QUAL_TAB15_VALUE__B                                        0
#define   QAM_LC_QUAL_TAB15_VALUE__W                                        5
#define   QAM_LC_QUAL_TAB15_VALUE__M                                        0x1F
#define   QAM_LC_QUAL_TAB15_VALUE__PRE                                      0x1

#define QAM_LC_QUAL_TAB16__A                                                0x1450024
#define QAM_LC_QUAL_TAB16__W                                                5
#define QAM_LC_QUAL_TAB16__M                                                0x1F
#define QAM_LC_QUAL_TAB16__PRE                                              0x1

#define   QAM_LC_QUAL_TAB16_VALUE__B                                        0
#define   QAM_LC_QUAL_TAB16_VALUE__W                                        5
#define   QAM_LC_QUAL_TAB16_VALUE__M                                        0x1F
#define   QAM_LC_QUAL_TAB16_VALUE__PRE                                      0x1

#define QAM_LC_QUAL_TAB20__A                                                0x1450025
#define QAM_LC_QUAL_TAB20__W                                                5
#define QAM_LC_QUAL_TAB20__M                                                0x1F
#define QAM_LC_QUAL_TAB20__PRE                                              0x1

#define   QAM_LC_QUAL_TAB20_VALUE__B                                        0
#define   QAM_LC_QUAL_TAB20_VALUE__W                                        5
#define   QAM_LC_QUAL_TAB20_VALUE__M                                        0x1F
#define   QAM_LC_QUAL_TAB20_VALUE__PRE                                      0x1

#define QAM_LC_QUAL_TAB25__A                                                0x1450026
#define QAM_LC_QUAL_TAB25__W                                                5
#define QAM_LC_QUAL_TAB25__M                                                0x1F
#define QAM_LC_QUAL_TAB25__PRE                                              0x1

#define   QAM_LC_QUAL_TAB25_VALUE__B                                        0
#define   QAM_LC_QUAL_TAB25_VALUE__W                                        5
#define   QAM_LC_QUAL_TAB25_VALUE__M                                        0x1F
#define   QAM_LC_QUAL_TAB25_VALUE__PRE                                      0x1

#define QAM_LC_EQ_TIMING__A                                                 0x1450027
#define QAM_LC_EQ_TIMING__W                                                 10
#define QAM_LC_EQ_TIMING__M                                                 0x3FF
#define QAM_LC_EQ_TIMING__PRE                                               0x0

#define   QAM_LC_EQ_TIMING_OFFS__B                                          0
#define   QAM_LC_EQ_TIMING_OFFS__W                                          10
#define   QAM_LC_EQ_TIMING_OFFS__M                                          0x3FF
#define   QAM_LC_EQ_TIMING_OFFS__PRE                                        0x0

#define QAM_LC_LPF_FACTORP__A                                               0x1450028
#define QAM_LC_LPF_FACTORP__W                                               3
#define QAM_LC_LPF_FACTORP__M                                               0x7
#define QAM_LC_LPF_FACTORP__PRE                                             0x3

#define   QAM_LC_LPF_FACTORP_FACTOR__B                                      0
#define   QAM_LC_LPF_FACTORP_FACTOR__W                                      3
#define   QAM_LC_LPF_FACTORP_FACTOR__M                                      0x7
#define   QAM_LC_LPF_FACTORP_FACTOR__PRE                                    0x3

#define QAM_LC_LPF_FACTORI__A                                               0x1450029
#define QAM_LC_LPF_FACTORI__W                                               3
#define QAM_LC_LPF_FACTORI__M                                               0x7
#define QAM_LC_LPF_FACTORI__PRE                                             0x3

#define   QAM_LC_LPF_FACTORI_FACTOR__B                                      0
#define   QAM_LC_LPF_FACTORI_FACTOR__W                                      3
#define   QAM_LC_LPF_FACTORI_FACTOR__M                                      0x7
#define   QAM_LC_LPF_FACTORI_FACTOR__PRE                                    0x3

#define QAM_LC_RATE_LIMIT__A                                                0x145002A
#define QAM_LC_RATE_LIMIT__W                                                2
#define QAM_LC_RATE_LIMIT__M                                                0x3
#define QAM_LC_RATE_LIMIT__PRE                                              0x3

#define   QAM_LC_RATE_LIMIT_LIMIT__B                                        0
#define   QAM_LC_RATE_LIMIT_LIMIT__W                                        2
#define   QAM_LC_RATE_LIMIT_LIMIT__M                                        0x3
#define   QAM_LC_RATE_LIMIT_LIMIT__PRE                                      0x3

#define QAM_LC_SYMBOL_FREQ__A                                               0x145002B
#define QAM_LC_SYMBOL_FREQ__W                                               10
#define QAM_LC_SYMBOL_FREQ__M                                               0x3FF
#define QAM_LC_SYMBOL_FREQ__PRE                                             0x199

#define   QAM_LC_SYMBOL_FREQ_FREQ__B                                        0
#define   QAM_LC_SYMBOL_FREQ_FREQ__W                                        10
#define   QAM_LC_SYMBOL_FREQ_FREQ__M                                        0x3FF
#define   QAM_LC_SYMBOL_FREQ_FREQ__PRE                                      0x199
#define     QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_64                                0x197
#define     QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256                               0x1B2

#define QAM_LC_MTA_LENGTH__A                                                0x145002C
#define QAM_LC_MTA_LENGTH__W                                                2
#define QAM_LC_MTA_LENGTH__M                                                0x3
#define QAM_LC_MTA_LENGTH__PRE                                              0x2

#define   QAM_LC_MTA_LENGTH_LENGTH__B                                       0
#define   QAM_LC_MTA_LENGTH_LENGTH__W                                       2
#define   QAM_LC_MTA_LENGTH_LENGTH__M                                       0x3
#define   QAM_LC_MTA_LENGTH_LENGTH__PRE                                     0x2

#define QAM_LC_AMP_ACCU__A                                                  0x145002D
#define QAM_LC_AMP_ACCU__W                                                  14
#define QAM_LC_AMP_ACCU__M                                                  0x3FFF
#define QAM_LC_AMP_ACCU__PRE                                                0x600

#define   QAM_LC_AMP_ACCU_ACCU__B                                           0
#define   QAM_LC_AMP_ACCU_ACCU__W                                           14
#define   QAM_LC_AMP_ACCU_ACCU__M                                           0x3FFF
#define   QAM_LC_AMP_ACCU_ACCU__PRE                                         0x600

#define QAM_LC_FREQ_ACCU__A                                                 0x145002E
#define QAM_LC_FREQ_ACCU__W                                                 10
#define QAM_LC_FREQ_ACCU__M                                                 0x3FF
#define QAM_LC_FREQ_ACCU__PRE                                               0x0

#define   QAM_LC_FREQ_ACCU_ACCU__B                                          0
#define   QAM_LC_FREQ_ACCU_ACCU__W                                          10
#define   QAM_LC_FREQ_ACCU_ACCU__M                                          0x3FF
#define   QAM_LC_FREQ_ACCU_ACCU__PRE                                        0x0

#define QAM_LC_RATE_ACCU__A                                                 0x145002F
#define QAM_LC_RATE_ACCU__W                                                 10
#define QAM_LC_RATE_ACCU__M                                                 0x3FF
#define QAM_LC_RATE_ACCU__PRE                                               0x0

#define   QAM_LC_RATE_ACCU_ACCU__B                                          0
#define   QAM_LC_RATE_ACCU_ACCU__W                                          10
#define   QAM_LC_RATE_ACCU_ACCU__M                                          0x3FF
#define   QAM_LC_RATE_ACCU_ACCU__PRE                                        0x0

#define QAM_LC_AMPLITUDE__A                                                 0x1450030
#define QAM_LC_AMPLITUDE__W                                                 10
#define QAM_LC_AMPLITUDE__M                                                 0x3FF
#define QAM_LC_AMPLITUDE__PRE                                               0x0

#define   QAM_LC_AMPLITUDE_SIZE__B                                          0
#define   QAM_LC_AMPLITUDE_SIZE__W                                          10
#define   QAM_LC_AMPLITUDE_SIZE__M                                          0x3FF
#define   QAM_LC_AMPLITUDE_SIZE__PRE                                        0x0

#define QAM_LC_RAD_ERROR__A                                                 0x1450031
#define QAM_LC_RAD_ERROR__W                                                 10
#define QAM_LC_RAD_ERROR__M                                                 0x3FF
#define QAM_LC_RAD_ERROR__PRE                                               0x0

#define   QAM_LC_RAD_ERROR_SIZE__B                                          0
#define   QAM_LC_RAD_ERROR_SIZE__W                                          10
#define   QAM_LC_RAD_ERROR_SIZE__M                                          0x3FF
#define   QAM_LC_RAD_ERROR_SIZE__PRE                                        0x0

#define QAM_LC_FREQ_OFFS__A                                                 0x1450032
#define QAM_LC_FREQ_OFFS__W                                                 10
#define QAM_LC_FREQ_OFFS__M                                                 0x3FF
#define QAM_LC_FREQ_OFFS__PRE                                               0x0

#define   QAM_LC_FREQ_OFFS_OFFS__B                                          0
#define   QAM_LC_FREQ_OFFS_OFFS__W                                          10
#define   QAM_LC_FREQ_OFFS_OFFS__M                                          0x3FF
#define   QAM_LC_FREQ_OFFS_OFFS__PRE                                        0x0

#define QAM_LC_PHASE_ERROR__A                                               0x1450033
#define QAM_LC_PHASE_ERROR__W                                               10
#define QAM_LC_PHASE_ERROR__M                                               0x3FF
#define QAM_LC_PHASE_ERROR__PRE                                             0x0

#define   QAM_LC_PHASE_ERROR_SIZE__B                                        0
#define   QAM_LC_PHASE_ERROR_SIZE__W                                        10
#define   QAM_LC_PHASE_ERROR_SIZE__M                                        0x3FF
#define   QAM_LC_PHASE_ERROR_SIZE__PRE                                      0x0

#define QAM_VD_COMM_EXEC__A                                                 0x1460000
#define QAM_VD_COMM_EXEC__W                                                 2
#define QAM_VD_COMM_EXEC__M                                                 0x3
#define QAM_VD_COMM_EXEC__PRE                                               0x0
#define   QAM_VD_COMM_EXEC_STOP                                             0x0
#define   QAM_VD_COMM_EXEC_ACTIVE                                           0x1
#define   QAM_VD_COMM_EXEC_HOLD                                             0x2

#define QAM_VD_COMM_MB__A                                                   0x1460002
#define QAM_VD_COMM_MB__W                                                   2
#define QAM_VD_COMM_MB__M                                                   0x3
#define QAM_VD_COMM_MB__PRE                                                 0x0
#define   QAM_VD_COMM_MB_CTL__B                                             0
#define   QAM_VD_COMM_MB_CTL__W                                             1
#define   QAM_VD_COMM_MB_CTL__M                                             0x1
#define   QAM_VD_COMM_MB_CTL__PRE                                           0x0
#define     QAM_VD_COMM_MB_CTL_OFF                                          0x0
#define     QAM_VD_COMM_MB_CTL_ON                                           0x1
#define   QAM_VD_COMM_MB_OBS__B                                             1
#define   QAM_VD_COMM_MB_OBS__W                                             1
#define   QAM_VD_COMM_MB_OBS__M                                             0x2
#define   QAM_VD_COMM_MB_OBS__PRE                                           0x0
#define     QAM_VD_COMM_MB_OBS_OFF                                          0x0
#define     QAM_VD_COMM_MB_OBS_ON                                           0x2

#define QAM_VD_COMM_INT_REQ__A                                              0x1460003
#define QAM_VD_COMM_INT_REQ__W                                              1
#define QAM_VD_COMM_INT_REQ__M                                              0x1
#define QAM_VD_COMM_INT_REQ__PRE                                            0x0
#define QAM_VD_COMM_INT_STA__A                                              0x1460005
#define QAM_VD_COMM_INT_STA__W                                              2
#define QAM_VD_COMM_INT_STA__M                                              0x3
#define QAM_VD_COMM_INT_STA__PRE                                            0x0

#define   QAM_VD_COMM_INT_STA_LOCK_INT__B                                   0
#define   QAM_VD_COMM_INT_STA_LOCK_INT__W                                   1
#define   QAM_VD_COMM_INT_STA_LOCK_INT__M                                   0x1
#define   QAM_VD_COMM_INT_STA_LOCK_INT__PRE                                 0x0

#define   QAM_VD_COMM_INT_STA_PERIOD_INT__B                                 1
#define   QAM_VD_COMM_INT_STA_PERIOD_INT__W                                 1
#define   QAM_VD_COMM_INT_STA_PERIOD_INT__M                                 0x2
#define   QAM_VD_COMM_INT_STA_PERIOD_INT__PRE                               0x0

#define QAM_VD_COMM_INT_MSK__A                                              0x1460006
#define QAM_VD_COMM_INT_MSK__W                                              2
#define QAM_VD_COMM_INT_MSK__M                                              0x3
#define QAM_VD_COMM_INT_MSK__PRE                                            0x0
#define   QAM_VD_COMM_INT_MSK_LOCK_INT__B                                   0
#define   QAM_VD_COMM_INT_MSK_LOCK_INT__W                                   1
#define   QAM_VD_COMM_INT_MSK_LOCK_INT__M                                   0x1
#define   QAM_VD_COMM_INT_MSK_LOCK_INT__PRE                                 0x0
#define   QAM_VD_COMM_INT_MSK_PERIOD_INT__B                                 1
#define   QAM_VD_COMM_INT_MSK_PERIOD_INT__W                                 1
#define   QAM_VD_COMM_INT_MSK_PERIOD_INT__M                                 0x2
#define   QAM_VD_COMM_INT_MSK_PERIOD_INT__PRE                               0x0

#define QAM_VD_COMM_INT_STM__A                                              0x1460007
#define QAM_VD_COMM_INT_STM__W                                              2
#define QAM_VD_COMM_INT_STM__M                                              0x3
#define QAM_VD_COMM_INT_STM__PRE                                            0x0
#define   QAM_VD_COMM_INT_STM_LOCK_INT__B                                   0
#define   QAM_VD_COMM_INT_STM_LOCK_INT__W                                   1
#define   QAM_VD_COMM_INT_STM_LOCK_INT__M                                   0x1
#define   QAM_VD_COMM_INT_STM_LOCK_INT__PRE                                 0x0
#define   QAM_VD_COMM_INT_STM_PERIOD_INT__B                                 1
#define   QAM_VD_COMM_INT_STM_PERIOD_INT__W                                 1
#define   QAM_VD_COMM_INT_STM_PERIOD_INT__M                                 0x2
#define   QAM_VD_COMM_INT_STM_PERIOD_INT__PRE                               0x0

#define QAM_VD_STATUS__A                                                    0x1460010
#define QAM_VD_STATUS__W                                                    1
#define QAM_VD_STATUS__M                                                    0x1
#define QAM_VD_STATUS__PRE                                                  0x0

#define   QAM_VD_STATUS_LOCK__B                                             0
#define   QAM_VD_STATUS_LOCK__W                                             1
#define   QAM_VD_STATUS_LOCK__M                                             0x1
#define   QAM_VD_STATUS_LOCK__PRE                                           0x0

#define QAM_VD_UNLOCK_CONTROL__A                                            0x1460011
#define QAM_VD_UNLOCK_CONTROL__W                                            1
#define QAM_VD_UNLOCK_CONTROL__M                                            0x1
#define QAM_VD_UNLOCK_CONTROL__PRE                                          0x0

#define   QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__B                              0
#define   QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__W                              1
#define   QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__M                              0x1
#define   QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__PRE                            0x0

#define QAM_VD_MIN_VOTING_ROUNDS__A                                         0x1460012
#define QAM_VD_MIN_VOTING_ROUNDS__W                                         6
#define QAM_VD_MIN_VOTING_ROUNDS__M                                         0x3F
#define QAM_VD_MIN_VOTING_ROUNDS__PRE                                       0x10

#define   QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__B                                0
#define   QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__W                                6
#define   QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__M                                0x3F
#define   QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__PRE                              0x10

#define QAM_VD_MAX_VOTING_ROUNDS__A                                         0x1460013
#define QAM_VD_MAX_VOTING_ROUNDS__W                                         6
#define QAM_VD_MAX_VOTING_ROUNDS__M                                         0x3F
#define QAM_VD_MAX_VOTING_ROUNDS__PRE                                       0x10

#define   QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__B                                0
#define   QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__W                                6
#define   QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__M                                0x3F
#define   QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__PRE                              0x10

#define QAM_VD_TRACEBACK_DEPTH__A                                           0x1460014
#define QAM_VD_TRACEBACK_DEPTH__W                                           5
#define QAM_VD_TRACEBACK_DEPTH__M                                           0x1F
#define QAM_VD_TRACEBACK_DEPTH__PRE                                         0x10

#define   QAM_VD_TRACEBACK_DEPTH_LENGTH__B                                  0
#define   QAM_VD_TRACEBACK_DEPTH_LENGTH__W                                  5
#define   QAM_VD_TRACEBACK_DEPTH_LENGTH__M                                  0x1F
#define   QAM_VD_TRACEBACK_DEPTH_LENGTH__PRE                                0x10

#define QAM_VD_UNLOCK__A                                                    0x1460015
#define QAM_VD_UNLOCK__W                                                    1
#define QAM_VD_UNLOCK__M                                                    0x1
#define QAM_VD_UNLOCK__PRE                                                  0x0
#define QAM_VD_MEASUREMENT_PERIOD__A                                        0x1460016
#define QAM_VD_MEASUREMENT_PERIOD__W                                        16
#define QAM_VD_MEASUREMENT_PERIOD__M                                        0xFFFF
#define QAM_VD_MEASUREMENT_PERIOD__PRE                                      0x8236

#define   QAM_VD_MEASUREMENT_PERIOD_PERIOD__B                               0
#define   QAM_VD_MEASUREMENT_PERIOD_PERIOD__W                               16
#define   QAM_VD_MEASUREMENT_PERIOD_PERIOD__M                               0xFFFF
#define   QAM_VD_MEASUREMENT_PERIOD_PERIOD__PRE                             0x8236

#define QAM_VD_MEASUREMENT_PRESCALE__A                                      0x1460017
#define QAM_VD_MEASUREMENT_PRESCALE__W                                      16
#define QAM_VD_MEASUREMENT_PRESCALE__M                                      0xFFFF
#define QAM_VD_MEASUREMENT_PRESCALE__PRE                                    0x4

#define   QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__B                           0
#define   QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__W                           16
#define   QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__M                           0xFFFF
#define   QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__PRE                         0x4

#define QAM_VD_DELTA_PATH_METRIC__A                                         0x1460018
#define QAM_VD_DELTA_PATH_METRIC__W                                         16
#define QAM_VD_DELTA_PATH_METRIC__M                                         0xFFFF
#define QAM_VD_DELTA_PATH_METRIC__PRE                                       0xFFFF

#define   QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__B                            0
#define   QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__W                            12
#define   QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__M                            0xFFF
#define   QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__PRE                          0xFFF

#define   QAM_VD_DELTA_PATH_METRIC_EXP__B                                   12
#define   QAM_VD_DELTA_PATH_METRIC_EXP__W                                   4
#define   QAM_VD_DELTA_PATH_METRIC_EXP__M                                   0xF000
#define   QAM_VD_DELTA_PATH_METRIC_EXP__PRE                                 0xF000

#define QAM_VD_NR_QSYM_ERRORS__A                                            0x1460019
#define QAM_VD_NR_QSYM_ERRORS__W                                            16
#define QAM_VD_NR_QSYM_ERRORS__M                                            0xFFFF
#define QAM_VD_NR_QSYM_ERRORS__PRE                                          0xFFFF

#define   QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__B                               0
#define   QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__W                               12
#define   QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__M                               0xFFF
#define   QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__PRE                             0xFFF

#define   QAM_VD_NR_QSYM_ERRORS_EXP__B                                      12
#define   QAM_VD_NR_QSYM_ERRORS_EXP__W                                      4
#define   QAM_VD_NR_QSYM_ERRORS_EXP__M                                      0xF000
#define   QAM_VD_NR_QSYM_ERRORS_EXP__PRE                                    0xF000

#define QAM_VD_NR_SYMBOL_ERRORS__A                                          0x146001A
#define QAM_VD_NR_SYMBOL_ERRORS__W                                          16
#define QAM_VD_NR_SYMBOL_ERRORS__M                                          0xFFFF
#define QAM_VD_NR_SYMBOL_ERRORS__PRE                                        0xFFFF

#define   QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B                             0
#define   QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__W                             12
#define   QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M                             0xFFF
#define   QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__PRE                           0xFFF

#define   QAM_VD_NR_SYMBOL_ERRORS_EXP__B                                    12
#define   QAM_VD_NR_SYMBOL_ERRORS_EXP__W                                    4
#define   QAM_VD_NR_SYMBOL_ERRORS_EXP__M                                    0xF000
#define   QAM_VD_NR_SYMBOL_ERRORS_EXP__PRE                                  0xF000

#define QAM_VD_RELOCK_COUNT__A                                              0x146001B
#define QAM_VD_RELOCK_COUNT__W                                              16
#define QAM_VD_RELOCK_COUNT__M                                              0xFFFF
#define QAM_VD_RELOCK_COUNT__PRE                                            0x0

#define   QAM_VD_RELOCK_COUNT_COUNT__B                                      0
#define   QAM_VD_RELOCK_COUNT_COUNT__W                                      8
#define   QAM_VD_RELOCK_COUNT_COUNT__M                                      0xFF
#define   QAM_VD_RELOCK_COUNT_COUNT__PRE                                    0x0

#define QAM_SY_COMM_EXEC__A                                                 0x1470000
#define QAM_SY_COMM_EXEC__W                                                 2
#define QAM_SY_COMM_EXEC__M                                                 0x3
#define QAM_SY_COMM_EXEC__PRE                                               0x0
#define   QAM_SY_COMM_EXEC_STOP                                             0x0
#define   QAM_SY_COMM_EXEC_ACTIVE                                           0x1
#define   QAM_SY_COMM_EXEC_HOLD                                             0x2

#define QAM_SY_COMM_MB__A                                                   0x1470002
#define QAM_SY_COMM_MB__W                                                   2
#define QAM_SY_COMM_MB__M                                                   0x3
#define QAM_SY_COMM_MB__PRE                                                 0x0
#define   QAM_SY_COMM_MB_CTL__B                                             0
#define   QAM_SY_COMM_MB_CTL__W                                             1
#define   QAM_SY_COMM_MB_CTL__M                                             0x1
#define   QAM_SY_COMM_MB_CTL__PRE                                           0x0
#define     QAM_SY_COMM_MB_CTL_OFF                                          0x0
#define     QAM_SY_COMM_MB_CTL_ON                                           0x1
#define   QAM_SY_COMM_MB_OBS__B                                             1
#define   QAM_SY_COMM_MB_OBS__W                                             1
#define   QAM_SY_COMM_MB_OBS__M                                             0x2
#define   QAM_SY_COMM_MB_OBS__PRE                                           0x0
#define     QAM_SY_COMM_MB_OBS_OFF                                          0x0
#define     QAM_SY_COMM_MB_OBS_ON                                           0x2

#define QAM_SY_COMM_INT_REQ__A                                              0x1470003
#define QAM_SY_COMM_INT_REQ__W                                              1
#define QAM_SY_COMM_INT_REQ__M                                              0x1
#define QAM_SY_COMM_INT_REQ__PRE                                            0x0
#define QAM_SY_COMM_INT_STA__A                                              0x1470005
#define QAM_SY_COMM_INT_STA__W                                              4
#define QAM_SY_COMM_INT_STA__M                                              0xF
#define QAM_SY_COMM_INT_STA__PRE                                            0x0

#define   QAM_SY_COMM_INT_STA_LOCK_INT__B                                   0
#define   QAM_SY_COMM_INT_STA_LOCK_INT__W                                   1
#define   QAM_SY_COMM_INT_STA_LOCK_INT__M                                   0x1
#define   QAM_SY_COMM_INT_STA_LOCK_INT__PRE                                 0x0

#define   QAM_SY_COMM_INT_STA_UNLOCK_INT__B                                 1
#define   QAM_SY_COMM_INT_STA_UNLOCK_INT__W                                 1
#define   QAM_SY_COMM_INT_STA_UNLOCK_INT__M                                 0x2
#define   QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE                               0x0

#define   QAM_SY_COMM_INT_STA_TIMEOUT_INT__B                                2
#define   QAM_SY_COMM_INT_STA_TIMEOUT_INT__W                                1
#define   QAM_SY_COMM_INT_STA_TIMEOUT_INT__M                                0x4
#define   QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE                              0x0

#define   QAM_SY_COMM_INT_STA_CTL_WORD_INT__B                               3
#define   QAM_SY_COMM_INT_STA_CTL_WORD_INT__W                               1
#define   QAM_SY_COMM_INT_STA_CTL_WORD_INT__M                               0x8
#define   QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE                             0x0

#define QAM_SY_COMM_INT_MSK__A                                              0x1470006
#define QAM_SY_COMM_INT_MSK__W                                              4
#define QAM_SY_COMM_INT_MSK__M                                              0xF
#define QAM_SY_COMM_INT_MSK__PRE                                            0x0
#define   QAM_SY_COMM_INT_MSK_LOCK_MSK__B                                   0
#define   QAM_SY_COMM_INT_MSK_LOCK_MSK__W                                   1
#define   QAM_SY_COMM_INT_MSK_LOCK_MSK__M                                   0x1
#define   QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE                                 0x0
#define   QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B                                 1
#define   QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W                                 1
#define   QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M                                 0x2
#define   QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE                               0x0
#define   QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B                                2
#define   QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W                                1
#define   QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M                                0x4
#define   QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE                              0x0
#define   QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B                               3
#define   QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W                               1
#define   QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M                               0x8
#define   QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE                             0x0

#define QAM_SY_COMM_INT_STM__A                                              0x1470007
#define QAM_SY_COMM_INT_STM__W                                              4
#define QAM_SY_COMM_INT_STM__M                                              0xF
#define QAM_SY_COMM_INT_STM__PRE                                            0x0
#define   QAM_SY_COMM_INT_STM_LOCK_MSK__B                                   0
#define   QAM_SY_COMM_INT_STM_LOCK_MSK__W                                   1
#define   QAM_SY_COMM_INT_STM_LOCK_MSK__M                                   0x1
#define   QAM_SY_COMM_INT_STM_LOCK_MSK__PRE                                 0x0
#define   QAM_SY_COMM_INT_STM_UNLOCK_MSK__B                                 1
#define   QAM_SY_COMM_INT_STM_UNLOCK_MSK__W                                 1
#define   QAM_SY_COMM_INT_STM_UNLOCK_MSK__M                                 0x2
#define   QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE                               0x0
#define   QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B                                2
#define   QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W                                1
#define   QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M                                0x4
#define   QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE                              0x0
#define   QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B                               3
#define   QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W                               1
#define   QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M                               0x8
#define   QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE                             0x0

#define QAM_SY_STATUS__A                                                    0x1470010
#define QAM_SY_STATUS__W                                                    2
#define QAM_SY_STATUS__M                                                    0x3
#define QAM_SY_STATUS__PRE                                                  0x0

#define   QAM_SY_STATUS_SYNC_STATE__B                                       0
#define   QAM_SY_STATUS_SYNC_STATE__W                                       2
#define   QAM_SY_STATUS_SYNC_STATE__M                                       0x3
#define   QAM_SY_STATUS_SYNC_STATE__PRE                                     0x0

#define QAM_SY_TIMEOUT__A                                                   0x1470011
#define QAM_SY_TIMEOUT__W                                                   16
#define QAM_SY_TIMEOUT__M                                                   0xFFFF
#define QAM_SY_TIMEOUT__PRE                                                 0x3A98

#define QAM_SY_SYNC_LWM__A                                                  0x1470012
#define QAM_SY_SYNC_LWM__W                                                  4
#define QAM_SY_SYNC_LWM__M                                                  0xF
#define QAM_SY_SYNC_LWM__PRE                                                0x2

#define QAM_SY_SYNC_AWM__A                                                  0x1470013
#define QAM_SY_SYNC_AWM__W                                                  4
#define QAM_SY_SYNC_AWM__M                                                  0xF
#define QAM_SY_SYNC_AWM__PRE                                                0x3

#define QAM_SY_SYNC_HWM__A                                                  0x1470014
#define QAM_SY_SYNC_HWM__W                                                  4
#define QAM_SY_SYNC_HWM__M                                                  0xF
#define QAM_SY_SYNC_HWM__PRE                                                0x5

#define QAM_SY_UNLOCK__A                                                    0x1470015
#define QAM_SY_UNLOCK__W                                                    1
#define QAM_SY_UNLOCK__M                                                    0x1
#define QAM_SY_UNLOCK__PRE                                                  0x0
#define QAM_SY_CONTROL_WORD__A                                              0x1470016
#define QAM_SY_CONTROL_WORD__W                                              4
#define QAM_SY_CONTROL_WORD__M                                              0xF
#define QAM_SY_CONTROL_WORD__PRE                                            0x0

#define   QAM_SY_CONTROL_WORD_CTRL_WORD__B                                  0
#define   QAM_SY_CONTROL_WORD_CTRL_WORD__W                                  4
#define   QAM_SY_CONTROL_WORD_CTRL_WORD__M                                  0xF
#define   QAM_SY_CONTROL_WORD_CTRL_WORD__PRE                                0x0

#define QAM_VD_ISS_RAM__A                                                   0x1480000

#define QAM_VD_QSS_RAM__A                                                   0x1490000

#define QAM_VD_SYM_RAM__A                                                   0x14A0000

#define SCU_COMM_EXEC__A                                                    0x800000
#define SCU_COMM_EXEC__W                                                    2
#define SCU_COMM_EXEC__M                                                    0x3
#define SCU_COMM_EXEC__PRE                                                  0x0
#define   SCU_COMM_EXEC_STOP                                                0x0
#define   SCU_COMM_EXEC_ACTIVE                                              0x1
#define   SCU_COMM_EXEC_HOLD                                                0x2

#define SCU_COMM_STATE__A                                                   0x800001
#define SCU_COMM_STATE__W                                                   16
#define SCU_COMM_STATE__M                                                   0xFFFF
#define SCU_COMM_STATE__PRE                                                 0x0

#define   SCU_COMM_STATE_COMM_STATE__B                                      0
#define   SCU_COMM_STATE_COMM_STATE__W                                      16
#define   SCU_COMM_STATE_COMM_STATE__M                                      0xFFFF
#define   SCU_COMM_STATE_COMM_STATE__PRE                                    0x0

#define SCU_TOP_COMM_EXEC__A                                                0x810000
#define SCU_TOP_COMM_EXEC__W                                                2
#define SCU_TOP_COMM_EXEC__M                                                0x3
#define SCU_TOP_COMM_EXEC__PRE                                              0x0
#define   SCU_TOP_COMM_EXEC_STOP                                            0x0
#define   SCU_TOP_COMM_EXEC_ACTIVE                                          0x1
#define   SCU_TOP_COMM_EXEC_HOLD                                            0x2

#define SCU_TOP_COMM_STATE__A                                               0x810001
#define SCU_TOP_COMM_STATE__W                                               16
#define SCU_TOP_COMM_STATE__M                                               0xFFFF
#define SCU_TOP_COMM_STATE__PRE                                             0x0
#define SCU_TOP_MWAIT_CTR__A                                                0x810010
#define SCU_TOP_MWAIT_CTR__W                                                2
#define SCU_TOP_MWAIT_CTR__M                                                0x3
#define SCU_TOP_MWAIT_CTR__PRE                                              0x0

#define   SCU_TOP_MWAIT_CTR_MWAIT_SEL__B                                    0
#define   SCU_TOP_MWAIT_CTR_MWAIT_SEL__W                                    1
#define   SCU_TOP_MWAIT_CTR_MWAIT_SEL__M                                    0x1
#define   SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE                                  0x0
#define     SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF                           0x0
#define     SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON                            0x1

#define   SCU_TOP_MWAIT_CTR_READY_DIS__B                                    1
#define   SCU_TOP_MWAIT_CTR_READY_DIS__W                                    1
#define   SCU_TOP_MWAIT_CTR_READY_DIS__M                                    0x2
#define   SCU_TOP_MWAIT_CTR_READY_DIS__PRE                                  0x0
#define     SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON                              0x0
#define     SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF                             0x2

#define SCU_LOW_RAM__A                                                      0x820000

#define   SCU_LOW_RAM_LOW__B                                                0
#define   SCU_LOW_RAM_LOW__W                                                16
#define   SCU_LOW_RAM_LOW__M                                                0xFFFF
#define   SCU_LOW_RAM_LOW__PRE                                              0x0

#define SCU_HIGH_RAM__A                                                     0x830000

#define   SCU_HIGH_RAM_HIGH__B                                              0
#define   SCU_HIGH_RAM_HIGH__W                                              16
#define   SCU_HIGH_RAM_HIGH__M                                              0xFFFF
#define   SCU_HIGH_RAM_HIGH__PRE                                            0x0

#define SCU_RAM_AGC_RF_MAX__A                                               0x831E96
#define SCU_RAM_AGC_RF_MAX__W                                               15
#define SCU_RAM_AGC_RF_MAX__M                                               0x7FFF
#define SCU_RAM_AGC_RF_MAX__PRE                                             0x0

#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A                                  0x831E97
#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W                                  16
#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M                                  0xFFFF
#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE                                0x0

#define SCU_RAM_AGC_KI_CYCCNT__A                                            0x831E98
#define SCU_RAM_AGC_KI_CYCCNT__W                                            16
#define SCU_RAM_AGC_KI_CYCCNT__M                                            0xFFFF
#define SCU_RAM_AGC_KI_CYCCNT__PRE                                          0x0

#define SCU_RAM_AGC_KI_CYCLEN__A                                            0x831E99
#define SCU_RAM_AGC_KI_CYCLEN__W                                            16
#define SCU_RAM_AGC_KI_CYCLEN__M                                            0xFFFF
#define SCU_RAM_AGC_KI_CYCLEN__PRE                                          0x0

#define SCU_RAM_AGC_SNS_CYCLEN__A                                           0x831E9A
#define SCU_RAM_AGC_SNS_CYCLEN__W                                           16
#define SCU_RAM_AGC_SNS_CYCLEN__M                                           0xFFFF
#define SCU_RAM_AGC_SNS_CYCLEN__PRE                                         0x0

#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A                                       0x831E9B
#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W                                       16
#define SCU_RAM_AGC_RF_SNS_DEV_MAX__M                                       0xFFFF
#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE                                     0x0

#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A                                       0x831E9C
#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W                                       16
#define SCU_RAM_AGC_RF_SNS_DEV_MIN__M                                       0xFFFF
#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE                                     0x0
#define SCU_RAM_AGC_KI__A                                                   0x831E9D
#define SCU_RAM_AGC_KI__W                                                   15
#define SCU_RAM_AGC_KI__M                                                   0x7FFF
#define SCU_RAM_AGC_KI__PRE                                                 0x0

#define   SCU_RAM_AGC_KI_DGAIN__B                                           0
#define   SCU_RAM_AGC_KI_DGAIN__W                                           4
#define   SCU_RAM_AGC_KI_DGAIN__M                                           0xF
#define   SCU_RAM_AGC_KI_DGAIN__PRE                                         0x0

#define   SCU_RAM_AGC_KI_RF__B                                              4
#define   SCU_RAM_AGC_KI_RF__W                                              4
#define   SCU_RAM_AGC_KI_RF__M                                              0xF0
#define   SCU_RAM_AGC_KI_RF__PRE                                            0x0

#define   SCU_RAM_AGC_KI_IF__B                                              8
#define   SCU_RAM_AGC_KI_IF__W                                              4
#define   SCU_RAM_AGC_KI_IF__M                                              0xF00
#define   SCU_RAM_AGC_KI_IF__PRE                                            0x0

#define   SCU_RAM_AGC_KI_IF_AGC_DISABLE__B                                  12
#define   SCU_RAM_AGC_KI_IF_AGC_DISABLE__W                                  1
#define   SCU_RAM_AGC_KI_IF_AGC_DISABLE__M                                  0x1000
#define   SCU_RAM_AGC_KI_IF_AGC_DISABLE__PRE                                0x0

#define   SCU_RAM_AGC_KI_INV_IF_POL__B                                      13
#define   SCU_RAM_AGC_KI_INV_IF_POL__W                                      1
#define   SCU_RAM_AGC_KI_INV_IF_POL__M                                      0x2000
#define   SCU_RAM_AGC_KI_INV_IF_POL__PRE                                    0x0

#define   SCU_RAM_AGC_KI_INV_RF_POL__B                                      14
#define   SCU_RAM_AGC_KI_INV_RF_POL__W                                      1
#define   SCU_RAM_AGC_KI_INV_RF_POL__M                                      0x4000
#define   SCU_RAM_AGC_KI_INV_RF_POL__PRE                                    0x0

#define SCU_RAM_AGC_KI_RED__A                                               0x831E9E
#define SCU_RAM_AGC_KI_RED__W                                               6
#define SCU_RAM_AGC_KI_RED__M                                               0x3F
#define SCU_RAM_AGC_KI_RED__PRE                                             0x0

#define   SCU_RAM_AGC_KI_RED_INNER_RED__B                                   0
#define   SCU_RAM_AGC_KI_RED_INNER_RED__W                                   2
#define   SCU_RAM_AGC_KI_RED_INNER_RED__M                                   0x3
#define   SCU_RAM_AGC_KI_RED_INNER_RED__PRE                                 0x0

#define   SCU_RAM_AGC_KI_RED_RAGC_RED__B                                    2
#define   SCU_RAM_AGC_KI_RED_RAGC_RED__W                                    2
#define   SCU_RAM_AGC_KI_RED_RAGC_RED__M                                    0xC
#define   SCU_RAM_AGC_KI_RED_RAGC_RED__PRE                                  0x0

#define   SCU_RAM_AGC_KI_RED_IAGC_RED__B                                    4
#define   SCU_RAM_AGC_KI_RED_IAGC_RED__W                                    2
#define   SCU_RAM_AGC_KI_RED_IAGC_RED__M                                    0x30
#define   SCU_RAM_AGC_KI_RED_IAGC_RED__PRE                                  0x0

#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A                                     0x831E9F
#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W                                     16
#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M                                     0xFFFF
#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE                                   0x0

#define SCU_RAM_AGC_KI_MINGAIN__A                                           0x831EA0
#define SCU_RAM_AGC_KI_MINGAIN__W                                           16
#define SCU_RAM_AGC_KI_MINGAIN__M                                           0xFFFF
#define SCU_RAM_AGC_KI_MINGAIN__PRE                                         0x0

#define SCU_RAM_AGC_KI_MAXGAIN__A                                           0x831EA1
#define SCU_RAM_AGC_KI_MAXGAIN__W                                           16
#define SCU_RAM_AGC_KI_MAXGAIN__M                                           0xFFFF
#define SCU_RAM_AGC_KI_MAXGAIN__PRE                                         0x0

#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A                                     0x831EA2
#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W                                     16
#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M                                     0xFFFF
#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE                                   0x0
#define SCU_RAM_AGC_KI_MIN__A                                               0x831EA3
#define SCU_RAM_AGC_KI_MIN__W                                               12
#define SCU_RAM_AGC_KI_MIN__M                                               0xFFF
#define SCU_RAM_AGC_KI_MIN__PRE                                             0x0

#define   SCU_RAM_AGC_KI_MIN_DGAIN__B                                       0
#define   SCU_RAM_AGC_KI_MIN_DGAIN__W                                       4
#define   SCU_RAM_AGC_KI_MIN_DGAIN__M                                       0xF
#define   SCU_RAM_AGC_KI_MIN_DGAIN__PRE                                     0x0

#define   SCU_RAM_AGC_KI_MIN_RF__B                                          4
#define   SCU_RAM_AGC_KI_MIN_RF__W                                          4
#define   SCU_RAM_AGC_KI_MIN_RF__M                                          0xF0
#define   SCU_RAM_AGC_KI_MIN_RF__PRE                                        0x0

#define   SCU_RAM_AGC_KI_MIN_IF__B                                          8
#define   SCU_RAM_AGC_KI_MIN_IF__W                                          4
#define   SCU_RAM_AGC_KI_MIN_IF__M                                          0xF00
#define   SCU_RAM_AGC_KI_MIN_IF__PRE                                        0x0

#define SCU_RAM_AGC_KI_MAX__A                                               0x831EA4
#define SCU_RAM_AGC_KI_MAX__W                                               12
#define SCU_RAM_AGC_KI_MAX__M                                               0xFFF
#define SCU_RAM_AGC_KI_MAX__PRE                                             0x0

#define   SCU_RAM_AGC_KI_MAX_DGAIN__B                                       0
#define   SCU_RAM_AGC_KI_MAX_DGAIN__W                                       4
#define   SCU_RAM_AGC_KI_MAX_DGAIN__M                                       0xF
#define   SCU_RAM_AGC_KI_MAX_DGAIN__PRE                                     0x0

#define   SCU_RAM_AGC_KI_MAX_RF__B                                          4
#define   SCU_RAM_AGC_KI_MAX_RF__W                                          4
#define   SCU_RAM_AGC_KI_MAX_RF__M                                          0xF0
#define   SCU_RAM_AGC_KI_MAX_RF__PRE                                        0x0

#define   SCU_RAM_AGC_KI_MAX_IF__B                                          8
#define   SCU_RAM_AGC_KI_MAX_IF__W                                          4
#define   SCU_RAM_AGC_KI_MAX_IF__M                                          0xF00
#define   SCU_RAM_AGC_KI_MAX_IF__PRE                                        0x0

#define SCU_RAM_AGC_CLP_SUM__A                                              0x831EA5
#define SCU_RAM_AGC_CLP_SUM__W                                              16
#define SCU_RAM_AGC_CLP_SUM__M                                              0xFFFF
#define SCU_RAM_AGC_CLP_SUM__PRE                                            0x0

#define SCU_RAM_AGC_CLP_SUM_MIN__A                                          0x831EA6
#define SCU_RAM_AGC_CLP_SUM_MIN__W                                          16
#define SCU_RAM_AGC_CLP_SUM_MIN__M                                          0xFFFF
#define SCU_RAM_AGC_CLP_SUM_MIN__PRE                                        0x0

#define SCU_RAM_AGC_CLP_SUM_MAX__A                                          0x831EA7
#define SCU_RAM_AGC_CLP_SUM_MAX__W                                          16
#define SCU_RAM_AGC_CLP_SUM_MAX__M                                          0xFFFF
#define SCU_RAM_AGC_CLP_SUM_MAX__PRE                                        0x0

#define SCU_RAM_AGC_CLP_CYCLEN__A                                           0x831EA8
#define SCU_RAM_AGC_CLP_CYCLEN__W                                           16
#define SCU_RAM_AGC_CLP_CYCLEN__M                                           0xFFFF
#define SCU_RAM_AGC_CLP_CYCLEN__PRE                                         0x0

#define SCU_RAM_AGC_CLP_CYCCNT__A                                           0x831EA9
#define SCU_RAM_AGC_CLP_CYCCNT__W                                           16
#define SCU_RAM_AGC_CLP_CYCCNT__M                                           0xFFFF
#define SCU_RAM_AGC_CLP_CYCCNT__PRE                                         0x0

#define SCU_RAM_AGC_CLP_DIR_TO__A                                           0x831EAA
#define SCU_RAM_AGC_CLP_DIR_TO__W                                           8
#define SCU_RAM_AGC_CLP_DIR_TO__M                                           0xFF
#define SCU_RAM_AGC_CLP_DIR_TO__PRE                                         0x0

#define SCU_RAM_AGC_CLP_DIR_WD__A                                           0x831EAB
#define SCU_RAM_AGC_CLP_DIR_WD__W                                           8
#define SCU_RAM_AGC_CLP_DIR_WD__M                                           0xFF
#define SCU_RAM_AGC_CLP_DIR_WD__PRE                                         0x0

#define SCU_RAM_AGC_CLP_DIR_STP__A                                          0x831EAC
#define SCU_RAM_AGC_CLP_DIR_STP__W                                          16
#define SCU_RAM_AGC_CLP_DIR_STP__M                                          0xFFFF
#define SCU_RAM_AGC_CLP_DIR_STP__PRE                                        0x0

#define SCU_RAM_AGC_SNS_SUM__A                                              0x831EAD
#define SCU_RAM_AGC_SNS_SUM__W                                              16
#define SCU_RAM_AGC_SNS_SUM__M                                              0xFFFF
#define SCU_RAM_AGC_SNS_SUM__PRE                                            0x0

#define SCU_RAM_AGC_SNS_SUM_MIN__A                                          0x831EAE
#define SCU_RAM_AGC_SNS_SUM_MIN__W                                          16
#define SCU_RAM_AGC_SNS_SUM_MIN__M                                          0xFFFF
#define SCU_RAM_AGC_SNS_SUM_MIN__PRE                                        0x0

#define SCU_RAM_AGC_SNS_SUM_MAX__A                                          0x831EAF
#define SCU_RAM_AGC_SNS_SUM_MAX__W                                          16
#define SCU_RAM_AGC_SNS_SUM_MAX__M                                          0xFFFF
#define SCU_RAM_AGC_SNS_SUM_MAX__PRE                                        0x0

#define SCU_RAM_AGC_SNS_CYCCNT__A                                           0x831EB0
#define SCU_RAM_AGC_SNS_CYCCNT__W                                           16
#define SCU_RAM_AGC_SNS_CYCCNT__M                                           0xFFFF
#define SCU_RAM_AGC_SNS_CYCCNT__PRE                                         0x0

#define SCU_RAM_AGC_SNS_DIR_TO__A                                           0x831EB1
#define SCU_RAM_AGC_SNS_DIR_TO__W                                           8
#define SCU_RAM_AGC_SNS_DIR_TO__M                                           0xFF
#define SCU_RAM_AGC_SNS_DIR_TO__PRE                                         0x0

#define SCU_RAM_AGC_SNS_DIR_WD__A                                           0x831EB2
#define SCU_RAM_AGC_SNS_DIR_WD__W                                           8
#define SCU_RAM_AGC_SNS_DIR_WD__M                                           0xFF
#define SCU_RAM_AGC_SNS_DIR_WD__PRE                                         0x0

#define SCU_RAM_AGC_SNS_DIR_STP__A                                          0x831EB3
#define SCU_RAM_AGC_SNS_DIR_STP__W                                          16
#define SCU_RAM_AGC_SNS_DIR_STP__M                                          0xFFFF
#define SCU_RAM_AGC_SNS_DIR_STP__PRE                                        0x0

#define SCU_RAM_AGC_INGAIN__A                                               0x831EB4
#define SCU_RAM_AGC_INGAIN__W                                               16
#define SCU_RAM_AGC_INGAIN__M                                               0xFFFF
#define SCU_RAM_AGC_INGAIN__PRE                                             0x0

#define SCU_RAM_AGC_INGAIN_TGT__A                                           0x831EB5
#define SCU_RAM_AGC_INGAIN_TGT__W                                           15
#define SCU_RAM_AGC_INGAIN_TGT__M                                           0x7FFF
#define SCU_RAM_AGC_INGAIN_TGT__PRE                                         0x0

#define SCU_RAM_AGC_INGAIN_TGT_MIN__A                                       0x831EB6
#define SCU_RAM_AGC_INGAIN_TGT_MIN__W                                       15
#define SCU_RAM_AGC_INGAIN_TGT_MIN__M                                       0x7FFF
#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE                                     0x0

#define SCU_RAM_AGC_INGAIN_TGT_MAX__A                                       0x831EB7
#define SCU_RAM_AGC_INGAIN_TGT_MAX__W                                       15
#define SCU_RAM_AGC_INGAIN_TGT_MAX__M                                       0x7FFF
#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE                                     0x0

#define SCU_RAM_AGC_IF_IACCU_HI__A                                          0x831EB8
#define SCU_RAM_AGC_IF_IACCU_HI__W                                          16
#define SCU_RAM_AGC_IF_IACCU_HI__M                                          0xFFFF
#define SCU_RAM_AGC_IF_IACCU_HI__PRE                                        0x0

#define SCU_RAM_AGC_IF_IACCU_LO__A                                          0x831EB9
#define SCU_RAM_AGC_IF_IACCU_LO__W                                          8
#define SCU_RAM_AGC_IF_IACCU_LO__M                                          0xFF
#define SCU_RAM_AGC_IF_IACCU_LO__PRE                                        0x0

#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A                                      0x831EBA
#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W                                      15
#define SCU_RAM_AGC_IF_IACCU_HI_TGT__M                                      0x7FFF
#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE                                    0x0

#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A                                  0x831EBB
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W                                  15
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M                                  0x7FFF
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE                                0x0

#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A                                  0x831EBC
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W                                  15
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M                                  0x7FFF
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE                                0x0

#define SCU_RAM_AGC_RF_IACCU_HI__A                                          0x831EBD
#define SCU_RAM_AGC_RF_IACCU_HI__W                                          16
#define SCU_RAM_AGC_RF_IACCU_HI__M                                          0xFFFF
#define SCU_RAM_AGC_RF_IACCU_HI__PRE                                        0x0

#define SCU_RAM_AGC_RF_IACCU_LO__A                                          0x831EBE
#define SCU_RAM_AGC_RF_IACCU_LO__W                                          8
#define SCU_RAM_AGC_RF_IACCU_LO__M                                          0xFF
#define SCU_RAM_AGC_RF_IACCU_LO__PRE                                        0x0

#define SCU_RAM_AGC_RF_IACCU_HI_CO__A                                       0x831EBF
#define SCU_RAM_AGC_RF_IACCU_HI_CO__W                                       16
#define SCU_RAM_AGC_RF_IACCU_HI_CO__M                                       0xFFFF
#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE                                     0x0

#define SCU_RAM_SP__A                                                       0x831EC0
#define SCU_RAM_SP__W                                                       16
#define SCU_RAM_SP__M                                                       0xFFFF
#define SCU_RAM_SP__PRE                                                     0x0

#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A                                  0x831EC1
#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W                                  16
#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M                                  0xFFFF
#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE                                0x0

#define SCU_RAM_AGC_KI_MIN_IFGAIN__A                                        0x831EC2
#define SCU_RAM_AGC_KI_MIN_IFGAIN__W                                        16
#define SCU_RAM_AGC_KI_MIN_IFGAIN__M                                        0xFFFF
#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE                                      0x0

#define SCU_RAM_AGC_KI_MAX_IFGAIN__A                                        0x831EC3
#define SCU_RAM_AGC_KI_MAX_IFGAIN__W                                        16
#define SCU_RAM_AGC_KI_MAX_IFGAIN__M                                        0xFFFF
#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE                                      0x0

#define SCU_RAM_FEC_MEAS_COUNT__A                                           0x831EC4
#define SCU_RAM_FEC_MEAS_COUNT__W                                           16
#define SCU_RAM_FEC_MEAS_COUNT__M                                           0xFFFF
#define SCU_RAM_FEC_MEAS_COUNT__PRE                                         0x0

#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A                                0x831EC5
#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__W                                16
#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__M                                0xFFFF
#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__PRE                              0x0

#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__A                                0x831EC6
#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__W                                16
#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__M                                0xFFFF
#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__PRE                              0x0
#define SCU_RAM_GPIO__A                                                     0x831EC7
#define SCU_RAM_GPIO__W                                                     1
#define SCU_RAM_GPIO__M                                                     0x1
#define SCU_RAM_GPIO__PRE                                                   0x0

#define   SCU_RAM_GPIO_HW_LOCK_IND__B                                       0
#define   SCU_RAM_GPIO_HW_LOCK_IND__W                                       1
#define   SCU_RAM_GPIO_HW_LOCK_IND__M                                       0x1
#define   SCU_RAM_GPIO_HW_LOCK_IND__PRE                                     0x0
#define     SCU_RAM_GPIO_HW_LOCK_IND_DISABLE                                0x0
#define     SCU_RAM_GPIO_HW_LOCK_IND_ENABLE                                 0x1

#define SCU_RAM_AGC_CLP_CTRL_MODE__A                                        0x831EC8
#define SCU_RAM_AGC_CLP_CTRL_MODE__W                                        8
#define SCU_RAM_AGC_CLP_CTRL_MODE__M                                        0xFF
#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE                                      0x0

#define   SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B                           0
#define   SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W                           1
#define   SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M                           0x1
#define   SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE                         0x0
#define     SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_false                      0x0
#define     SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_true                       0x1

#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B                          1
#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W                          1
#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M                          0x2
#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE                        0x0
#define     SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE                0x0
#define     SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE               0x2

#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B                         2
#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W                         1
#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M                         0x4
#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE                       0x0
#define     SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE              0x0
#define     SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE               0x4

#define SCU_RAM_AGC_KI_MIN_RFGAIN__A                                        0x831EC9
#define SCU_RAM_AGC_KI_MIN_RFGAIN__W                                        16
#define SCU_RAM_AGC_KI_MIN_RFGAIN__M                                        0xFFFF
#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE                                      0x0

#define SCU_RAM_AGC_KI_MAX_RFGAIN__A                                        0x831ECA
#define SCU_RAM_AGC_KI_MAX_RFGAIN__W                                        16
#define SCU_RAM_AGC_KI_MAX_RFGAIN__M                                        0xFFFF
#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE                                      0x0

#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A                                   0x831ECB
#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W                                   16
#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M                                   0xFFFF
#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE                                 0x0

#define SCU_RAM_INHIBIT_1__A                                                0x831ECC
#define SCU_RAM_INHIBIT_1__W                                                16
#define SCU_RAM_INHIBIT_1__M                                                0xFFFF
#define SCU_RAM_INHIBIT_1__PRE                                              0x0

#define SCU_RAM_HTOL_BUF_0__A                                               0x831ECD
#define SCU_RAM_HTOL_BUF_0__W                                               16
#define SCU_RAM_HTOL_BUF_0__M                                               0xFFFF
#define SCU_RAM_HTOL_BUF_0__PRE                                             0x0

#define SCU_RAM_HTOL_BUF_1__A                                               0x831ECE
#define SCU_RAM_HTOL_BUF_1__W                                               16
#define SCU_RAM_HTOL_BUF_1__M                                               0xFFFF
#define SCU_RAM_HTOL_BUF_1__PRE                                             0x0

#define SCU_RAM_INHIBIT_2__A                                                0x831ECF
#define SCU_RAM_INHIBIT_2__W                                                16
#define SCU_RAM_INHIBIT_2__M                                                0xFFFF
#define SCU_RAM_INHIBIT_2__PRE                                              0x0

#define SCU_RAM_TR_SHORT_BUF_0__A                                           0x831ED0
#define SCU_RAM_TR_SHORT_BUF_0__W                                           16
#define SCU_RAM_TR_SHORT_BUF_0__M                                           0xFFFF
#define SCU_RAM_TR_SHORT_BUF_0__PRE                                         0x0

#define SCU_RAM_TR_SHORT_BUF_1__A                                           0x831ED1
#define SCU_RAM_TR_SHORT_BUF_1__W                                           16
#define SCU_RAM_TR_SHORT_BUF_1__M                                           0xFFFF
#define SCU_RAM_TR_SHORT_BUF_1__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_0__A                                            0x831ED2
#define SCU_RAM_TR_LONG_BUF_0__W                                            16
#define SCU_RAM_TR_LONG_BUF_0__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_0__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_1__A                                            0x831ED3
#define SCU_RAM_TR_LONG_BUF_1__W                                            16
#define SCU_RAM_TR_LONG_BUF_1__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_1__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_2__A                                            0x831ED4
#define SCU_RAM_TR_LONG_BUF_2__W                                            16
#define SCU_RAM_TR_LONG_BUF_2__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_2__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_3__A                                            0x831ED5
#define SCU_RAM_TR_LONG_BUF_3__W                                            16
#define SCU_RAM_TR_LONG_BUF_3__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_3__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_4__A                                            0x831ED6
#define SCU_RAM_TR_LONG_BUF_4__W                                            16
#define SCU_RAM_TR_LONG_BUF_4__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_4__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_5__A                                            0x831ED7
#define SCU_RAM_TR_LONG_BUF_5__W                                            16
#define SCU_RAM_TR_LONG_BUF_5__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_5__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_6__A                                            0x831ED8
#define SCU_RAM_TR_LONG_BUF_6__W                                            16
#define SCU_RAM_TR_LONG_BUF_6__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_6__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_7__A                                            0x831ED9
#define SCU_RAM_TR_LONG_BUF_7__W                                            16
#define SCU_RAM_TR_LONG_BUF_7__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_7__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_8__A                                            0x831EDA
#define SCU_RAM_TR_LONG_BUF_8__W                                            16
#define SCU_RAM_TR_LONG_BUF_8__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_8__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_9__A                                            0x831EDB
#define SCU_RAM_TR_LONG_BUF_9__W                                            16
#define SCU_RAM_TR_LONG_BUF_9__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_9__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_10__A                                           0x831EDC
#define SCU_RAM_TR_LONG_BUF_10__W                                           16
#define SCU_RAM_TR_LONG_BUF_10__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_10__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_11__A                                           0x831EDD
#define SCU_RAM_TR_LONG_BUF_11__W                                           16
#define SCU_RAM_TR_LONG_BUF_11__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_11__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_12__A                                           0x831EDE
#define SCU_RAM_TR_LONG_BUF_12__W                                           16
#define SCU_RAM_TR_LONG_BUF_12__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_12__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_13__A                                           0x831EDF
#define SCU_RAM_TR_LONG_BUF_13__W                                           16
#define SCU_RAM_TR_LONG_BUF_13__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_13__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_14__A                                           0x831EE0
#define SCU_RAM_TR_LONG_BUF_14__W                                           16
#define SCU_RAM_TR_LONG_BUF_14__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_14__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_15__A                                           0x831EE1
#define SCU_RAM_TR_LONG_BUF_15__W                                           16
#define SCU_RAM_TR_LONG_BUF_15__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_15__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_16__A                                           0x831EE2
#define SCU_RAM_TR_LONG_BUF_16__W                                           16
#define SCU_RAM_TR_LONG_BUF_16__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_16__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_17__A                                           0x831EE3
#define SCU_RAM_TR_LONG_BUF_17__W                                           16
#define SCU_RAM_TR_LONG_BUF_17__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_17__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_18__A                                           0x831EE4
#define SCU_RAM_TR_LONG_BUF_18__W                                           16
#define SCU_RAM_TR_LONG_BUF_18__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_18__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_19__A                                           0x831EE5
#define SCU_RAM_TR_LONG_BUF_19__W                                           16
#define SCU_RAM_TR_LONG_BUF_19__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_19__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_20__A                                           0x831EE6
#define SCU_RAM_TR_LONG_BUF_20__W                                           16
#define SCU_RAM_TR_LONG_BUF_20__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_20__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_21__A                                           0x831EE7
#define SCU_RAM_TR_LONG_BUF_21__W                                           16
#define SCU_RAM_TR_LONG_BUF_21__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_21__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_22__A                                           0x831EE8
#define SCU_RAM_TR_LONG_BUF_22__W                                           16
#define SCU_RAM_TR_LONG_BUF_22__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_22__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_23__A                                           0x831EE9
#define SCU_RAM_TR_LONG_BUF_23__W                                           16
#define SCU_RAM_TR_LONG_BUF_23__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_23__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_24__A                                           0x831EEA
#define SCU_RAM_TR_LONG_BUF_24__W                                           16
#define SCU_RAM_TR_LONG_BUF_24__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_24__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_25__A                                           0x831EEB
#define SCU_RAM_TR_LONG_BUF_25__W                                           16
#define SCU_RAM_TR_LONG_BUF_25__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_25__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_26__A                                           0x831EEC
#define SCU_RAM_TR_LONG_BUF_26__W                                           16
#define SCU_RAM_TR_LONG_BUF_26__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_26__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_27__A                                           0x831EED
#define SCU_RAM_TR_LONG_BUF_27__W                                           16
#define SCU_RAM_TR_LONG_BUF_27__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_27__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_28__A                                           0x831EEE
#define SCU_RAM_TR_LONG_BUF_28__W                                           16
#define SCU_RAM_TR_LONG_BUF_28__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_28__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_29__A                                           0x831EEF
#define SCU_RAM_TR_LONG_BUF_29__W                                           16
#define SCU_RAM_TR_LONG_BUF_29__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_29__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_30__A                                           0x831EF0
#define SCU_RAM_TR_LONG_BUF_30__W                                           16
#define SCU_RAM_TR_LONG_BUF_30__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_30__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_31__A                                           0x831EF1
#define SCU_RAM_TR_LONG_BUF_31__W                                           16
#define SCU_RAM_TR_LONG_BUF_31__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_31__PRE                                         0x0
#define SCU_RAM_ATV_AMS_MAX__A                                              0x831EF2
#define SCU_RAM_ATV_AMS_MAX__W                                              11
#define SCU_RAM_ATV_AMS_MAX__M                                              0x7FF
#define SCU_RAM_ATV_AMS_MAX__PRE                                            0x0

#define   SCU_RAM_ATV_AMS_MAX_AMS_MAX__B                                    0
#define   SCU_RAM_ATV_AMS_MAX_AMS_MAX__W                                    11
#define   SCU_RAM_ATV_AMS_MAX_AMS_MAX__M                                    0x7FF
#define   SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE                                  0x0

#define SCU_RAM_ATV_AMS_MIN__A                                              0x831EF3
#define SCU_RAM_ATV_AMS_MIN__W                                              11
#define SCU_RAM_ATV_AMS_MIN__M                                              0x7FF
#define SCU_RAM_ATV_AMS_MIN__PRE                                            0x0

#define   SCU_RAM_ATV_AMS_MIN_AMS_MIN__B                                    0
#define   SCU_RAM_ATV_AMS_MIN_AMS_MIN__W                                    11
#define   SCU_RAM_ATV_AMS_MIN_AMS_MIN__M                                    0x7FF
#define   SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE                                  0x0

#define SCU_RAM_ATV_FIELD_CNT__A                                            0x831EF4
#define SCU_RAM_ATV_FIELD_CNT__W                                            9
#define SCU_RAM_ATV_FIELD_CNT__M                                            0x1FF
#define SCU_RAM_ATV_FIELD_CNT__PRE                                          0x0

#define   SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B                                0
#define   SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W                                9
#define   SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M                                0x1FF
#define   SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE                              0x0

#define SCU_RAM_ATV_AAGC_FAST__A                                            0x831EF5
#define SCU_RAM_ATV_AAGC_FAST__W                                            1
#define SCU_RAM_ATV_AAGC_FAST__M                                            0x1
#define SCU_RAM_ATV_AAGC_FAST__PRE                                          0x0

#define   SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B                                0
#define   SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W                                1
#define   SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M                                0x1
#define   SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE                              0x0
#define     SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF                             0x0
#define     SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON                              0x1

#define SCU_RAM_ATV_AAGC_LP2__A                                             0x831EF6
#define SCU_RAM_ATV_AAGC_LP2__W                                             16
#define SCU_RAM_ATV_AAGC_LP2__M                                             0xFFFF
#define SCU_RAM_ATV_AAGC_LP2__PRE                                           0x0

#define   SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B                                  0
#define   SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W                                  16
#define   SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M                                  0xFFFF
#define   SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE                                0x0

#define SCU_RAM_ATV_BP_LVL__A                                               0x831EF7
#define SCU_RAM_ATV_BP_LVL__W                                               11
#define SCU_RAM_ATV_BP_LVL__M                                               0x7FF
#define SCU_RAM_ATV_BP_LVL__PRE                                             0x0

#define   SCU_RAM_ATV_BP_LVL_BP_LVL__B                                      0
#define   SCU_RAM_ATV_BP_LVL_BP_LVL__W                                      11
#define   SCU_RAM_ATV_BP_LVL_BP_LVL__M                                      0x7FF
#define   SCU_RAM_ATV_BP_LVL_BP_LVL__PRE                                    0x0

#define SCU_RAM_ATV_BP_RELY__A                                              0x831EF8
#define SCU_RAM_ATV_BP_RELY__W                                              8
#define SCU_RAM_ATV_BP_RELY__M                                              0xFF
#define SCU_RAM_ATV_BP_RELY__PRE                                            0x0

#define   SCU_RAM_ATV_BP_RELY_BP_RELY__B                                    0
#define   SCU_RAM_ATV_BP_RELY_BP_RELY__W                                    8
#define   SCU_RAM_ATV_BP_RELY_BP_RELY__M                                    0xFF
#define   SCU_RAM_ATV_BP_RELY_BP_RELY__PRE                                  0x0

#define SCU_RAM_ATV_BP_MTA__A                                               0x831EF9
#define SCU_RAM_ATV_BP_MTA__W                                               14
#define SCU_RAM_ATV_BP_MTA__M                                               0x3FFF
#define SCU_RAM_ATV_BP_MTA__PRE                                             0x0

#define   SCU_RAM_ATV_BP_MTA_BP_MTA__B                                      0
#define   SCU_RAM_ATV_BP_MTA_BP_MTA__W                                      14
#define   SCU_RAM_ATV_BP_MTA_BP_MTA__M                                      0x3FFF
#define   SCU_RAM_ATV_BP_MTA_BP_MTA__PRE                                    0x0

#define SCU_RAM_ATV_BP_REF__A                                               0x831EFA
#define SCU_RAM_ATV_BP_REF__W                                               11
#define SCU_RAM_ATV_BP_REF__M                                               0x7FF
#define SCU_RAM_ATV_BP_REF__PRE                                             0x0

#define   SCU_RAM_ATV_BP_REF_BP_REF__B                                      0
#define   SCU_RAM_ATV_BP_REF_BP_REF__W                                      11
#define   SCU_RAM_ATV_BP_REF_BP_REF__M                                      0x7FF
#define   SCU_RAM_ATV_BP_REF_BP_REF__PRE                                    0x0

#define SCU_RAM_ATV_BP_REF_MIN__A                                           0x831EFB
#define SCU_RAM_ATV_BP_REF_MIN__W                                           11
#define SCU_RAM_ATV_BP_REF_MIN__M                                           0x7FF
#define SCU_RAM_ATV_BP_REF_MIN__PRE                                         0x0

#define   SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B                              0
#define   SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W                              11
#define   SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M                              0x7FF
#define   SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE                            0x0

#define SCU_RAM_ATV_BP_REF_MAX__A                                           0x831EFC
#define SCU_RAM_ATV_BP_REF_MAX__W                                           11
#define SCU_RAM_ATV_BP_REF_MAX__M                                           0x7FF
#define SCU_RAM_ATV_BP_REF_MAX__PRE                                         0x0

#define   SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B                              0
#define   SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W                              11
#define   SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M                              0x7FF
#define   SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE                            0x0

#define SCU_RAM_ATV_BP_CNT__A                                               0x831EFD
#define SCU_RAM_ATV_BP_CNT__W                                               8
#define SCU_RAM_ATV_BP_CNT__M                                               0xFF
#define SCU_RAM_ATV_BP_CNT__PRE                                             0x0

#define   SCU_RAM_ATV_BP_CNT_BP_CNT__B                                      0
#define   SCU_RAM_ATV_BP_CNT_BP_CNT__W                                      8
#define   SCU_RAM_ATV_BP_CNT_BP_CNT__M                                      0xFF
#define   SCU_RAM_ATV_BP_CNT_BP_CNT__PRE                                    0x0

#define SCU_RAM_ATV_BP_XD_CNT__A                                            0x831EFE
#define SCU_RAM_ATV_BP_XD_CNT__W                                            12
#define SCU_RAM_ATV_BP_XD_CNT__M                                            0xFFF
#define SCU_RAM_ATV_BP_XD_CNT__PRE                                          0x0

#define   SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B                                0
#define   SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W                                12
#define   SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M                                0xFFF
#define   SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE                              0x0

#define SCU_RAM_ATV_PAGC_KI_MIN__A                                          0x831EFF
#define SCU_RAM_ATV_PAGC_KI_MIN__W                                          12
#define SCU_RAM_ATV_PAGC_KI_MIN__M                                          0xFFF
#define SCU_RAM_ATV_PAGC_KI_MIN__PRE                                        0x0

#define   SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B                            0
#define   SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W                            12
#define   SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M                            0xFFF
#define   SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE                          0x0

#define SCU_RAM_ATV_BPC_KI_MIN__A                                           0x831F00
#define SCU_RAM_ATV_BPC_KI_MIN__W                                           12
#define SCU_RAM_ATV_BPC_KI_MIN__M                                           0xFFF
#define SCU_RAM_ATV_BPC_KI_MIN__PRE                                         0x0

#define   SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B                              0
#define   SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W                              12
#define   SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M                              0xFFF
#define   SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE                            0x0

#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A                                0x831F01
#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__W                                16
#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__M                                0xFFFF
#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__PRE                              0x0

#define SCU_RAM_ORX_RF_RX_DATA_RATE__A                                      0x831F02
#define SCU_RAM_ORX_RF_RX_DATA_RATE__W                                      8
#define SCU_RAM_ORX_RF_RX_DATA_RATE__M                                      0xFF
#define SCU_RAM_ORX_RF_RX_DATA_RATE__PRE                                    0x0
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC                      0x0
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC                      0x1
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT                  0x40
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT                  0x41
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC                      0x80
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC                      0x81
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC                      0xC0
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC                      0xC1

#define SCU_RAM_ORX_SCU_STATE__A                                            0x831F03
#define SCU_RAM_ORX_SCU_STATE__W                                            8
#define SCU_RAM_ORX_SCU_STATE__M                                            0xFF
#define SCU_RAM_ORX_SCU_STATE__PRE                                          0x0
#define   SCU_RAM_ORX_SCU_STATE_RESET                                       0x0
#define   SCU_RAM_ORX_SCU_STATE_AGN_HUNT                                    0x1
#define   SCU_RAM_ORX_SCU_STATE_DGN_HUNT                                    0x2
#define   SCU_RAM_ORX_SCU_STATE_AGC_HUNT                                    0x3
#define   SCU_RAM_ORX_SCU_STATE_FRQ_HUNT                                    0x4
#define   SCU_RAM_ORX_SCU_STATE_PHA_HUNT                                    0x8
#define   SCU_RAM_ORX_SCU_STATE_TIM_HUNT                                    0x10
#define   SCU_RAM_ORX_SCU_STATE_EQU_HUNT                                    0x20
#define   SCU_RAM_ORX_SCU_STATE_EQT_HUNT                                    0x30
#define   SCU_RAM_ORX_SCU_STATE_SYNC                                        0x40

#define SCU_RAM_ORX_SCU_LOCK__A                                             0x831F04
#define SCU_RAM_ORX_SCU_LOCK__W                                             16
#define SCU_RAM_ORX_SCU_LOCK__M                                             0xFFFF
#define SCU_RAM_ORX_SCU_LOCK__PRE                                           0x0

#define SCU_RAM_ORX_TARGET_MODE__A                                          0x831F05
#define SCU_RAM_ORX_TARGET_MODE__W                                          2
#define SCU_RAM_ORX_TARGET_MODE__M                                          0x3
#define SCU_RAM_ORX_TARGET_MODE__PRE                                        0x0
#define   SCU_RAM_ORX_TARGET_MODE_1544KBPS                                  0x0
#define   SCU_RAM_ORX_TARGET_MODE_3088KBPS                                  0x1
#define   SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT                             0x2
#define   SCU_RAM_ORX_TARGET_MODE_2048KBPS_RO                               0x3

#define SCU_RAM_ORX_MER_MIN_DB__A                                           0x831F06
#define SCU_RAM_ORX_MER_MIN_DB__W                                           8
#define SCU_RAM_ORX_MER_MIN_DB__M                                           0xFF
#define SCU_RAM_ORX_MER_MIN_DB__PRE                                         0x0

#define SCU_RAM_ORX_RF_GAIN__A                                              0x831F07
#define SCU_RAM_ORX_RF_GAIN__W                                              16
#define SCU_RAM_ORX_RF_GAIN__M                                              0xFFFF
#define SCU_RAM_ORX_RF_GAIN__PRE                                            0x0

#define SCU_RAM_ORX_RF_GAIN_MIN__A                                          0x831F08
#define SCU_RAM_ORX_RF_GAIN_MIN__W                                          16
#define SCU_RAM_ORX_RF_GAIN_MIN__M                                          0xFFFF
#define SCU_RAM_ORX_RF_GAIN_MIN__PRE                                        0x0

#define SCU_RAM_ORX_RF_GAIN_MAX__A                                          0x831F09
#define SCU_RAM_ORX_RF_GAIN_MAX__W                                          16
#define SCU_RAM_ORX_RF_GAIN_MAX__M                                          0xFFFF
#define SCU_RAM_ORX_RF_GAIN_MAX__PRE                                        0x0

#define SCU_RAM_ORX_IF_GAIN__A                                              0x831F0A
#define SCU_RAM_ORX_IF_GAIN__W                                              16
#define SCU_RAM_ORX_IF_GAIN__M                                              0xFFFF
#define SCU_RAM_ORX_IF_GAIN__PRE                                            0x0

#define SCU_RAM_ORX_IF_GAIN_MIN__A                                          0x831F0B
#define SCU_RAM_ORX_IF_GAIN_MIN__W                                          16
#define SCU_RAM_ORX_IF_GAIN_MIN__M                                          0xFFFF
#define SCU_RAM_ORX_IF_GAIN_MIN__PRE                                        0x0

#define SCU_RAM_ORX_IF_GAIN_MAX__A                                          0x831F0C
#define SCU_RAM_ORX_IF_GAIN_MAX__W                                          16
#define SCU_RAM_ORX_IF_GAIN_MAX__M                                          0xFFFF
#define SCU_RAM_ORX_IF_GAIN_MAX__PRE                                        0x0

#define SCU_RAM_ORX_AGN_HEADR__A                                            0x831F0D
#define SCU_RAM_ORX_AGN_HEADR__W                                            16
#define SCU_RAM_ORX_AGN_HEADR__M                                            0xFFFF
#define SCU_RAM_ORX_AGN_HEADR__PRE                                          0x0

#define SCU_RAM_ORX_AGN_HEADR_STP__A                                        0x831F0E
#define SCU_RAM_ORX_AGN_HEADR_STP__W                                        8
#define SCU_RAM_ORX_AGN_HEADR_STP__M                                        0xFF
#define SCU_RAM_ORX_AGN_HEADR_STP__PRE                                      0x0

#define SCU_RAM_ORX_AGN_KI__A                                               0x831F0F
#define SCU_RAM_ORX_AGN_KI__W                                               8
#define SCU_RAM_ORX_AGN_KI__M                                               0xFF
#define SCU_RAM_ORX_AGN_KI__PRE                                             0x0

#define SCU_RAM_ORX_AGN_LOCK_TH__A                                          0x831F10
#define SCU_RAM_ORX_AGN_LOCK_TH__W                                          16
#define SCU_RAM_ORX_AGN_LOCK_TH__M                                          0xFFFF
#define SCU_RAM_ORX_AGN_LOCK_TH__PRE                                        0x0

#define SCU_RAM_ORX_AGN_LOCK_WD__A                                          0x831F11
#define SCU_RAM_ORX_AGN_LOCK_WD__W                                          16
#define SCU_RAM_ORX_AGN_LOCK_WD__M                                          0xFFFF
#define SCU_RAM_ORX_AGN_LOCK_WD__PRE                                        0x0

#define SCU_RAM_ORX_AGN_ONLOCK_TTH__A                                       0x831F12
#define SCU_RAM_ORX_AGN_ONLOCK_TTH__W                                       16
#define SCU_RAM_ORX_AGN_ONLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_AGN_ONLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_AGN_UNLOCK_TTH__A                                       0x831F13
#define SCU_RAM_ORX_AGN_UNLOCK_TTH__W                                       16
#define SCU_RAM_ORX_AGN_UNLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_AGN_UNLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_AGN_LOCK_TOTH__A                                        0x831F14
#define SCU_RAM_ORX_AGN_LOCK_TOTH__W                                        16
#define SCU_RAM_ORX_AGN_LOCK_TOTH__M                                        0xFFFF
#define SCU_RAM_ORX_AGN_LOCK_TOTH__PRE                                      0x0

#define SCU_RAM_ORX_AGN_LOCK_MASK__A                                        0x831F15
#define SCU_RAM_ORX_AGN_LOCK_MASK__W                                        8
#define SCU_RAM_ORX_AGN_LOCK_MASK__M                                        0xFF
#define SCU_RAM_ORX_AGN_LOCK_MASK__PRE                                      0x0

#define SCU_RAM_ORX_DGN__A                                                  0x831F16
#define SCU_RAM_ORX_DGN__W                                                  16
#define SCU_RAM_ORX_DGN__M                                                  0xFFFF
#define SCU_RAM_ORX_DGN__PRE                                                0x0

#define SCU_RAM_ORX_DGN_MIN__A                                              0x831F17
#define SCU_RAM_ORX_DGN_MIN__W                                              16
#define SCU_RAM_ORX_DGN_MIN__M                                              0xFFFF
#define SCU_RAM_ORX_DGN_MIN__PRE                                            0x0

#define SCU_RAM_ORX_DGN_MAX__A                                              0x831F18
#define SCU_RAM_ORX_DGN_MAX__W                                              16
#define SCU_RAM_ORX_DGN_MAX__M                                              0xFFFF
#define SCU_RAM_ORX_DGN_MAX__PRE                                            0x0

#define SCU_RAM_ORX_DGN_AMP__A                                              0x831F19
#define SCU_RAM_ORX_DGN_AMP__W                                              16
#define SCU_RAM_ORX_DGN_AMP__M                                              0xFFFF
#define SCU_RAM_ORX_DGN_AMP__PRE                                            0x0

#define SCU_RAM_ORX_DGN_AMPTARGET__A                                        0x831F1A
#define SCU_RAM_ORX_DGN_AMPTARGET__W                                        16
#define SCU_RAM_ORX_DGN_AMPTARGET__M                                        0xFFFF
#define SCU_RAM_ORX_DGN_AMPTARGET__PRE                                      0x0

#define SCU_RAM_ORX_DGN_KI__A                                               0x831F1B
#define SCU_RAM_ORX_DGN_KI__W                                               8
#define SCU_RAM_ORX_DGN_KI__M                                               0xFF
#define SCU_RAM_ORX_DGN_KI__PRE                                             0x0

#define SCU_RAM_ORX_DGN_LOCK_TH__A                                          0x831F1C
#define SCU_RAM_ORX_DGN_LOCK_TH__W                                          16
#define SCU_RAM_ORX_DGN_LOCK_TH__M                                          0xFFFF
#define SCU_RAM_ORX_DGN_LOCK_TH__PRE                                        0x0

#define SCU_RAM_ORX_DGN_LOCK_WD__A                                          0x831F1D
#define SCU_RAM_ORX_DGN_LOCK_WD__W                                          16
#define SCU_RAM_ORX_DGN_LOCK_WD__M                                          0xFFFF
#define SCU_RAM_ORX_DGN_LOCK_WD__PRE                                        0x0

#define SCU_RAM_ORX_DGN_ONLOCK_TTH__A                                       0x831F1E
#define SCU_RAM_ORX_DGN_ONLOCK_TTH__W                                       16
#define SCU_RAM_ORX_DGN_ONLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_DGN_ONLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_DGN_UNLOCK_TTH__A                                       0x831F1F
#define SCU_RAM_ORX_DGN_UNLOCK_TTH__W                                       16
#define SCU_RAM_ORX_DGN_UNLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_DGN_UNLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_DGN_LOCK_TOTH__A                                        0x831F20
#define SCU_RAM_ORX_DGN_LOCK_TOTH__W                                        16
#define SCU_RAM_ORX_DGN_LOCK_TOTH__M                                        0xFFFF
#define SCU_RAM_ORX_DGN_LOCK_TOTH__PRE                                      0x0

#define SCU_RAM_ORX_DGN_LOCK_MASK__A                                        0x831F21
#define SCU_RAM_ORX_DGN_LOCK_MASK__W                                        8
#define SCU_RAM_ORX_DGN_LOCK_MASK__M                                        0xFF
#define SCU_RAM_ORX_DGN_LOCK_MASK__PRE                                      0x0

#define SCU_RAM_ORX_FREQ_GAIN_CORR__A                                       0x831F22
#define SCU_RAM_ORX_FREQ_GAIN_CORR__W                                       8
#define SCU_RAM_ORX_FREQ_GAIN_CORR__M                                       0xFF
#define SCU_RAM_ORX_FREQ_GAIN_CORR__PRE                                     0x0
#define   SCU_RAM_ORX_FREQ_GAIN_CORR_1544KBPS                               0x60
#define   SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS                               0x80
#define   SCU_RAM_ORX_FREQ_GAIN_CORR_3088KBPS                               0xC0

#define SCU_RAM_ORX_FRQ_OFFSET__A                                           0x831F23
#define SCU_RAM_ORX_FRQ_OFFSET__W                                           16
#define SCU_RAM_ORX_FRQ_OFFSET__M                                           0xFFFF
#define SCU_RAM_ORX_FRQ_OFFSET__PRE                                         0x0

#define SCU_RAM_ORX_FRQ_OFFSET_MAX__A                                       0x831F24
#define SCU_RAM_ORX_FRQ_OFFSET_MAX__W                                       15
#define SCU_RAM_ORX_FRQ_OFFSET_MAX__M                                       0x7FFF
#define SCU_RAM_ORX_FRQ_OFFSET_MAX__PRE                                     0x0

#define SCU_RAM_ORX_FRQ_KI__A                                               0x831F25
#define SCU_RAM_ORX_FRQ_KI__W                                               8
#define SCU_RAM_ORX_FRQ_KI__M                                               0xFF
#define SCU_RAM_ORX_FRQ_KI__PRE                                             0x0

#define SCU_RAM_ORX_FRQ_DIFF__A                                             0x831F26
#define SCU_RAM_ORX_FRQ_DIFF__W                                             16
#define SCU_RAM_ORX_FRQ_DIFF__M                                             0xFFFF
#define SCU_RAM_ORX_FRQ_DIFF__PRE                                           0x0

#define SCU_RAM_ORX_FRQ_LOCK_TH__A                                          0x831F27
#define SCU_RAM_ORX_FRQ_LOCK_TH__W                                          16
#define SCU_RAM_ORX_FRQ_LOCK_TH__M                                          0xFFFF
#define SCU_RAM_ORX_FRQ_LOCK_TH__PRE                                        0x0

#define SCU_RAM_ORX_FRQ_LOCK_WD__A                                          0x831F28
#define SCU_RAM_ORX_FRQ_LOCK_WD__W                                          16
#define SCU_RAM_ORX_FRQ_LOCK_WD__M                                          0xFFFF
#define SCU_RAM_ORX_FRQ_LOCK_WD__PRE                                        0x0

#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__A                                       0x831F29
#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__W                                       16
#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__A                                       0x831F2A
#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__W                                       16
#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_FRQ_LOCK_TOTH__A                                        0x831F2B
#define SCU_RAM_ORX_FRQ_LOCK_TOTH__W                                        16
#define SCU_RAM_ORX_FRQ_LOCK_TOTH__M                                        0xFFFF
#define SCU_RAM_ORX_FRQ_LOCK_TOTH__PRE                                      0x0

#define SCU_RAM_ORX_FRQ_LOCK_MASK__A                                        0x831F2C
#define SCU_RAM_ORX_FRQ_LOCK_MASK__W                                        8
#define SCU_RAM_ORX_FRQ_LOCK_MASK__M                                        0xFF
#define SCU_RAM_ORX_FRQ_LOCK_MASK__PRE                                      0x0

#define SCU_RAM_ORX_PHA_DIFF__A                                             0x831F2D
#define SCU_RAM_ORX_PHA_DIFF__W                                             16
#define SCU_RAM_ORX_PHA_DIFF__M                                             0xFFFF
#define SCU_RAM_ORX_PHA_DIFF__PRE                                           0x0

#define SCU_RAM_ORX_PHA_LOCK_TH__A                                          0x831F2E
#define SCU_RAM_ORX_PHA_LOCK_TH__W                                          16
#define SCU_RAM_ORX_PHA_LOCK_TH__M                                          0xFFFF
#define SCU_RAM_ORX_PHA_LOCK_TH__PRE                                        0x0

#define SCU_RAM_ORX_PHA_LOCK_WD__A                                          0x831F2F
#define SCU_RAM_ORX_PHA_LOCK_WD__W                                          16
#define SCU_RAM_ORX_PHA_LOCK_WD__M                                          0xFFFF
#define SCU_RAM_ORX_PHA_LOCK_WD__PRE                                        0x0

#define SCU_RAM_ORX_PHA_ONLOCK_TTH__A                                       0x831F30
#define SCU_RAM_ORX_PHA_ONLOCK_TTH__W                                       16
#define SCU_RAM_ORX_PHA_ONLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_PHA_ONLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_PHA_UNLOCK_TTH__A                                       0x831F31
#define SCU_RAM_ORX_PHA_UNLOCK_TTH__W                                       16
#define SCU_RAM_ORX_PHA_UNLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_PHA_UNLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_PHA_LOCK_TOTH__A                                        0x831F32
#define SCU_RAM_ORX_PHA_LOCK_TOTH__W                                        16
#define SCU_RAM_ORX_PHA_LOCK_TOTH__M                                        0xFFFF
#define SCU_RAM_ORX_PHA_LOCK_TOTH__PRE                                      0x0

#define SCU_RAM_ORX_PHA_LOCK_MASK__A                                        0x831F33
#define SCU_RAM_ORX_PHA_LOCK_MASK__W                                        8
#define SCU_RAM_ORX_PHA_LOCK_MASK__M                                        0xFF
#define SCU_RAM_ORX_PHA_LOCK_MASK__PRE                                      0x0

#define SCU_RAM_ORX_TIM_OFFSET__A                                           0x831F34
#define SCU_RAM_ORX_TIM_OFFSET__W                                           16
#define SCU_RAM_ORX_TIM_OFFSET__M                                           0xFFFF
#define SCU_RAM_ORX_TIM_OFFSET__PRE                                         0x0

#define SCU_RAM_ORX_TIM_DIFF__A                                             0x831F35
#define SCU_RAM_ORX_TIM_DIFF__W                                             16
#define SCU_RAM_ORX_TIM_DIFF__M                                             0xFFFF
#define SCU_RAM_ORX_TIM_DIFF__PRE                                           0x0

#define SCU_RAM_ORX_TIM_LOCK_TH__A                                          0x831F36
#define SCU_RAM_ORX_TIM_LOCK_TH__W                                          16
#define SCU_RAM_ORX_TIM_LOCK_TH__M                                          0xFFFF
#define SCU_RAM_ORX_TIM_LOCK_TH__PRE                                        0x0

#define SCU_RAM_ORX_TIM_LOCK_WD__A                                          0x831F37
#define SCU_RAM_ORX_TIM_LOCK_WD__W                                          16
#define SCU_RAM_ORX_TIM_LOCK_WD__M                                          0xFFFF
#define SCU_RAM_ORX_TIM_LOCK_WD__PRE                                        0x0

#define SCU_RAM_ORX_TIM_ONLOCK_TTH__A                                       0x831F38
#define SCU_RAM_ORX_TIM_ONLOCK_TTH__W                                       16
#define SCU_RAM_ORX_TIM_ONLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_TIM_ONLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_TIM_UNLOCK_TTH__A                                       0x831F39
#define SCU_RAM_ORX_TIM_UNLOCK_TTH__W                                       16
#define SCU_RAM_ORX_TIM_UNLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_TIM_UNLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_TIM_LOCK_TOTH__A                                        0x831F3A
#define SCU_RAM_ORX_TIM_LOCK_TOTH__W                                        16
#define SCU_RAM_ORX_TIM_LOCK_TOTH__M                                        0xFFFF
#define SCU_RAM_ORX_TIM_LOCK_TOTH__PRE                                      0x0

#define SCU_RAM_ORX_TIM_LOCK_MASK__A                                        0x831F3B
#define SCU_RAM_ORX_TIM_LOCK_MASK__W                                        8
#define SCU_RAM_ORX_TIM_LOCK_MASK__M                                        0xFF
#define SCU_RAM_ORX_TIM_LOCK_MASK__PRE                                      0x0

#define SCU_RAM_ORX_EQU_DIFF__A                                             0x831F3C
#define SCU_RAM_ORX_EQU_DIFF__W                                             16
#define SCU_RAM_ORX_EQU_DIFF__M                                             0xFFFF
#define SCU_RAM_ORX_EQU_DIFF__PRE                                           0x0

#define SCU_RAM_ORX_EQU_LOCK_TH__A                                          0x831F3D
#define SCU_RAM_ORX_EQU_LOCK_TH__W                                          16
#define SCU_RAM_ORX_EQU_LOCK_TH__M                                          0xFFFF
#define SCU_RAM_ORX_EQU_LOCK_TH__PRE                                        0x0

#define SCU_RAM_ORX_EQU_LOCK_WD__A                                          0x831F3E
#define SCU_RAM_ORX_EQU_LOCK_WD__W                                          16
#define SCU_RAM_ORX_EQU_LOCK_WD__M                                          0xFFFF
#define SCU_RAM_ORX_EQU_LOCK_WD__PRE                                        0x0

#define SCU_RAM_ORX_EQU_ONLOCK_TTH__A                                       0x831F3F
#define SCU_RAM_ORX_EQU_ONLOCK_TTH__W                                       16
#define SCU_RAM_ORX_EQU_ONLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_EQU_ONLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_EQU_UNLOCK_TTH__A                                       0x831F40
#define SCU_RAM_ORX_EQU_UNLOCK_TTH__W                                       16
#define SCU_RAM_ORX_EQU_UNLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_EQU_UNLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_EQU_LOCK_TOTH__A                                        0x831F41
#define SCU_RAM_ORX_EQU_LOCK_TOTH__W                                        16
#define SCU_RAM_ORX_EQU_LOCK_TOTH__M                                        0xFFFF
#define SCU_RAM_ORX_EQU_LOCK_TOTH__PRE                                      0x0

#define SCU_RAM_ORX_EQU_LOCK_MASK__A                                        0x831F42
#define SCU_RAM_ORX_EQU_LOCK_MASK__W                                        8
#define SCU_RAM_ORX_EQU_LOCK_MASK__M                                        0xFF
#define SCU_RAM_ORX_EQU_LOCK_MASK__PRE                                      0x0

#define SCU_RAM_ORX_FLT_FRQ__A                                              0x831F43
#define SCU_RAM_ORX_FLT_FRQ__W                                              16
#define SCU_RAM_ORX_FLT_FRQ__M                                              0xFFFF
#define SCU_RAM_ORX_FLT_FRQ__PRE                                            0x0
#define SCU_RAM_ORX_RST_CPH__A                                              0x831F44
#define SCU_RAM_ORX_RST_CPH__W                                              4
#define SCU_RAM_ORX_RST_CPH__M                                              0xF
#define SCU_RAM_ORX_RST_CPH__PRE                                            0x0

#define   SCU_RAM_ORX_RST_CPH_RST_CPH__B                                    0
#define   SCU_RAM_ORX_RST_CPH_RST_CPH__W                                    4
#define   SCU_RAM_ORX_RST_CPH_RST_CPH__M                                    0xF
#define   SCU_RAM_ORX_RST_CPH_RST_CPH__PRE                                  0x0

#define SCU_RAM_ORX_RST_CTI__A                                              0x831F45
#define SCU_RAM_ORX_RST_CTI__W                                              4
#define SCU_RAM_ORX_RST_CTI__M                                              0xF
#define SCU_RAM_ORX_RST_CTI__PRE                                            0x0

#define   SCU_RAM_ORX_RST_CTI_RST_CTI__B                                    0
#define   SCU_RAM_ORX_RST_CTI_RST_CTI__W                                    4
#define   SCU_RAM_ORX_RST_CTI_RST_CTI__M                                    0xF
#define   SCU_RAM_ORX_RST_CTI_RST_CTI__PRE                                  0x0

#define SCU_RAM_ORX_RST_KRN__A                                              0x831F46
#define SCU_RAM_ORX_RST_KRN__W                                              4
#define SCU_RAM_ORX_RST_KRN__M                                              0xF
#define SCU_RAM_ORX_RST_KRN__PRE                                            0x0

#define   SCU_RAM_ORX_RST_KRN_RST_KRN__B                                    0
#define   SCU_RAM_ORX_RST_KRN_RST_KRN__W                                    4
#define   SCU_RAM_ORX_RST_KRN_RST_KRN__M                                    0xF
#define   SCU_RAM_ORX_RST_KRN_RST_KRN__PRE                                  0x0

#define SCU_RAM_ORX_RST_KRP__A                                              0x831F47
#define SCU_RAM_ORX_RST_KRP__W                                              4
#define SCU_RAM_ORX_RST_KRP__M                                              0xF
#define SCU_RAM_ORX_RST_KRP__PRE                                            0x0

#define   SCU_RAM_ORX_RST_KRP_RST_KRP__B                                    0
#define   SCU_RAM_ORX_RST_KRP_RST_KRP__W                                    4
#define   SCU_RAM_ORX_RST_KRP_RST_KRP__M                                    0xF
#define   SCU_RAM_ORX_RST_KRP_RST_KRP__PRE                                  0x0

#define SCU_RAM_ATV_STANDARD__A                                             0x831F48
#define SCU_RAM_ATV_STANDARD__W                                             12
#define SCU_RAM_ATV_STANDARD__M                                             0xFFF
#define SCU_RAM_ATV_STANDARD__PRE                                           0x0

#define   SCU_RAM_ATV_STANDARD_STANDARD__B                                  0
#define   SCU_RAM_ATV_STANDARD_STANDARD__W                                  12
#define   SCU_RAM_ATV_STANDARD_STANDARD__M                                  0xFFF
#define   SCU_RAM_ATV_STANDARD_STANDARD__PRE                                0x0
#define     SCU_RAM_ATV_STANDARD_STANDARD_MN                                0x2
#define     SCU_RAM_ATV_STANDARD_STANDARD_B                                 0x103
#define     SCU_RAM_ATV_STANDARD_STANDARD_G                                 0x3
#define     SCU_RAM_ATV_STANDARD_STANDARD_DK                                0x4
#define     SCU_RAM_ATV_STANDARD_STANDARD_L                                 0x9
#define     SCU_RAM_ATV_STANDARD_STANDARD_LP                                0x109
#define     SCU_RAM_ATV_STANDARD_STANDARD_I                                 0xA
#define     SCU_RAM_ATV_STANDARD_STANDARD_FM                                0x40

#define SCU_RAM_ATV_DETECT__A                                               0x831F49
#define SCU_RAM_ATV_DETECT__W                                               1
#define SCU_RAM_ATV_DETECT__M                                               0x1
#define SCU_RAM_ATV_DETECT__PRE                                             0x0

#define   SCU_RAM_ATV_DETECT_DETECT__B                                      0
#define   SCU_RAM_ATV_DETECT_DETECT__W                                      1
#define   SCU_RAM_ATV_DETECT_DETECT__M                                      0x1
#define   SCU_RAM_ATV_DETECT_DETECT__PRE                                    0x0
#define     SCU_RAM_ATV_DETECT_DETECT_false                                 0x0
#define     SCU_RAM_ATV_DETECT_DETECT_true                                  0x1

#define SCU_RAM_ATV_DETECT_TH__A                                            0x831F4A
#define SCU_RAM_ATV_DETECT_TH__W                                            8
#define SCU_RAM_ATV_DETECT_TH__M                                            0xFF
#define SCU_RAM_ATV_DETECT_TH__PRE                                          0x0

#define   SCU_RAM_ATV_DETECT_TH_DETECT_TH__B                                0
#define   SCU_RAM_ATV_DETECT_TH_DETECT_TH__W                                8
#define   SCU_RAM_ATV_DETECT_TH_DETECT_TH__M                                0xFF
#define   SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE                              0x0

#define SCU_RAM_ATV_LOCK__A                                                 0x831F4B
#define SCU_RAM_ATV_LOCK__W                                                 2
#define SCU_RAM_ATV_LOCK__M                                                 0x3
#define SCU_RAM_ATV_LOCK__PRE                                               0x0

#define   SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B                                   0
#define   SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W                                   1
#define   SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M                                   0x1
#define   SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE                                 0x0
#define     SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK                            0x0
#define     SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK                               0x1

#define   SCU_RAM_ATV_LOCK_SYNC_FLAG__B                                     1
#define   SCU_RAM_ATV_LOCK_SYNC_FLAG__W                                     1
#define   SCU_RAM_ATV_LOCK_SYNC_FLAG__M                                     0x2
#define   SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE                                   0x0
#define     SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC                              0x0
#define     SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC                                 0x2

#define SCU_RAM_ATV_CR_LOCK__A                                              0x831F4C
#define SCU_RAM_ATV_CR_LOCK__W                                              11
#define SCU_RAM_ATV_CR_LOCK__M                                              0x7FF
#define SCU_RAM_ATV_CR_LOCK__PRE                                            0x0

#define   SCU_RAM_ATV_CR_LOCK_CR_LOCK__B                                    0
#define   SCU_RAM_ATV_CR_LOCK_CR_LOCK__W                                    11
#define   SCU_RAM_ATV_CR_LOCK_CR_LOCK__M                                    0x7FF
#define   SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE                                  0x0

#define SCU_RAM_ATV_AGC_MODE__A                                             0x831F4D
#define SCU_RAM_ATV_AGC_MODE__W                                             8
#define SCU_RAM_ATV_AGC_MODE__M                                             0xFF
#define SCU_RAM_ATV_AGC_MODE__PRE                                           0x0

#define   SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B                                  2
#define   SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W                                  1
#define   SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M                                  0x4
#define   SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE                                0x0
#define     SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST                          0x0
#define     SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW                          0x4

#define   SCU_RAM_ATV_AGC_MODE_BP_EN__B                                     3
#define   SCU_RAM_ATV_AGC_MODE_BP_EN__W                                     1
#define   SCU_RAM_ATV_AGC_MODE_BP_EN__M                                     0x8
#define   SCU_RAM_ATV_AGC_MODE_BP_EN__PRE                                   0x0
#define     SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE                          0x0
#define     SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE                           0x8

#define   SCU_RAM_ATV_AGC_MODE_SIF_STD__B                                   4
#define   SCU_RAM_ATV_AGC_MODE_SIF_STD__W                                   2
#define   SCU_RAM_ATV_AGC_MODE_SIF_STD__M                                   0x30
#define   SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE                                 0x0
#define     SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF                        0x0
#define     SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM                         0x10
#define     SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM                         0x20

#define   SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B                              6
#define   SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W                              1
#define   SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M                              0x40
#define   SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE                            0x0
#define     SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE                  0x0
#define     SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE                   0x40

#define   SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B                                 7
#define   SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W                                 1
#define   SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M                                 0x80
#define   SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE                               0x0
#define     SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE                       0x0
#define     SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE                      0x80

#define SCU_RAM_ATV_RSV_01__A                                               0x831F4E
#define SCU_RAM_ATV_RSV_01__W                                               16
#define SCU_RAM_ATV_RSV_01__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_01__PRE                                             0x0

#define SCU_RAM_ATV_RSV_02__A                                               0x831F4F
#define SCU_RAM_ATV_RSV_02__W                                               16
#define SCU_RAM_ATV_RSV_02__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_02__PRE                                             0x0

#define SCU_RAM_ATV_RSV_03__A                                               0x831F50
#define SCU_RAM_ATV_RSV_03__W                                               16
#define SCU_RAM_ATV_RSV_03__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_03__PRE                                             0x0

#define SCU_RAM_ATV_RSV_04__A                                               0x831F51
#define SCU_RAM_ATV_RSV_04__W                                               16
#define SCU_RAM_ATV_RSV_04__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_04__PRE                                             0x0
#define SCU_RAM_ATV_FAGC_TH_RED__A                                          0x831F52
#define SCU_RAM_ATV_FAGC_TH_RED__W                                          8
#define SCU_RAM_ATV_FAGC_TH_RED__M                                          0xFF
#define SCU_RAM_ATV_FAGC_TH_RED__PRE                                        0x0

#define   SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B                            0
#define   SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W                            8
#define   SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M                            0xFF
#define   SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE                          0x0

#define SCU_RAM_ATV_AMS_MAX_REF__A                                          0x831F53
#define SCU_RAM_ATV_AMS_MAX_REF__W                                          11
#define SCU_RAM_ATV_AMS_MAX_REF__M                                          0x7FF
#define SCU_RAM_ATV_AMS_MAX_REF__PRE                                        0x0

#define   SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B                            0
#define   SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W                            11
#define   SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M                            0x7FF
#define   SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE                          0x0
#define     SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN                       0x2BC
#define     SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK                          0x2D0
#define     SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I                           0x314
#define     SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP                         0x28A

#define SCU_RAM_ATV_ACT_AMX__A                                              0x831F54
#define SCU_RAM_ATV_ACT_AMX__W                                              11
#define SCU_RAM_ATV_ACT_AMX__M                                              0x7FF
#define SCU_RAM_ATV_ACT_AMX__PRE                                            0x0

#define   SCU_RAM_ATV_ACT_AMX_ACT_AMX__B                                    0
#define   SCU_RAM_ATV_ACT_AMX_ACT_AMX__W                                    11
#define   SCU_RAM_ATV_ACT_AMX_ACT_AMX__M                                    0x7FF
#define   SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE                                  0x0

#define SCU_RAM_ATV_ACT_AMI__A                                              0x831F55
#define SCU_RAM_ATV_ACT_AMI__W                                              11
#define SCU_RAM_ATV_ACT_AMI__M                                              0x7FF
#define SCU_RAM_ATV_ACT_AMI__PRE                                            0x0

#define   SCU_RAM_ATV_ACT_AMI_ACT_AMI__B                                    0
#define   SCU_RAM_ATV_ACT_AMI_ACT_AMI__W                                    11
#define   SCU_RAM_ATV_ACT_AMI_ACT_AMI__M                                    0x7FF
#define   SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE                                  0x0

#define SCU_RAM_ATV_RSV_05__A                                               0x831F56
#define SCU_RAM_ATV_RSV_05__W                                               16
#define SCU_RAM_ATV_RSV_05__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_05__PRE                                             0x0

#define SCU_RAM_ATV_RSV_06__A                                               0x831F57
#define SCU_RAM_ATV_RSV_06__W                                               16
#define SCU_RAM_ATV_RSV_06__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_06__PRE                                             0x0

#define SCU_RAM_ATV_RSV_07__A                                               0x831F58
#define SCU_RAM_ATV_RSV_07__W                                               16
#define SCU_RAM_ATV_RSV_07__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_07__PRE                                             0x0

#define SCU_RAM_ATV_RSV_08__A                                               0x831F59
#define SCU_RAM_ATV_RSV_08__W                                               16
#define SCU_RAM_ATV_RSV_08__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_08__PRE                                             0x0

#define SCU_RAM_ATV_RSV_09__A                                               0x831F5A
#define SCU_RAM_ATV_RSV_09__W                                               16
#define SCU_RAM_ATV_RSV_09__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_09__PRE                                             0x0

#define SCU_RAM_ATV_RSV_10__A                                               0x831F5B
#define SCU_RAM_ATV_RSV_10__W                                               16
#define SCU_RAM_ATV_RSV_10__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_10__PRE                                             0x0

#define SCU_RAM_ATV_RSV_11__A                                               0x831F5C
#define SCU_RAM_ATV_RSV_11__W                                               16
#define SCU_RAM_ATV_RSV_11__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_11__PRE                                             0x0

#define SCU_RAM_ATV_RSV_12__A                                               0x831F5D
#define SCU_RAM_ATV_RSV_12__W                                               16
#define SCU_RAM_ATV_RSV_12__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_12__PRE                                             0x0
#define SCU_RAM_ATV_VID_GAIN_HI__A                                          0x831F5E
#define SCU_RAM_ATV_VID_GAIN_HI__W                                          16
#define SCU_RAM_ATV_VID_GAIN_HI__M                                          0xFFFF
#define SCU_RAM_ATV_VID_GAIN_HI__PRE                                        0x0

#define   SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B                            0
#define   SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W                            16
#define   SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M                            0xFFFF
#define   SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE                          0x0

#define SCU_RAM_ATV_VID_GAIN_LO__A                                          0x831F5F
#define SCU_RAM_ATV_VID_GAIN_LO__W                                          8
#define SCU_RAM_ATV_VID_GAIN_LO__M                                          0xFF
#define SCU_RAM_ATV_VID_GAIN_LO__PRE                                        0x0

#define   SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B                            0
#define   SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W                            8
#define   SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M                            0xFF
#define   SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE                          0x0

#define SCU_RAM_ATV_RSV_13__A                                               0x831F60
#define SCU_RAM_ATV_RSV_13__W                                               16
#define SCU_RAM_ATV_RSV_13__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_13__PRE                                             0x0

#define SCU_RAM_ATV_RSV_14__A                                               0x831F61
#define SCU_RAM_ATV_RSV_14__W                                               16
#define SCU_RAM_ATV_RSV_14__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_14__PRE                                             0x0

#define SCU_RAM_ATV_RSV_15__A                                               0x831F62
#define SCU_RAM_ATV_RSV_15__W                                               16
#define SCU_RAM_ATV_RSV_15__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_15__PRE                                             0x0

#define SCU_RAM_ATV_RSV_16__A                                               0x831F63
#define SCU_RAM_ATV_RSV_16__W                                               16
#define SCU_RAM_ATV_RSV_16__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_16__PRE                                             0x0
#define SCU_RAM_ATV_AAGC_CNT__A                                             0x831F64
#define SCU_RAM_ATV_AAGC_CNT__W                                             8
#define SCU_RAM_ATV_AAGC_CNT__M                                             0xFF
#define SCU_RAM_ATV_AAGC_CNT__PRE                                           0x0

#define   SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B                                  0
#define   SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W                                  8
#define   SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M                                  0xFF
#define   SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE                                0x0

#define SCU_RAM_ATV_SIF_GAIN__A                                             0x831F65
#define SCU_RAM_ATV_SIF_GAIN__W                                             11
#define SCU_RAM_ATV_SIF_GAIN__M                                             0x7FF
#define SCU_RAM_ATV_SIF_GAIN__PRE                                           0x0

#define   SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B                                  0
#define   SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W                                  11
#define   SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M                                  0x7FF
#define   SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE                                0x0

#define SCU_RAM_ATV_RSV_17__A                                               0x831F66
#define SCU_RAM_ATV_RSV_17__W                                               16
#define SCU_RAM_ATV_RSV_17__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_17__PRE                                             0x0

#define SCU_RAM_ATV_RSV_18__A                                               0x831F67
#define SCU_RAM_ATV_RSV_18__W                                               16
#define SCU_RAM_ATV_RSV_18__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_18__PRE                                             0x0

#define SCU_RAM_ATV_RATE_OFS__A                                             0x831F68
#define SCU_RAM_ATV_RATE_OFS__W                                             12
#define SCU_RAM_ATV_RATE_OFS__M                                             0xFFF
#define SCU_RAM_ATV_RATE_OFS__PRE                                           0x0

#define SCU_RAM_ATV_LO_INCR__A                                              0x831F69
#define SCU_RAM_ATV_LO_INCR__W                                              12
#define SCU_RAM_ATV_LO_INCR__M                                              0xFFF
#define SCU_RAM_ATV_LO_INCR__PRE                                            0x0

#define SCU_RAM_ATV_IIR_CRIT__A                                             0x831F6A
#define SCU_RAM_ATV_IIR_CRIT__W                                             12
#define SCU_RAM_ATV_IIR_CRIT__M                                             0xFFF
#define SCU_RAM_ATV_IIR_CRIT__PRE                                           0x0

#define SCU_RAM_ATV_DEF_RATE_OFS__A                                         0x831F6B
#define SCU_RAM_ATV_DEF_RATE_OFS__W                                         12
#define SCU_RAM_ATV_DEF_RATE_OFS__M                                         0xFFF
#define SCU_RAM_ATV_DEF_RATE_OFS__PRE                                       0x0

#define SCU_RAM_ATV_DEF_LO_INCR__A                                          0x831F6C
#define SCU_RAM_ATV_DEF_LO_INCR__W                                          12
#define SCU_RAM_ATV_DEF_LO_INCR__M                                          0xFFF
#define SCU_RAM_ATV_DEF_LO_INCR__PRE                                        0x0

#define SCU_RAM_ATV_ENABLE_IIR_WA__A                                        0x831F6D
#define SCU_RAM_ATV_ENABLE_IIR_WA__W                                        1
#define SCU_RAM_ATV_ENABLE_IIR_WA__M                                        0x1
#define SCU_RAM_ATV_ENABLE_IIR_WA__PRE                                      0x0

#define SCU_RAM_ATV_MOD_CONTROL__A                                          0x831F6E
#define SCU_RAM_ATV_MOD_CONTROL__W                                          12
#define SCU_RAM_ATV_MOD_CONTROL__M                                          0xFFF
#define SCU_RAM_ATV_MOD_CONTROL__PRE                                        0x0

#define SCU_RAM_ATV_PAGC_KI_MAX__A                                          0x831F6F
#define SCU_RAM_ATV_PAGC_KI_MAX__W                                          12
#define SCU_RAM_ATV_PAGC_KI_MAX__M                                          0xFFF
#define SCU_RAM_ATV_PAGC_KI_MAX__PRE                                        0x0

#define SCU_RAM_ATV_BPC_KI_MAX__A                                           0x831F70
#define SCU_RAM_ATV_BPC_KI_MAX__W                                           12
#define SCU_RAM_ATV_BPC_KI_MAX__M                                           0xFFF
#define SCU_RAM_ATV_BPC_KI_MAX__PRE                                         0x0

#define SCU_RAM_ATV_NAGC_KI_MAX__A                                          0x831F71
#define SCU_RAM_ATV_NAGC_KI_MAX__W                                          12
#define SCU_RAM_ATV_NAGC_KI_MAX__M                                          0xFFF
#define SCU_RAM_ATV_NAGC_KI_MAX__PRE                                        0x0
#define SCU_RAM_ATV_NAGC_KI_MIN__A                                          0x831F72
#define SCU_RAM_ATV_NAGC_KI_MIN__W                                          12
#define SCU_RAM_ATV_NAGC_KI_MIN__M                                          0xFFF
#define SCU_RAM_ATV_NAGC_KI_MIN__PRE                                        0x0

#define   SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B                            0
#define   SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W                            12
#define   SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M                            0xFFF
#define   SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE                          0x0

#define SCU_RAM_ATV_KI_CHANGE_TH__A                                         0x831F73
#define SCU_RAM_ATV_KI_CHANGE_TH__W                                         8
#define SCU_RAM_ATV_KI_CHANGE_TH__M                                         0xFF
#define SCU_RAM_ATV_KI_CHANGE_TH__PRE                                       0x0

#define   SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B                          0
#define   SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W                          8
#define   SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M                          0xFF
#define   SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE                        0x0
#define     SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD                   0x14
#define     SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD                   0x28

#define SCU_RAM_QAM_PARAM_ANNEX__A                                          0x831F74
#define SCU_RAM_QAM_PARAM_ANNEX__W                                          2
#define SCU_RAM_QAM_PARAM_ANNEX__M                                          0x3
#define SCU_RAM_QAM_PARAM_ANNEX__PRE                                        0x0

#define   SCU_RAM_QAM_PARAM_ANNEX_BIT__B                                    0
#define   SCU_RAM_QAM_PARAM_ANNEX_BIT__W                                    2
#define   SCU_RAM_QAM_PARAM_ANNEX_BIT__M                                    0x3
#define   SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE                                  0x0
#define     SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A                             0x0
#define     SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B                             0x1
#define     SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C                             0x2
#define     SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D                             0x3

#define SCU_RAM_QAM_PARAM_CONSTELLATION__A                                  0x831F75
#define SCU_RAM_QAM_PARAM_CONSTELLATION__W                                  3
#define SCU_RAM_QAM_PARAM_CONSTELLATION__M                                  0x7
#define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE                                0x0

#define   SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B                            0
#define   SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W                            3
#define   SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M                            0x7
#define   SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE                          0x0
#define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN                     0x0
#define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16                      0x3
#define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32                      0x4
#define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64                      0x5
#define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128                     0x6
#define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256                     0x7

#define SCU_RAM_QAM_PARAM_INTERLEAVE__A                                     0x831F76
#define SCU_RAM_QAM_PARAM_INTERLEAVE__W                                     8
#define SCU_RAM_QAM_PARAM_INTERLEAVE__M                                     0xFF
#define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE                                   0x0

#define   SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B                               0
#define   SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W                               8
#define   SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M                               0xFF
#define   SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE                             0x0
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1                        0x0
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2                     0x1
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2                        0x2
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2                         0x3
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3                        0x4
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4                         0x5
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4                        0x6
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8                         0x7
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5                        0x8
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16                         0x9
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6                        0xA
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7                        0xC
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8                        0xE
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17                        0x10
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4                          0x11
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN                        0xFE
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO                           0xFF

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A                                  0x831F77
#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W                                  16
#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M                                  0xFFFF
#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE                                0x0

#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B                            0
#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W                            16
#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M                            0xFFFF
#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE                          0x0

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A                                  0x831F78
#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W                                  16
#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M                                  0xFFFF
#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE                                0x0

#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B                            0
#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W                            16
#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M                            0xFFFF
#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE                          0x0

#define SCU_RAM_QAM_EQ_CENTERTAP__A                                         0x831F79
#define SCU_RAM_QAM_EQ_CENTERTAP__W                                         16
#define SCU_RAM_QAM_EQ_CENTERTAP__M                                         0xFFFF
#define SCU_RAM_QAM_EQ_CENTERTAP__PRE                                       0x0

#define   SCU_RAM_QAM_EQ_CENTERTAP_BIT__B                                   0
#define   SCU_RAM_QAM_EQ_CENTERTAP_BIT__W                                   8
#define   SCU_RAM_QAM_EQ_CENTERTAP_BIT__M                                   0xFF
#define   SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE                                 0x0

#define SCU_RAM_QAM_WR_RSV_0__A                                             0x831F7A
#define SCU_RAM_QAM_WR_RSV_0__W                                             16
#define SCU_RAM_QAM_WR_RSV_0__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_0__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_0_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_0_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_0_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_0_BIT__PRE                                     0x0

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A                                  0x831F7B
#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W                                  16
#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M                                  0xFFFF
#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE                                0x0

#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B                            0
#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W                            16
#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M                            0xFFFF
#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE                          0x0

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A                                  0x831F7C
#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W                                  16
#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M                                  0xFFFF
#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE                                0x0

#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B                            0
#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W                            16
#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M                            0xFFFF
#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE                          0x0

#define SCU_RAM_QAM_WR_RSV_5__A                                             0x831F7D
#define SCU_RAM_QAM_WR_RSV_5__W                                             16
#define SCU_RAM_QAM_WR_RSV_5__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_5__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_5_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_5_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_5_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_5_BIT__PRE                                     0x0

#define SCU_RAM_QAM_WR_RSV_6__A                                             0x831F7E
#define SCU_RAM_QAM_WR_RSV_6__W                                             16
#define SCU_RAM_QAM_WR_RSV_6__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_6__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_6_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_6_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_6_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_6_BIT__PRE                                     0x0

#define SCU_RAM_QAM_WR_RSV_7__A                                             0x831F7F
#define SCU_RAM_QAM_WR_RSV_7__W                                             16
#define SCU_RAM_QAM_WR_RSV_7__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_7__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_7_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_7_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_7_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_7_BIT__PRE                                     0x0

#define SCU_RAM_QAM_WR_RSV_8__A                                             0x831F80
#define SCU_RAM_QAM_WR_RSV_8__W                                             16
#define SCU_RAM_QAM_WR_RSV_8__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_8__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_8_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_8_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_8_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_8_BIT__PRE                                     0x0

#define SCU_RAM_QAM_WR_RSV_9__A                                             0x831F81
#define SCU_RAM_QAM_WR_RSV_9__W                                             16
#define SCU_RAM_QAM_WR_RSV_9__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_9__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_9_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_9_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_9_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_9_BIT__PRE                                     0x0

#define SCU_RAM_QAM_WR_RSV_10__A                                            0x831F82
#define SCU_RAM_QAM_WR_RSV_10__W                                            16
#define SCU_RAM_QAM_WR_RSV_10__M                                            0xFFFF
#define SCU_RAM_QAM_WR_RSV_10__PRE                                          0x0

#define   SCU_RAM_QAM_WR_RSV_10_BIT__B                                      0
#define   SCU_RAM_QAM_WR_RSV_10_BIT__W                                      16
#define   SCU_RAM_QAM_WR_RSV_10_BIT__M                                      0xFFFF
#define   SCU_RAM_QAM_WR_RSV_10_BIT__PRE                                    0x0

#define SCU_RAM_QAM_FSM_FMHUM_TO__A                                         0x831F83
#define SCU_RAM_QAM_FSM_FMHUM_TO__W                                         16
#define SCU_RAM_QAM_FSM_FMHUM_TO__M                                         0xFFFF
#define SCU_RAM_QAM_FSM_FMHUM_TO__PRE                                       0x0

#define   SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B                                   0
#define   SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W                                   16
#define   SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M                                   0xFFFF
#define   SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE                                 0x0
#define     SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO                        0x0

#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A                                   0x831F84
#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W                                   16
#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M                                   0xFFFF
#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE                                 0x0

#define   SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B                             0
#define   SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W                             16
#define   SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M                             0xFFFF
#define   SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE                           0x0

#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A                                  0x831F85
#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W                                  16
#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M                                  0xFFFF
#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE                                0x0

#define   SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B                            0
#define   SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W                            16
#define   SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M                            0xFFFF
#define   SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE                          0x0

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A                                    0x831F86
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W                                    16
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M                                    0xFFFF
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE                                  0x0

#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B                              0
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W                              16
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M                              0xFFFF
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE                            0x0

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A                                    0x831F87
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W                                    16
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M                                    0xFFFF
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE                                  0x0

#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B                              0
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W                              16
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M                              0xFFFF
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE                            0x0

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A                                    0x831F88
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W                                    16
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M                                    0xFFFF
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE                                  0x0

#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B                              0
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W                              16
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M                              0xFFFF
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE                            0x0

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A                                    0x831F89
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W                                    16
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M                                    0xFFFF
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE                                  0x0

#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B                              0
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W                              16
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M                              0xFFFF
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE                            0x0

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A                                    0x831F8A
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W                                    16
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M                                    0xFFFF
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE                                  0x0

#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B                              0
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W                              16
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M                              0xFFFF
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE                            0x0

#define SCU_RAM_QAM_FSM_STATE_TGT__A                                        0x831F8B
#define SCU_RAM_QAM_FSM_STATE_TGT__W                                        4
#define SCU_RAM_QAM_FSM_STATE_TGT__M                                        0xF
#define SCU_RAM_QAM_FSM_STATE_TGT__PRE                                      0x0

#define   SCU_RAM_QAM_FSM_STATE_TGT_BIT__B                                  0
#define   SCU_RAM_QAM_FSM_STATE_TGT_BIT__W                                  4
#define   SCU_RAM_QAM_FSM_STATE_TGT_BIT__M                                  0xF
#define   SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE                                0x0
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP                       0x0
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE                      0x1
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ                      0x2
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT                   0x3
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE                     0x4
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE                  0x5
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING                          0x6
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST                    0x7

#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A                                    0x831F8C
#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W                                    9
#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M                                    0x1FF
#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE                                  0x0

#define   SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B                          0
#define   SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W                          1
#define   SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M                          0x1
#define   SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE                        0x0

#define SCU_RAM_QAM_FSM_ATH__A                                              0x831F8D
#define SCU_RAM_QAM_FSM_ATH__W                                              16
#define SCU_RAM_QAM_FSM_ATH__M                                              0xFFFF
#define SCU_RAM_QAM_FSM_ATH__PRE                                            0x0

#define   SCU_RAM_QAM_FSM_ATH_BIT__B                                        0
#define   SCU_RAM_QAM_FSM_ATH_BIT__W                                        16
#define   SCU_RAM_QAM_FSM_ATH_BIT__M                                        0xFFFF
#define   SCU_RAM_QAM_FSM_ATH_BIT__PRE                                      0x0

#define SCU_RAM_QAM_FSM_RTH__A                                              0x831F8E
#define SCU_RAM_QAM_FSM_RTH__W                                              16
#define SCU_RAM_QAM_FSM_RTH__M                                              0xFFFF
#define SCU_RAM_QAM_FSM_RTH__PRE                                            0x0

#define   SCU_RAM_QAM_FSM_RTH_BIT__B                                        0
#define   SCU_RAM_QAM_FSM_RTH_BIT__W                                        16
#define   SCU_RAM_QAM_FSM_RTH_BIT__M                                        0xFFFF
#define   SCU_RAM_QAM_FSM_RTH_BIT__PRE                                      0x0
#define     SCU_RAM_QAM_FSM_RTH_BIT_QAM_16                                  0x8C
#define     SCU_RAM_QAM_FSM_RTH_BIT_QAM_32                                  0x50
#define     SCU_RAM_QAM_FSM_RTH_BIT_QAM_64                                  0x4E
#define     SCU_RAM_QAM_FSM_RTH_BIT_QAM_128                                 0x32
#define     SCU_RAM_QAM_FSM_RTH_BIT_QAM_256                                 0x2D

#define SCU_RAM_QAM_FSM_FTH__A                                              0x831F8F
#define SCU_RAM_QAM_FSM_FTH__W                                              16
#define SCU_RAM_QAM_FSM_FTH__M                                              0xFFFF
#define SCU_RAM_QAM_FSM_FTH__PRE                                            0x0

#define   SCU_RAM_QAM_FSM_FTH_BIT__B                                        0
#define   SCU_RAM_QAM_FSM_FTH_BIT__W                                        16
#define   SCU_RAM_QAM_FSM_FTH_BIT__M                                        0xFFFF
#define   SCU_RAM_QAM_FSM_FTH_BIT__PRE                                      0x0
#define     SCU_RAM_QAM_FSM_FTH_BIT_QAM_16                                  0x32
#define     SCU_RAM_QAM_FSM_FTH_BIT_QAM_32                                  0x1E
#define     SCU_RAM_QAM_FSM_FTH_BIT_QAM_64                                  0x1E
#define     SCU_RAM_QAM_FSM_FTH_BIT_QAM_128                                 0x14
#define     SCU_RAM_QAM_FSM_FTH_BIT_QAM_256                                 0x14

#define SCU_RAM_QAM_FSM_PTH__A                                              0x831F90
#define SCU_RAM_QAM_FSM_PTH__W                                              16
#define SCU_RAM_QAM_FSM_PTH__M                                              0xFFFF
#define SCU_RAM_QAM_FSM_PTH__PRE                                            0x0

#define   SCU_RAM_QAM_FSM_PTH_BIT__B                                        0
#define   SCU_RAM_QAM_FSM_PTH_BIT__W                                        16
#define   SCU_RAM_QAM_FSM_PTH_BIT__M                                        0xFFFF
#define   SCU_RAM_QAM_FSM_PTH_BIT__PRE                                      0x0
#define     SCU_RAM_QAM_FSM_PTH_BIT_QAM_16                                  0xC8
#define     SCU_RAM_QAM_FSM_PTH_BIT_QAM_32                                  0x96
#define     SCU_RAM_QAM_FSM_PTH_BIT_QAM_64                                  0x8C
#define     SCU_RAM_QAM_FSM_PTH_BIT_QAM_128                                 0x64
#define     SCU_RAM_QAM_FSM_PTH_BIT_QAM_256                                 0x64

#define SCU_RAM_QAM_FSM_MTH__A                                              0x831F91
#define SCU_RAM_QAM_FSM_MTH__W                                              16
#define SCU_RAM_QAM_FSM_MTH__M                                              0xFFFF
#define SCU_RAM_QAM_FSM_MTH__PRE                                            0x0

#define   SCU_RAM_QAM_FSM_MTH_BIT__B                                        0
#define   SCU_RAM_QAM_FSM_MTH_BIT__W                                        16
#define   SCU_RAM_QAM_FSM_MTH_BIT__M                                        0xFFFF
#define   SCU_RAM_QAM_FSM_MTH_BIT__PRE                                      0x0
#define     SCU_RAM_QAM_FSM_MTH_BIT_QAM_16                                  0x5A
#define     SCU_RAM_QAM_FSM_MTH_BIT_QAM_32                                  0x50
#define     SCU_RAM_QAM_FSM_MTH_BIT_QAM_64                                  0x46
#define     SCU_RAM_QAM_FSM_MTH_BIT_QAM_128                                 0x3C
#define     SCU_RAM_QAM_FSM_MTH_BIT_QAM_256                                 0x50

#define SCU_RAM_QAM_FSM_CTH__A                                              0x831F92
#define SCU_RAM_QAM_FSM_CTH__W                                              16
#define SCU_RAM_QAM_FSM_CTH__M                                              0xFFFF
#define SCU_RAM_QAM_FSM_CTH__PRE                                            0x0

#define   SCU_RAM_QAM_FSM_CTH_BIT__B                                        0
#define   SCU_RAM_QAM_FSM_CTH_BIT__W                                        16
#define   SCU_RAM_QAM_FSM_CTH_BIT__M                                        0xFFFF
#define   SCU_RAM_QAM_FSM_CTH_BIT__PRE                                      0x0
#define     SCU_RAM_QAM_FSM_CTH_BIT_QAM_16                                  0xA0
#define     SCU_RAM_QAM_FSM_CTH_BIT_QAM_32                                  0x8C
#define     SCU_RAM_QAM_FSM_CTH_BIT_QAM_64                                  0x8C
#define     SCU_RAM_QAM_FSM_CTH_BIT_QAM_128                                 0x8C
#define     SCU_RAM_QAM_FSM_CTH_BIT_QAM_256                                 0x8C

#define SCU_RAM_QAM_FSM_QTH__A                                              0x831F93
#define SCU_RAM_QAM_FSM_QTH__W                                              16
#define SCU_RAM_QAM_FSM_QTH__M                                              0xFFFF
#define SCU_RAM_QAM_FSM_QTH__PRE                                            0x0

#define   SCU_RAM_QAM_FSM_QTH_BIT__B                                        0
#define   SCU_RAM_QAM_FSM_QTH_BIT__W                                        16
#define   SCU_RAM_QAM_FSM_QTH_BIT__M                                        0xFFFF
#define   SCU_RAM_QAM_FSM_QTH_BIT__PRE                                      0x0
#define     SCU_RAM_QAM_FSM_QTH_BIT_QAM_16                                  0xE6
#define     SCU_RAM_QAM_FSM_QTH_BIT_QAM_32                                  0xAA
#define     SCU_RAM_QAM_FSM_QTH_BIT_QAM_64                                  0xC3
#define     SCU_RAM_QAM_FSM_QTH_BIT_QAM_128                                 0x8C
#define     SCU_RAM_QAM_FSM_QTH_BIT_QAM_256                                 0x96

#define SCU_RAM_QAM_FSM_RATE_LIM__A                                         0x831F94
#define SCU_RAM_QAM_FSM_RATE_LIM__W                                         16
#define SCU_RAM_QAM_FSM_RATE_LIM__M                                         0xFFFF
#define SCU_RAM_QAM_FSM_RATE_LIM__PRE                                       0x0

#define   SCU_RAM_QAM_FSM_RATE_LIM_BIT__B                                   0
#define   SCU_RAM_QAM_FSM_RATE_LIM_BIT__W                                   16
#define   SCU_RAM_QAM_FSM_RATE_LIM_BIT__M                                   0xFFFF
#define   SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE                                 0x0
#define     SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16                             0x46
#define     SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32                             0x46
#define     SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64                             0x46
#define     SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128                            0x46
#define     SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256                            0x46

#define SCU_RAM_QAM_FSM_FREQ_LIM__A                                         0x831F95
#define SCU_RAM_QAM_FSM_FREQ_LIM__W                                         16
#define SCU_RAM_QAM_FSM_FREQ_LIM__M                                         0xFFFF
#define SCU_RAM_QAM_FSM_FREQ_LIM__PRE                                       0x0

#define   SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B                                   0
#define   SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W                                   16
#define   SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M                                   0xFFFF
#define   SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE                                 0x0
#define     SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16                             0x1E
#define     SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32                             0x14
#define     SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64                             0x28
#define     SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128                            0x8
#define     SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256                            0x28

#define SCU_RAM_QAM_FSM_COUNT_LIM__A                                        0x831F96
#define SCU_RAM_QAM_FSM_COUNT_LIM__W                                        16
#define SCU_RAM_QAM_FSM_COUNT_LIM__M                                        0xFFFF
#define SCU_RAM_QAM_FSM_COUNT_LIM__PRE                                      0x0

#define   SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B                                  0
#define   SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W                                  16
#define   SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M                                  0xFFFF
#define   SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE                                0x0
#define     SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16                            0x4
#define     SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32                            0x6
#define     SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64                            0x6
#define     SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128                           0x7
#define     SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256                           0x6

#define SCU_RAM_QAM_LC_CA_COARSE__A                                         0x831F97
#define SCU_RAM_QAM_LC_CA_COARSE__W                                         16
#define SCU_RAM_QAM_LC_CA_COARSE__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CA_COARSE__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CA_COARSE_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CA_COARSE_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CA_COARSE_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CA_MEDIUM__A                                         0x831F98
#define SCU_RAM_QAM_LC_CA_MEDIUM__W                                         16
#define SCU_RAM_QAM_LC_CA_MEDIUM__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CA_MEDIUM__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CA_FINE__A                                           0x831F99
#define SCU_RAM_QAM_LC_CA_FINE__W                                           16
#define SCU_RAM_QAM_LC_CA_FINE__M                                           0xFFFF
#define SCU_RAM_QAM_LC_CA_FINE__PRE                                         0x0

#define   SCU_RAM_QAM_LC_CA_FINE_BIT__B                                     0
#define   SCU_RAM_QAM_LC_CA_FINE_BIT__W                                     8
#define   SCU_RAM_QAM_LC_CA_FINE_BIT__M                                     0xFF
#define   SCU_RAM_QAM_LC_CA_FINE_BIT__PRE                                   0x0

#define SCU_RAM_QAM_LC_CP_COARSE__A                                         0x831F9A
#define SCU_RAM_QAM_LC_CP_COARSE__W                                         16
#define SCU_RAM_QAM_LC_CP_COARSE__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CP_COARSE__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CP_COARSE_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CP_COARSE_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CP_COARSE_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CP_MEDIUM__A                                         0x831F9B
#define SCU_RAM_QAM_LC_CP_MEDIUM__W                                         16
#define SCU_RAM_QAM_LC_CP_MEDIUM__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CP_MEDIUM__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CP_FINE__A                                           0x831F9C
#define SCU_RAM_QAM_LC_CP_FINE__W                                           16
#define SCU_RAM_QAM_LC_CP_FINE__M                                           0xFFFF
#define SCU_RAM_QAM_LC_CP_FINE__PRE                                         0x0

#define   SCU_RAM_QAM_LC_CP_FINE_BIT__B                                     0
#define   SCU_RAM_QAM_LC_CP_FINE_BIT__W                                     8
#define   SCU_RAM_QAM_LC_CP_FINE_BIT__M                                     0xFF
#define   SCU_RAM_QAM_LC_CP_FINE_BIT__PRE                                   0x0

#define SCU_RAM_QAM_LC_CI_COARSE__A                                         0x831F9D
#define SCU_RAM_QAM_LC_CI_COARSE__W                                         16
#define SCU_RAM_QAM_LC_CI_COARSE__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CI_COARSE__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CI_COARSE_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CI_COARSE_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CI_COARSE_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CI_MEDIUM__A                                         0x831F9E
#define SCU_RAM_QAM_LC_CI_MEDIUM__W                                         16
#define SCU_RAM_QAM_LC_CI_MEDIUM__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CI_MEDIUM__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CI_FINE__A                                           0x831F9F
#define SCU_RAM_QAM_LC_CI_FINE__W                                           16
#define SCU_RAM_QAM_LC_CI_FINE__M                                           0xFFFF
#define SCU_RAM_QAM_LC_CI_FINE__PRE                                         0x0

#define   SCU_RAM_QAM_LC_CI_FINE_BIT__B                                     0
#define   SCU_RAM_QAM_LC_CI_FINE_BIT__W                                     8
#define   SCU_RAM_QAM_LC_CI_FINE_BIT__M                                     0xFF
#define   SCU_RAM_QAM_LC_CI_FINE_BIT__PRE                                   0x0

#define SCU_RAM_QAM_LC_EP_COARSE__A                                         0x831FA0
#define SCU_RAM_QAM_LC_EP_COARSE__W                                         16
#define SCU_RAM_QAM_LC_EP_COARSE__M                                         0xFFFF
#define SCU_RAM_QAM_LC_EP_COARSE__PRE                                       0x0

#define   SCU_RAM_QAM_LC_EP_COARSE_BIT__B                                   0
#define   SCU_RAM_QAM_LC_EP_COARSE_BIT__W                                   8
#define   SCU_RAM_QAM_LC_EP_COARSE_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_EP_MEDIUM__A                                         0x831FA1
#define SCU_RAM_QAM_LC_EP_MEDIUM__W                                         16
#define SCU_RAM_QAM_LC_EP_MEDIUM__M                                         0xFFFF
#define SCU_RAM_QAM_LC_EP_MEDIUM__PRE                                       0x0

#define   SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B                                   0
#define   SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W                                   8
#define   SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_EP_FINE__A                                           0x831FA2
#define SCU_RAM_QAM_LC_EP_FINE__W                                           16
#define SCU_RAM_QAM_LC_EP_FINE__M                                           0xFFFF
#define SCU_RAM_QAM_LC_EP_FINE__PRE                                         0x0

#define   SCU_RAM_QAM_LC_EP_FINE_BIT__B                                     0
#define   SCU_RAM_QAM_LC_EP_FINE_BIT__W                                     8
#define   SCU_RAM_QAM_LC_EP_FINE_BIT__M                                     0xFF
#define   SCU_RAM_QAM_LC_EP_FINE_BIT__PRE                                   0x0

#define SCU_RAM_QAM_LC_EI_COARSE__A                                         0x831FA3
#define SCU_RAM_QAM_LC_EI_COARSE__W                                         16
#define SCU_RAM_QAM_LC_EI_COARSE__M                                         0xFFFF
#define SCU_RAM_QAM_LC_EI_COARSE__PRE                                       0x0

#define   SCU_RAM_QAM_LC_EI_COARSE_BIT__B                                   0
#define   SCU_RAM_QAM_LC_EI_COARSE_BIT__W                                   8
#define   SCU_RAM_QAM_LC_EI_COARSE_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_EI_MEDIUM__A                                         0x831FA4
#define SCU_RAM_QAM_LC_EI_MEDIUM__W                                         16
#define SCU_RAM_QAM_LC_EI_MEDIUM__M                                         0xFFFF
#define SCU_RAM_QAM_LC_EI_MEDIUM__PRE                                       0x0

#define   SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B                                   0
#define   SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W                                   8
#define   SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_EI_FINE__A                                           0x831FA5
#define SCU_RAM_QAM_LC_EI_FINE__W                                           16
#define SCU_RAM_QAM_LC_EI_FINE__M                                           0xFFFF
#define SCU_RAM_QAM_LC_EI_FINE__PRE                                         0x0

#define   SCU_RAM_QAM_LC_EI_FINE_BIT__B                                     0
#define   SCU_RAM_QAM_LC_EI_FINE_BIT__W                                     8
#define   SCU_RAM_QAM_LC_EI_FINE_BIT__M                                     0xFF
#define   SCU_RAM_QAM_LC_EI_FINE_BIT__PRE                                   0x0

#define SCU_RAM_QAM_LC_CF_COARSE__A                                         0x831FA6
#define SCU_RAM_QAM_LC_CF_COARSE__W                                         16
#define SCU_RAM_QAM_LC_CF_COARSE__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CF_COARSE__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CF_COARSE_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CF_COARSE_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CF_COARSE_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CF_MEDIUM__A                                         0x831FA7
#define SCU_RAM_QAM_LC_CF_MEDIUM__W                                         16
#define SCU_RAM_QAM_LC_CF_MEDIUM__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CF_FINE__A                                           0x831FA8
#define SCU_RAM_QAM_LC_CF_FINE__W                                           16
#define SCU_RAM_QAM_LC_CF_FINE__M                                           0xFFFF
#define SCU_RAM_QAM_LC_CF_FINE__PRE                                         0x0

#define   SCU_RAM_QAM_LC_CF_FINE_BIT__B                                     0
#define   SCU_RAM_QAM_LC_CF_FINE_BIT__W                                     8
#define   SCU_RAM_QAM_LC_CF_FINE_BIT__M                                     0xFF
#define   SCU_RAM_QAM_LC_CF_FINE_BIT__PRE                                   0x0

#define SCU_RAM_QAM_LC_CF1_COARSE__A                                        0x831FA9
#define SCU_RAM_QAM_LC_CF1_COARSE__W                                        16
#define SCU_RAM_QAM_LC_CF1_COARSE__M                                        0xFFFF
#define SCU_RAM_QAM_LC_CF1_COARSE__PRE                                      0x0

#define   SCU_RAM_QAM_LC_CF1_COARSE_BIT__B                                  0
#define   SCU_RAM_QAM_LC_CF1_COARSE_BIT__W                                  8
#define   SCU_RAM_QAM_LC_CF1_COARSE_BIT__M                                  0xFF
#define   SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE                                0x0

#define SCU_RAM_QAM_LC_CF1_MEDIUM__A                                        0x831FAA
#define SCU_RAM_QAM_LC_CF1_MEDIUM__W                                        16
#define SCU_RAM_QAM_LC_CF1_MEDIUM__M                                        0xFFFF
#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE                                      0x0

#define   SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B                                  0
#define   SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W                                  8
#define   SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M                                  0xFF
#define   SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE                                0x0

#define SCU_RAM_QAM_LC_CF1_FINE__A                                          0x831FAB
#define SCU_RAM_QAM_LC_CF1_FINE__W                                          16
#define SCU_RAM_QAM_LC_CF1_FINE__M                                          0xFFFF
#define SCU_RAM_QAM_LC_CF1_FINE__PRE                                        0x0

#define   SCU_RAM_QAM_LC_CF1_FINE_BIT__B                                    0
#define   SCU_RAM_QAM_LC_CF1_FINE_BIT__W                                    8
#define   SCU_RAM_QAM_LC_CF1_FINE_BIT__M                                    0xFF
#define   SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE                                  0x0

#define SCU_RAM_QAM_SL_SIG_POWER__A                                         0x831FAC
#define SCU_RAM_QAM_SL_SIG_POWER__W                                         16
#define SCU_RAM_QAM_SL_SIG_POWER__M                                         0xFFFF
#define SCU_RAM_QAM_SL_SIG_POWER__PRE                                       0x0

#define   SCU_RAM_QAM_SL_SIG_POWER_BIT__B                                   0
#define   SCU_RAM_QAM_SL_SIG_POWER_BIT__W                                   16
#define   SCU_RAM_QAM_SL_SIG_POWER_BIT__M                                   0xFFFF
#define   SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE                                 0x0

#define SCU_RAM_QAM_EQ_CMA_RAD0__A                                          0x831FAD
#define SCU_RAM_QAM_EQ_CMA_RAD0__W                                          14
#define SCU_RAM_QAM_EQ_CMA_RAD0__M                                          0x3FFF
#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE                                        0x0

#define   SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B                                    0
#define   SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W                                    14
#define   SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M                                    0x3FFF
#define   SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE                                  0x0
#define     SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16                              0x34CD
#define     SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32                              0x1A33
#define     SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64                              0x3418
#define     SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128                             0x1814
#define     SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256                             0x2CEE

#define SCU_RAM_QAM_EQ_CMA_RAD1__A                                          0x831FAE
#define SCU_RAM_QAM_EQ_CMA_RAD1__W                                          14
#define SCU_RAM_QAM_EQ_CMA_RAD1__M                                          0x3FFF
#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE                                        0x0

#define   SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B                                    0
#define   SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W                                    14
#define   SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M                                    0x3FFF
#define   SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE                                  0x0
#define     SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16                              0x34CD
#define     SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32                              0x1A33
#define     SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64                              0x314A
#define     SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128                             0x19C6
#define     SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256                             0x2F34

#define SCU_RAM_QAM_EQ_CMA_RAD2__A                                          0x831FAF
#define SCU_RAM_QAM_EQ_CMA_RAD2__W                                          14
#define SCU_RAM_QAM_EQ_CMA_RAD2__M                                          0x3FFF
#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE                                        0x0

#define   SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B                                    0
#define   SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W                                    14
#define   SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M                                    0x3FFF
#define   SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE                                  0x0
#define     SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16                              0x34CD
#define     SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32                              0x1A33
#define     SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64                              0x2ED4
#define     SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128                             0x18FA
#define     SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256                             0x30FF

#define SCU_RAM_QAM_EQ_CMA_RAD3__A                                          0x831FB0
#define SCU_RAM_QAM_EQ_CMA_RAD3__W                                          14
#define SCU_RAM_QAM_EQ_CMA_RAD3__M                                          0x3FFF
#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE                                        0x0

#define   SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B                                    0
#define   SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W                                    14
#define   SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M                                    0x3FFF
#define   SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE                                  0x0
#define     SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16                              0x34CD
#define     SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32                              0x1A33
#define     SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64                              0x35F1
#define     SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128                             0x1909
#define     SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256                             0x3283

#define SCU_RAM_QAM_EQ_CMA_RAD4__A                                          0x831FB1
#define SCU_RAM_QAM_EQ_CMA_RAD4__W                                          14
#define SCU_RAM_QAM_EQ_CMA_RAD4__M                                          0x3FFF
#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE                                        0x0

#define   SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B                                    0
#define   SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W                                    14
#define   SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M                                    0x3FFF
#define   SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE                                  0x0
#define     SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16                              0x34CD
#define     SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32                              0x1A33
#define     SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64                              0x35F1
#define     SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128                             0x1A00
#define     SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256                             0x353D

#define SCU_RAM_QAM_EQ_CMA_RAD5__A                                          0x831FB2
#define SCU_RAM_QAM_EQ_CMA_RAD5__W                                          14
#define SCU_RAM_QAM_EQ_CMA_RAD5__M                                          0x3FFF
#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE                                        0x0

#define   SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B                                    0
#define   SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W                                    14
#define   SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M                                    0x3FFF
#define   SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE                                  0x0
#define     SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16                              0x34CD
#define     SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32                              0x1A33
#define     SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64                              0x3CF9
#define     SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128                             0x1C46
#define     SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256                             0x3C19

#define SCU_RAM_QAM_CTL_ENA__A                                              0x831FB3
#define SCU_RAM_QAM_CTL_ENA__W                                              16
#define SCU_RAM_QAM_CTL_ENA__M                                              0xFFFF
#define SCU_RAM_QAM_CTL_ENA__PRE                                            0x0

#define   SCU_RAM_QAM_CTL_ENA_AMP__B                                        0
#define   SCU_RAM_QAM_CTL_ENA_AMP__W                                        1
#define   SCU_RAM_QAM_CTL_ENA_AMP__M                                        0x1
#define   SCU_RAM_QAM_CTL_ENA_AMP__PRE                                      0x0

#define   SCU_RAM_QAM_CTL_ENA_ACQ__B                                        1
#define   SCU_RAM_QAM_CTL_ENA_ACQ__W                                        1
#define   SCU_RAM_QAM_CTL_ENA_ACQ__M                                        0x2
#define   SCU_RAM_QAM_CTL_ENA_ACQ__PRE                                      0x0

#define   SCU_RAM_QAM_CTL_ENA_EQU__B                                        2
#define   SCU_RAM_QAM_CTL_ENA_EQU__W                                        1
#define   SCU_RAM_QAM_CTL_ENA_EQU__M                                        0x4
#define   SCU_RAM_QAM_CTL_ENA_EQU__PRE                                      0x0

#define   SCU_RAM_QAM_CTL_ENA_SLC__B                                        3
#define   SCU_RAM_QAM_CTL_ENA_SLC__W                                        1
#define   SCU_RAM_QAM_CTL_ENA_SLC__M                                        0x8
#define   SCU_RAM_QAM_CTL_ENA_SLC__PRE                                      0x0

#define   SCU_RAM_QAM_CTL_ENA_LC__B                                         4
#define   SCU_RAM_QAM_CTL_ENA_LC__W                                         1
#define   SCU_RAM_QAM_CTL_ENA_LC__M                                         0x10
#define   SCU_RAM_QAM_CTL_ENA_LC__PRE                                       0x0

#define   SCU_RAM_QAM_CTL_ENA_AGC__B                                        5
#define   SCU_RAM_QAM_CTL_ENA_AGC__W                                        1
#define   SCU_RAM_QAM_CTL_ENA_AGC__M                                        0x20
#define   SCU_RAM_QAM_CTL_ENA_AGC__PRE                                      0x0

#define   SCU_RAM_QAM_CTL_ENA_FEC__B                                        6
#define   SCU_RAM_QAM_CTL_ENA_FEC__W                                        1
#define   SCU_RAM_QAM_CTL_ENA_FEC__M                                        0x40
#define   SCU_RAM_QAM_CTL_ENA_FEC__PRE                                      0x0

#define   SCU_RAM_QAM_CTL_ENA_AXIS__B                                       7
#define   SCU_RAM_QAM_CTL_ENA_AXIS__W                                       1
#define   SCU_RAM_QAM_CTL_ENA_AXIS__M                                       0x80
#define   SCU_RAM_QAM_CTL_ENA_AXIS__PRE                                     0x0

#define   SCU_RAM_QAM_CTL_ENA_FMHUM__B                                      8
#define   SCU_RAM_QAM_CTL_ENA_FMHUM__W                                      1
#define   SCU_RAM_QAM_CTL_ENA_FMHUM__M                                      0x100
#define   SCU_RAM_QAM_CTL_ENA_FMHUM__PRE                                    0x0

#define   SCU_RAM_QAM_CTL_ENA_EQTIME__B                                     9
#define   SCU_RAM_QAM_CTL_ENA_EQTIME__W                                     1
#define   SCU_RAM_QAM_CTL_ENA_EQTIME__M                                     0x200
#define   SCU_RAM_QAM_CTL_ENA_EQTIME__PRE                                   0x0

#define   SCU_RAM_QAM_CTL_ENA_EXTLCK__B                                     10
#define   SCU_RAM_QAM_CTL_ENA_EXTLCK__W                                     1
#define   SCU_RAM_QAM_CTL_ENA_EXTLCK__M                                     0x400
#define   SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE                                   0x0

#define SCU_RAM_QAM_WR_RSV_1__A                                             0x831FB4
#define SCU_RAM_QAM_WR_RSV_1__W                                             16
#define SCU_RAM_QAM_WR_RSV_1__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_1__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_1_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_1_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_1_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_1_BIT__PRE                                     0x0

#define SCU_RAM_QAM_WR_RSV_2__A                                             0x831FB5
#define SCU_RAM_QAM_WR_RSV_2__W                                             16
#define SCU_RAM_QAM_WR_RSV_2__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_2__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_2_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_2_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_2_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_2_BIT__PRE                                     0x0

#define SCU_RAM_QAM_WR_RSV_3__A                                             0x831FB6
#define SCU_RAM_QAM_WR_RSV_3__W                                             16
#define SCU_RAM_QAM_WR_RSV_3__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_3__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_3_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_3_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_3_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_3_BIT__PRE                                     0x0

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A                                 0x831FB7
#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W                                 3
#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M                                 0x7
#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE                               0x0

#define   SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B                           0
#define   SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W                           3
#define   SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M                           0x7
#define   SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE                         0x0
#define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN                    0x0
#define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16                     0x3
#define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32                     0x4
#define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64                     0x5
#define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128                    0x6
#define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256                    0x7

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A                                    0x831FB8
#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W                                    8
#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M                                    0xFF
#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE                                  0x0

#define   SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B                              0
#define   SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W                              8
#define   SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M                              0xFF
#define   SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE                            0x0
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1                       0x0
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2                    0x1
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2                       0x2
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2                        0x3
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3                       0x4
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4                        0x5
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4                       0x6
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8                        0x7
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5                       0x8
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16                        0x9
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6                       0xA
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7                       0xC
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8                       0xE
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17                       0x10
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4                         0x11
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN                       0xFE

#define SCU_RAM_QAM_RD_RSV_4__A                                             0x831FB9
#define SCU_RAM_QAM_RD_RSV_4__W                                             16
#define SCU_RAM_QAM_RD_RSV_4__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_4__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_4_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_4_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_4_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_4_BIT__PRE                                     0x0

#define SCU_RAM_QAM_LOCKED__A                                               0x831FBA
#define SCU_RAM_QAM_LOCKED__W                                               16
#define SCU_RAM_QAM_LOCKED__M                                               0xFFFF
#define SCU_RAM_QAM_LOCKED__PRE                                             0x0

#define   SCU_RAM_QAM_LOCKED_INTLEVEL__B                                    0
#define   SCU_RAM_QAM_LOCKED_INTLEVEL__W                                    8
#define   SCU_RAM_QAM_LOCKED_INTLEVEL__M                                    0xFF
#define   SCU_RAM_QAM_LOCKED_INTLEVEL__PRE                                  0x0
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED                          0x0
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK                              0x1
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK                             0x2
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK                             0x3
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK                          0x4
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK                          0x5
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK                            0x6
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK                         0x7

#define   SCU_RAM_QAM_LOCKED_LOCKED__B                                      8
#define   SCU_RAM_QAM_LOCKED_LOCKED__W                                      8
#define   SCU_RAM_QAM_LOCKED_LOCKED__M                                      0xFF00
#define   SCU_RAM_QAM_LOCKED_LOCKED__PRE                                    0x0
#define     SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED                            0x0
#define     SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED                          0x4000
#define     SCU_RAM_QAM_LOCKED_LOCKED_LOCKED                                0x8000
#define     SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK                            0xC000

#define SCU_RAM_QAM_EVENTS_OCC_HI__A                                        0x831FBB
#define SCU_RAM_QAM_EVENTS_OCC_HI__W                                        16
#define SCU_RAM_QAM_EVENTS_OCC_HI__M                                        0xFFFF
#define SCU_RAM_QAM_EVENTS_OCC_HI__PRE                                      0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B                               0
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W                               1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M                               0x1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE                             0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B                          1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W                          1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M                          0x2
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE                        0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B                                 2
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W                                 1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M                                 0x4
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE                               0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B                           3
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W                           1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M                           0x8
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE                         0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B                          4
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W                          1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M                          0x10
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE                        0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B                              5
#define   SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W                              1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M                              0x20
#define   SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE                            0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B                            6
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W                            1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M                            0x40
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE                          0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B                           7
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W                           1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M                           0x80
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE                         0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B                              8
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W                              1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M                              0x100
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE                            0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B                            9
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W                            1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M                            0x200
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE                          0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B                              10
#define   SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W                              1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M                              0x400
#define   SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE                            0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B                              11
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W                              1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M                              0x800
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE                            0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B                                  12
#define   SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W                                  4
#define   SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M                                  0xF000
#define   SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE                                0x0

#define SCU_RAM_QAM_EVENTS_OCC_LO__A                                        0x831FBC
#define SCU_RAM_QAM_EVENTS_OCC_LO__W                                        16
#define SCU_RAM_QAM_EVENTS_OCC_LO__M                                        0xFFFF
#define SCU_RAM_QAM_EVENTS_OCC_LO__PRE                                      0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B                                0
#define   SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W                                1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M                                0x1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE                              0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B                                 1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W                                 1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M                                 0x2
#define   SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE                               0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B                                2
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W                                1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M                                0x4
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE                              0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B                                3
#define   SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W                                1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M                                0x8
#define   SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE                              0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B                               4
#define   SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W                               1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M                               0x10
#define   SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE                             0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_MER__B                                  5
#define   SCU_RAM_QAM_EVENTS_OCC_LO_MER__W                                  1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_MER__M                                  0x20
#define   SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE                                0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B                                 6
#define   SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W                                 1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M                                 0x40
#define   SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE                               0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B                             7
#define   SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W                             1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M                             0x80
#define   SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE                           0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_SER__B                                  8
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SER__W                                  1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SER__M                                  0x100
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE                                0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B                           9
#define   SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W                           1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M                           0x200
#define   SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE                         0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B                           10
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W                           1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M                           0x400
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE                         0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B                          11
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W                          1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M                          0x800
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE                        0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B                          12
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W                          1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M                          0x1000
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE                        0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B                             13
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W                             1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M                             0x2000
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE                           0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B                           14
#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W                           1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M                           0x4000
#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE                         0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B                          15
#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W                          1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M                          0x8000
#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE                        0x0

#define SCU_RAM_QAM_EVENTS_SCHED_HI__A                                      0x831FBD
#define SCU_RAM_QAM_EVENTS_SCHED_HI__W                                      16
#define SCU_RAM_QAM_EVENTS_SCHED_HI__M                                      0xFFFF
#define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE                                    0x0

#define   SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B                                0
#define   SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W                                16
#define   SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M                                0xFFFF
#define   SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE                              0x0

#define SCU_RAM_QAM_EVENTS_SCHED_LO__A                                      0x831FBE
#define SCU_RAM_QAM_EVENTS_SCHED_LO__W                                      16
#define SCU_RAM_QAM_EVENTS_SCHED_LO__M                                      0xFFFF
#define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE                                    0x0

#define   SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B                                0
#define   SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W                                16
#define   SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M                                0xFFFF
#define   SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE                              0x0

#define SCU_RAM_QAM_TASKLETS_SCHED__A                                       0x831FBF
#define SCU_RAM_QAM_TASKLETS_SCHED__W                                       16
#define SCU_RAM_QAM_TASKLETS_SCHED__M                                       0xFFFF
#define SCU_RAM_QAM_TASKLETS_SCHED__PRE                                     0x0

#define   SCU_RAM_QAM_TASKLETS_SCHED_BIT__B                                 0
#define   SCU_RAM_QAM_TASKLETS_SCHED_BIT__W                                 16
#define   SCU_RAM_QAM_TASKLETS_SCHED_BIT__M                                 0xFFFF
#define   SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE                               0x0

#define SCU_RAM_QAM_TASKLETS_RUN__A                                         0x831FC0
#define SCU_RAM_QAM_TASKLETS_RUN__W                                         16
#define SCU_RAM_QAM_TASKLETS_RUN__M                                         0xFFFF
#define SCU_RAM_QAM_TASKLETS_RUN__PRE                                       0x0

#define   SCU_RAM_QAM_TASKLETS_RUN_BIT__B                                   0
#define   SCU_RAM_QAM_TASKLETS_RUN_BIT__W                                   16
#define   SCU_RAM_QAM_TASKLETS_RUN_BIT__M                                   0xFFFF
#define   SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE                                 0x0

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A                                 0x831FC1
#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W                                 16
#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M                                 0xFFFF
#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE                               0x0

#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B                           0
#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W                           16
#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M                           0xFFFF
#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE                         0x0

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A                                 0x831FC2
#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W                                 16
#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M                                 0xFFFF
#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE                               0x0

#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B                           0
#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W                           16
#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M                           0xFFFF
#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE                         0x0

#define SCU_RAM_QAM_RD_RSV_5__A                                             0x831FC3
#define SCU_RAM_QAM_RD_RSV_5__W                                             16
#define SCU_RAM_QAM_RD_RSV_5__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_5__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_5_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_5_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_5_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_5_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_6__A                                             0x831FC4
#define SCU_RAM_QAM_RD_RSV_6__W                                             16
#define SCU_RAM_QAM_RD_RSV_6__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_6__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_6_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_6_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_6_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_6_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_7__A                                             0x831FC5
#define SCU_RAM_QAM_RD_RSV_7__W                                             16
#define SCU_RAM_QAM_RD_RSV_7__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_7__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_7_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_7_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_7_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_7_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_8__A                                             0x831FC6
#define SCU_RAM_QAM_RD_RSV_8__W                                             16
#define SCU_RAM_QAM_RD_RSV_8__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_8__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_8_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_8_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_8_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_8_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_9__A                                             0x831FC7
#define SCU_RAM_QAM_RD_RSV_9__W                                             16
#define SCU_RAM_QAM_RD_RSV_9__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_9__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_9_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_9_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_9_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_9_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_10__A                                            0x831FC8
#define SCU_RAM_QAM_RD_RSV_10__W                                            16
#define SCU_RAM_QAM_RD_RSV_10__M                                            0xFFFF
#define SCU_RAM_QAM_RD_RSV_10__PRE                                          0x0

#define   SCU_RAM_QAM_RD_RSV_10_BIT__B                                      0
#define   SCU_RAM_QAM_RD_RSV_10_BIT__W                                      16
#define   SCU_RAM_QAM_RD_RSV_10_BIT__M                                      0xFFFF
#define   SCU_RAM_QAM_RD_RSV_10_BIT__PRE                                    0x0

#define SCU_RAM_QAM_AGC_TPOW_OFFS__A                                        0x831FC9
#define SCU_RAM_QAM_AGC_TPOW_OFFS__W                                        16
#define SCU_RAM_QAM_AGC_TPOW_OFFS__M                                        0xFFFF
#define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE                                      0x0

#define   SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B                                  0
#define   SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W                                  16
#define   SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M                                  0xFFFF
#define   SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE                                0x0

#define SCU_RAM_QAM_FSM_STATE__A                                            0x831FCA
#define SCU_RAM_QAM_FSM_STATE__W                                            4
#define SCU_RAM_QAM_FSM_STATE__M                                            0xF
#define SCU_RAM_QAM_FSM_STATE__PRE                                          0x0

#define   SCU_RAM_QAM_FSM_STATE_BIT__B                                      0
#define   SCU_RAM_QAM_FSM_STATE_BIT__W                                      4
#define   SCU_RAM_QAM_FSM_STATE_BIT__M                                      0xF
#define   SCU_RAM_QAM_FSM_STATE_BIT__PRE                                    0x0
#define     SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP                           0x0
#define     SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE                          0x1
#define     SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ                          0x2
#define     SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT                       0x3
#define     SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE                         0x4
#define     SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE                      0x5
#define     SCU_RAM_QAM_FSM_STATE_BIT_TRACKING                              0x6
#define     SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST                        0x7

#define SCU_RAM_QAM_FSM_STATE_NEW__A                                        0x831FCB
#define SCU_RAM_QAM_FSM_STATE_NEW__W                                        4
#define SCU_RAM_QAM_FSM_STATE_NEW__M                                        0xF
#define SCU_RAM_QAM_FSM_STATE_NEW__PRE                                      0x0

#define   SCU_RAM_QAM_FSM_STATE_NEW_BIT__B                                  0
#define   SCU_RAM_QAM_FSM_STATE_NEW_BIT__W                                  4
#define   SCU_RAM_QAM_FSM_STATE_NEW_BIT__M                                  0xF
#define   SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE                                0x0
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP                       0x0
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE                      0x1
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ                      0x2
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT                   0x3
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE                     0x4
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE                  0x5
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING                          0x6
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST                    0x7

#define SCU_RAM_QAM_FSM_LOCK_FLAGS__A                                       0x831FCC
#define SCU_RAM_QAM_FSM_LOCK_FLAGS__W                                       9
#define SCU_RAM_QAM_FSM_LOCK_FLAGS__M                                       0x1FF
#define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE                                     0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B                             0
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W                             1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M                             0x1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE                           0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B                         1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W                         1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M                         0x2
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE                       0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B                          2
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W                          1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M                          0x4
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE                        0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B                            3
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W                            1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M                            0x8
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE                          0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B                         4
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W                         1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M                         0x10
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE                       0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B                          5
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W                          1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M                          0x20
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE                        0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B                         6
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W                         1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M                         0x40
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE                       0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B                           7
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W                           1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M                           0x80
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE                         0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B                          8
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W                          1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M                          0x100
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE                        0x0

#define SCU_RAM_QAM_FSM_RATE_VARIATION__A                                   0x831FCD
#define SCU_RAM_QAM_FSM_RATE_VARIATION__W                                   16
#define SCU_RAM_QAM_FSM_RATE_VARIATION__M                                   0xFFFF
#define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE                                 0x0

#define   SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B                             0
#define   SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W                             16
#define   SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M                             0xFFFF
#define   SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE                           0x0

#define SCU_RAM_QAM_FSM_FREQ_VARIATION__A                                   0x831FCE
#define SCU_RAM_QAM_FSM_FREQ_VARIATION__W                                   16
#define SCU_RAM_QAM_FSM_FREQ_VARIATION__M                                   0xFFFF
#define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE                                 0x0

#define   SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B                             0
#define   SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W                             16
#define   SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M                             0xFFFF
#define   SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE                           0x0

#define SCU_RAM_QAM_ERR_STATE__A                                            0x831FCF
#define SCU_RAM_QAM_ERR_STATE__W                                            4
#define SCU_RAM_QAM_ERR_STATE__M                                            0xF
#define SCU_RAM_QAM_ERR_STATE__PRE                                          0x0

#define   SCU_RAM_QAM_ERR_STATE_BIT__B                                      0
#define   SCU_RAM_QAM_ERR_STATE_BIT__W                                      4
#define   SCU_RAM_QAM_ERR_STATE_BIT__M                                      0xF
#define   SCU_RAM_QAM_ERR_STATE_BIT__PRE                                    0x0
#define     SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP                           0x0
#define     SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE                          0x1
#define     SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ                          0x2
#define     SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT                       0x3
#define     SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE                         0x4
#define     SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE                      0x5
#define     SCU_RAM_QAM_ERR_STATE_BIT_TRACKING                              0x6
#define     SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST                        0x7

#define SCU_RAM_QAM_ERR_LOCK_FLAGS__A                                       0x831FD0
#define SCU_RAM_QAM_ERR_LOCK_FLAGS__W                                       9
#define SCU_RAM_QAM_ERR_LOCK_FLAGS__M                                       0x1FF
#define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE                                     0x0

#define   SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B                             0
#define   SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W                             1
#define   SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M                             0x1
#define   SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE                           0x0

#define SCU_RAM_QAM_EQ_LOCK__A                                              0x831FD1
#define SCU_RAM_QAM_EQ_LOCK__W                                              1
#define SCU_RAM_QAM_EQ_LOCK__M                                              0x1
#define SCU_RAM_QAM_EQ_LOCK__PRE                                            0x0

#define   SCU_RAM_QAM_EQ_LOCK_BIT__B                                        0
#define   SCU_RAM_QAM_EQ_LOCK_BIT__W                                        1
#define   SCU_RAM_QAM_EQ_LOCK_BIT__M                                        0x1
#define   SCU_RAM_QAM_EQ_LOCK_BIT__PRE                                      0x0

#define SCU_RAM_QAM_EQ_STATE__A                                             0x831FD2
#define SCU_RAM_QAM_EQ_STATE__W                                             16
#define SCU_RAM_QAM_EQ_STATE__M                                             0xFFFF
#define SCU_RAM_QAM_EQ_STATE__PRE                                           0x0

#define   SCU_RAM_QAM_EQ_STATE_BIT__B                                       0
#define   SCU_RAM_QAM_EQ_STATE_BIT__W                                       16
#define   SCU_RAM_QAM_EQ_STATE_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_EQ_STATE_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_0__A                                             0x831FD3
#define SCU_RAM_QAM_RD_RSV_0__W                                             16
#define SCU_RAM_QAM_RD_RSV_0__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_0__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_0_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_0_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_0_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_0_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_1__A                                             0x831FD4
#define SCU_RAM_QAM_RD_RSV_1__W                                             16
#define SCU_RAM_QAM_RD_RSV_1__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_1__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_1_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_1_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_1_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_1_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_2__A                                             0x831FD5
#define SCU_RAM_QAM_RD_RSV_2__W                                             16
#define SCU_RAM_QAM_RD_RSV_2__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_2__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_2_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_2_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_2_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_2_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_3__A                                             0x831FD6
#define SCU_RAM_QAM_RD_RSV_3__W                                             16
#define SCU_RAM_QAM_RD_RSV_3__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_3__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_3_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_3_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_3_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_3_BIT__PRE                                     0x0

#define SCU_RAM_VSB_CTL_MODE__A                                             0x831FD7
#define SCU_RAM_VSB_CTL_MODE__W                                             2
#define SCU_RAM_VSB_CTL_MODE__M                                             0x3
#define SCU_RAM_VSB_CTL_MODE__PRE                                           0x0

#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__B                          0
#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__W                          1
#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__M                          0x1
#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__PRE                        0x0
#define     SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_OFF                       0x0
#define     SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_ON                        0x1

#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__B                          1
#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__W                          1
#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__M                          0x2
#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__PRE                        0x0
#define     SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_OFF                       0x0
#define     SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_ON                        0x2

#define SCU_RAM_VSB_NOTCH_THRESHOLD__A                                      0x831FD8
#define SCU_RAM_VSB_NOTCH_THRESHOLD__W                                      16
#define SCU_RAM_VSB_NOTCH_THRESHOLD__M                                      0xFFFF
#define SCU_RAM_VSB_NOTCH_THRESHOLD__PRE                                    0x0

#define SCU_RAM_VSB_RSV_0__A                                                0x831FD9
#define SCU_RAM_VSB_RSV_0__W                                                16
#define SCU_RAM_VSB_RSV_0__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_0__PRE                                              0x0

#define SCU_RAM_VSB_RSV_1__A                                                0x831FDA
#define SCU_RAM_VSB_RSV_1__W                                                16
#define SCU_RAM_VSB_RSV_1__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_1__PRE                                              0x0

#define SCU_RAM_VSB_RSV_2__A                                                0x831FDB
#define SCU_RAM_VSB_RSV_2__W                                                16
#define SCU_RAM_VSB_RSV_2__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_2__PRE                                              0x0

#define SCU_RAM_VSB_RSV_3__A                                                0x831FDC
#define SCU_RAM_VSB_RSV_3__W                                                16
#define SCU_RAM_VSB_RSV_3__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_3__PRE                                              0x0

#define SCU_RAM_VSB_RSV_4__A                                                0x831FDD
#define SCU_RAM_VSB_RSV_4__W                                                16
#define SCU_RAM_VSB_RSV_4__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_4__PRE                                              0x0

#define SCU_RAM_VSB_RSV_5__A                                                0x831FDE
#define SCU_RAM_VSB_RSV_5__W                                                16
#define SCU_RAM_VSB_RSV_5__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_5__PRE                                              0x0

#define SCU_RAM_VSB_RSV_6__A                                                0x831FDF
#define SCU_RAM_VSB_RSV_6__W                                                16
#define SCU_RAM_VSB_RSV_6__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_6__PRE                                              0x0

#define SCU_RAM_VSB_RSV_7__A                                                0x831FE0
#define SCU_RAM_VSB_RSV_7__W                                                16
#define SCU_RAM_VSB_RSV_7__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_7__PRE                                              0x0

#define SCU_RAM_VSB_RSV_8__A                                                0x831FE1
#define SCU_RAM_VSB_RSV_8__W                                                16
#define SCU_RAM_VSB_RSV_8__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_8__PRE                                              0x0

#define SCU_RAM_VSB_RSV_9__A                                                0x831FE2
#define SCU_RAM_VSB_RSV_9__W                                                16
#define SCU_RAM_VSB_RSV_9__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_9__PRE                                              0x0

#define SCU_RAM_VSB_RSV_10__A                                               0x831FE3
#define SCU_RAM_VSB_RSV_10__W                                               16
#define SCU_RAM_VSB_RSV_10__M                                               0xFFFF
#define SCU_RAM_VSB_RSV_10__PRE                                             0x0

#define SCU_RAM_VSB_RSV_11__A                                               0x831FE4
#define SCU_RAM_VSB_RSV_11__W                                               16
#define SCU_RAM_VSB_RSV_11__M                                               0xFFFF
#define SCU_RAM_VSB_RSV_11__PRE                                             0x0

#define SCU_RAM_VSB_RSV_12__A                                               0x831FE5
#define SCU_RAM_VSB_RSV_12__W                                               16
#define SCU_RAM_VSB_RSV_12__M                                               0xFFFF
#define SCU_RAM_VSB_RSV_12__PRE                                             0x0

#define SCU_RAM_VSB_RSV_13__A                                               0x831FE6
#define SCU_RAM_VSB_RSV_13__W                                               16
#define SCU_RAM_VSB_RSV_13__M                                               0xFFFF
#define SCU_RAM_VSB_RSV_13__PRE                                             0x0

#define SCU_RAM_VSB_AGC_POW_TGT__A                                          0x831FE7
#define SCU_RAM_VSB_AGC_POW_TGT__W                                          15
#define SCU_RAM_VSB_AGC_POW_TGT__M                                          0x7FFF
#define SCU_RAM_VSB_AGC_POW_TGT__PRE                                        0x0

#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__A                                     0x831FE8
#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__W                                     8
#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__M                                     0xFF
#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__PRE                                   0x0

#define SCU_RAM_VSB_FIELD_NUMBER__A                                         0x831FE9
#define SCU_RAM_VSB_FIELD_NUMBER__W                                         9
#define SCU_RAM_VSB_FIELD_NUMBER__M                                         0x1FF
#define SCU_RAM_VSB_FIELD_NUMBER__PRE                                       0x0

#define SCU_RAM_VSB_SEGMENT_NUMBER__A                                       0x831FEA
#define SCU_RAM_VSB_SEGMENT_NUMBER__W                                       10
#define SCU_RAM_VSB_SEGMENT_NUMBER__M                                       0x3FF
#define SCU_RAM_VSB_SEGMENT_NUMBER__PRE                                     0x0

#define SCU_RAM_DRIVER_VER_HI__A                                            0x831FEB
#define SCU_RAM_DRIVER_VER_HI__W                                            16
#define SCU_RAM_DRIVER_VER_HI__M                                            0xFFFF
#define SCU_RAM_DRIVER_VER_HI__PRE                                          0x0

#define SCU_RAM_DRIVER_VER_LO__A                                            0x831FEC
#define SCU_RAM_DRIVER_VER_LO__W                                            16
#define SCU_RAM_DRIVER_VER_LO__M                                            0xFFFF
#define SCU_RAM_DRIVER_VER_LO__PRE                                          0x0

#define SCU_RAM_PARAM_15__A                                                 0x831FED
#define SCU_RAM_PARAM_15__W                                                 16
#define SCU_RAM_PARAM_15__M                                                 0xFFFF
#define SCU_RAM_PARAM_15__PRE                                               0x0

#define SCU_RAM_PARAM_14__A                                                 0x831FEE
#define SCU_RAM_PARAM_14__W                                                 16
#define SCU_RAM_PARAM_14__M                                                 0xFFFF
#define SCU_RAM_PARAM_14__PRE                                               0x0

#define SCU_RAM_PARAM_13__A                                                 0x831FEF
#define SCU_RAM_PARAM_13__W                                                 16
#define SCU_RAM_PARAM_13__M                                                 0xFFFF
#define SCU_RAM_PARAM_13__PRE                                               0x0

#define SCU_RAM_PARAM_12__A                                                 0x831FF0
#define SCU_RAM_PARAM_12__W                                                 16
#define SCU_RAM_PARAM_12__M                                                 0xFFFF
#define SCU_RAM_PARAM_12__PRE                                               0x0

#define SCU_RAM_PARAM_11__A                                                 0x831FF1
#define SCU_RAM_PARAM_11__W                                                 16
#define SCU_RAM_PARAM_11__M                                                 0xFFFF
#define SCU_RAM_PARAM_11__PRE                                               0x0

#define SCU_RAM_PARAM_10__A                                                 0x831FF2
#define SCU_RAM_PARAM_10__W                                                 16
#define SCU_RAM_PARAM_10__M                                                 0xFFFF
#define SCU_RAM_PARAM_10__PRE                                               0x0

#define SCU_RAM_PARAM_9__A                                                  0x831FF3
#define SCU_RAM_PARAM_9__W                                                  16
#define SCU_RAM_PARAM_9__M                                                  0xFFFF
#define SCU_RAM_PARAM_9__PRE                                                0x0

#define SCU_RAM_PARAM_8__A                                                  0x831FF4
#define SCU_RAM_PARAM_8__W                                                  16
#define SCU_RAM_PARAM_8__M                                                  0xFFFF
#define SCU_RAM_PARAM_8__PRE                                                0x0

#define SCU_RAM_PARAM_7__A                                                  0x831FF5
#define SCU_RAM_PARAM_7__W                                                  16
#define SCU_RAM_PARAM_7__M                                                  0xFFFF
#define SCU_RAM_PARAM_7__PRE                                                0x0

#define SCU_RAM_PARAM_6__A                                                  0x831FF6
#define SCU_RAM_PARAM_6__W                                                  16
#define SCU_RAM_PARAM_6__M                                                  0xFFFF
#define SCU_RAM_PARAM_6__PRE                                                0x0

#define SCU_RAM_PARAM_5__A                                                  0x831FF7
#define SCU_RAM_PARAM_5__W                                                  16
#define SCU_RAM_PARAM_5__M                                                  0xFFFF
#define SCU_RAM_PARAM_5__PRE                                                0x0

#define SCU_RAM_PARAM_4__A                                                  0x831FF8
#define SCU_RAM_PARAM_4__W                                                  16
#define SCU_RAM_PARAM_4__M                                                  0xFFFF
#define SCU_RAM_PARAM_4__PRE                                                0x0

#define SCU_RAM_PARAM_3__A                                                  0x831FF9
#define SCU_RAM_PARAM_3__W                                                  16
#define SCU_RAM_PARAM_3__M                                                  0xFFFF
#define SCU_RAM_PARAM_3__PRE                                                0x0

#define SCU_RAM_PARAM_2__A                                                  0x831FFA
#define SCU_RAM_PARAM_2__W                                                  16
#define SCU_RAM_PARAM_2__M                                                  0xFFFF
#define SCU_RAM_PARAM_2__PRE                                                0x0

#define SCU_RAM_PARAM_1__A                                                  0x831FFB
#define SCU_RAM_PARAM_1__W                                                  16
#define SCU_RAM_PARAM_1__M                                                  0xFFFF
#define SCU_RAM_PARAM_1__PRE                                                0x0
#define   SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED                     0x0
#define   SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED                   0x4000
#define   SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED                         0x8000
#define   SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK                     0xC000

#define SCU_RAM_PARAM_0__A                                                  0x831FFC
#define SCU_RAM_PARAM_0__W                                                  16
#define SCU_RAM_PARAM_0__M                                                  0xFFFF
#define SCU_RAM_PARAM_0__PRE                                                0x0
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD                      0x2
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD                       0x103
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD                       0x3
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD                      0x4
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD                       0x9
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD                      0x109
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD                       0xA
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD                      0x40
#define   SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A                          0x0
#define   SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B                          0x1
#define   SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C                          0x2
#define   SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D                          0x3
#define   SCU_RAM_PARAM_0_RESULT_OK                                         0x0
#define   SCU_RAM_PARAM_0_RESULT_UNKCMD                                     0xFFFF
#define   SCU_RAM_PARAM_0_RESULT_UNKSTD                                     0xFFFE
#define   SCU_RAM_PARAM_0_RESULT_INVPAR                                     0xFFFD
#define   SCU_RAM_PARAM_0_RESULT_SIZE                                       0xFFFC

#define SCU_RAM_COMMAND__A                                                  0x831FFD
#define SCU_RAM_COMMAND__W                                                  16
#define SCU_RAM_COMMAND__M                                                  0xFFFF
#define SCU_RAM_COMMAND__PRE                                                0x0
#define   SCU_RAM_COMMAND_CMD_DEMOD_RESET                                   0x1
#define   SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV                                 0x2
#define   SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM                               0x3
#define   SCU_RAM_COMMAND_CMD_DEMOD_START                                   0x4
#define   SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK                                0x5
#define   SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM                               0x6
#define   SCU_RAM_COMMAND_CMD_DEMOD_HOLD                                    0x7
#define   SCU_RAM_COMMAND_CMD_DEMOD_RESUME                                  0x8
#define   SCU_RAM_COMMAND_CMD_DEMOD_STOP                                    0x9
#define   SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE                          0x80
#define   SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE                        0x81
#define   SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL                            0x82
#define   SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR                           0x83
#define   SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE                            0x84
#define   SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE                         0x85
#define   SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS                            0x80
#define   SCU_RAM_COMMAND_CMD_DEBUG_HTOL                                    0x81
#define   SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER                       0x82
#define   SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK                       0x83
#define   SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK                        0x84
#define   SCU_RAM_COMMAND_CMD_ADMIN_NOP                                     0xFF
#define   SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION                             0xFE
#define   SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION                        0xFD
#define   SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS                         0xC0

#define   SCU_RAM_COMMAND_STANDARD__B                                       8
#define   SCU_RAM_COMMAND_STANDARD__W                                       8
#define   SCU_RAM_COMMAND_STANDARD__M                                       0xFF00
#define   SCU_RAM_COMMAND_STANDARD__PRE                                     0x0
#define     SCU_RAM_COMMAND_STANDARD_ATV                                    0x100
#define     SCU_RAM_COMMAND_STANDARD_QAM                                    0x200
#define     SCU_RAM_COMMAND_STANDARD_VSB                                    0x300
#define     SCU_RAM_COMMAND_STANDARD_OFDM                                   0x400
#define     SCU_RAM_COMMAND_STANDARD_OOB                                    0x8000
#define     SCU_RAM_COMMAND_STANDARD_TOP                                    0xFF00

#define SCU_RAM_VERSION_HI__A                                               0x831FFE
#define SCU_RAM_VERSION_HI__W                                               16
#define SCU_RAM_VERSION_HI__M                                               0xFFFF
#define SCU_RAM_VERSION_HI__PRE                                             0x0

#define   SCU_RAM_VERSION_HI_VER_MAJOR_N3__B                                12
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N3__W                                4
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N3__M                                0xF000
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE                              0x0

#define   SCU_RAM_VERSION_HI_VER_MAJOR_N2__B                                8
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N2__W                                4
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N2__M                                0xF00
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE                              0x0

#define   SCU_RAM_VERSION_HI_VER_MAJOR_N1__B                                4
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N1__W                                4
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N1__M                                0xF0
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE                              0x0

#define   SCU_RAM_VERSION_HI_VER_MINOR_N1__B                                0
#define   SCU_RAM_VERSION_HI_VER_MINOR_N1__W                                4
#define   SCU_RAM_VERSION_HI_VER_MINOR_N1__M                                0xF
#define   SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE                              0x0

#define SCU_RAM_VERSION_LO__A                                               0x831FFF
#define SCU_RAM_VERSION_LO__W                                               16
#define SCU_RAM_VERSION_LO__M                                               0xFFFF
#define SCU_RAM_VERSION_LO__PRE                                             0x0

#define   SCU_RAM_VERSION_LO_VER_PATCH_N4__B                                12
#define   SCU_RAM_VERSION_LO_VER_PATCH_N4__W                                4
#define   SCU_RAM_VERSION_LO_VER_PATCH_N4__M                                0xF000
#define   SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE                              0x0

#define   SCU_RAM_VERSION_LO_VER_PATCH_N3__B                                8
#define   SCU_RAM_VERSION_LO_VER_PATCH_N3__W                                4
#define   SCU_RAM_VERSION_LO_VER_PATCH_N3__M                                0xF00
#define   SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE                              0x0

#define   SCU_RAM_VERSION_LO_VER_PATCH_N2__B                                4
#define   SCU_RAM_VERSION_LO_VER_PATCH_N2__W                                4
#define   SCU_RAM_VERSION_LO_VER_PATCH_N2__M                                0xF0
#define   SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE                              0x0

#define   SCU_RAM_VERSION_LO_VER_PATCH_N1__B                                0
#define   SCU_RAM_VERSION_LO_VER_PATCH_N1__W                                4
#define   SCU_RAM_VERSION_LO_VER_PATCH_N1__M                                0xF
#define   SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE                              0x0

#define SIO_COMM_EXEC__A                                                    0x400000
#define SIO_COMM_EXEC__W                                                    2
#define SIO_COMM_EXEC__M                                                    0x3
#define SIO_COMM_EXEC__PRE                                                  0x0
#define   SIO_COMM_EXEC_STOP                                                0x0
#define   SIO_COMM_EXEC_ACTIVE                                              0x1
#define   SIO_COMM_EXEC_HOLD                                                0x2

#define SIO_COMM_STATE__A                                                   0x400001
#define SIO_COMM_STATE__W                                                   16
#define SIO_COMM_STATE__M                                                   0xFFFF
#define SIO_COMM_STATE__PRE                                                 0x0
#define SIO_COMM_MB__A                                                      0x400002
#define SIO_COMM_MB__W                                                      16
#define SIO_COMM_MB__M                                                      0xFFFF
#define SIO_COMM_MB__PRE                                                    0x0
#define SIO_COMM_INT_REQ__A                                                 0x400003
#define SIO_COMM_INT_REQ__W                                                 16
#define SIO_COMM_INT_REQ__M                                                 0xFFFF
#define SIO_COMM_INT_REQ__PRE                                               0x0

#define   SIO_COMM_INT_REQ_HI_REQ__B                                        0
#define   SIO_COMM_INT_REQ_HI_REQ__W                                        1
#define   SIO_COMM_INT_REQ_HI_REQ__M                                        0x1
#define   SIO_COMM_INT_REQ_HI_REQ__PRE                                      0x0

#define   SIO_COMM_INT_REQ_SA_REQ__B                                        1
#define   SIO_COMM_INT_REQ_SA_REQ__W                                        1
#define   SIO_COMM_INT_REQ_SA_REQ__M                                        0x2
#define   SIO_COMM_INT_REQ_SA_REQ__PRE                                      0x0

#define SIO_COMM_INT_STA__A                                                 0x400005
#define SIO_COMM_INT_STA__W                                                 16
#define SIO_COMM_INT_STA__M                                                 0xFFFF
#define SIO_COMM_INT_STA__PRE                                               0x0
#define SIO_COMM_INT_MSK__A                                                 0x400006
#define SIO_COMM_INT_MSK__W                                                 16
#define SIO_COMM_INT_MSK__M                                                 0xFFFF
#define SIO_COMM_INT_MSK__PRE                                               0x0
#define SIO_COMM_INT_STM__A                                                 0x400007
#define SIO_COMM_INT_STM__W                                                 16
#define SIO_COMM_INT_STM__M                                                 0xFFFF
#define SIO_COMM_INT_STM__PRE                                               0x0

#define SIO_TOP_COMM_EXEC__A                                                0x410000
#define SIO_TOP_COMM_EXEC__W                                                2
#define SIO_TOP_COMM_EXEC__M                                                0x3
#define SIO_TOP_COMM_EXEC__PRE                                              0x0
#define   SIO_TOP_COMM_EXEC_STOP                                            0x0
#define   SIO_TOP_COMM_EXEC_ACTIVE                                          0x1
#define   SIO_TOP_COMM_EXEC_HOLD                                            0x2

#define SIO_TOP_COMM_KEY__A                                                 0x41000F
#define SIO_TOP_COMM_KEY__W                                                 16
#define SIO_TOP_COMM_KEY__M                                                 0xFFFF
#define SIO_TOP_COMM_KEY__PRE                                               0x0
#define   SIO_TOP_COMM_KEY_KEY                                              0xFABA

#define SIO_TOP_JTAGID_LO__A                                                0x410012
#define SIO_TOP_JTAGID_LO__W                                                16
#define SIO_TOP_JTAGID_LO__M                                                0xFFFF
#define SIO_TOP_JTAGID_LO__PRE                                              0x0

#define SIO_TOP_JTAGID_HI__A                                                0x410013
#define SIO_TOP_JTAGID_HI__W                                                16
#define SIO_TOP_JTAGID_HI__M                                                0xFFFF
#define SIO_TOP_JTAGID_HI__PRE                                              0x0

#define SIO_HI_RA_RAM_S0_FLG_SMM__A                                         0x420010
#define SIO_HI_RA_RAM_S0_FLG_SMM__W                                         1
#define SIO_HI_RA_RAM_S0_FLG_SMM__M                                         0x1
#define SIO_HI_RA_RAM_S0_FLG_SMM__PRE                                       0x0

#define SIO_HI_RA_RAM_S0_DEV_ID__A                                          0x420011
#define SIO_HI_RA_RAM_S0_DEV_ID__W                                          7
#define SIO_HI_RA_RAM_S0_DEV_ID__M                                          0x7F
#define SIO_HI_RA_RAM_S0_DEV_ID__PRE                                        0x52

#define SIO_HI_RA_RAM_S0_FLG_CRC__A                                         0x420012
#define SIO_HI_RA_RAM_S0_FLG_CRC__W                                         1
#define SIO_HI_RA_RAM_S0_FLG_CRC__M                                         0x1
#define SIO_HI_RA_RAM_S0_FLG_CRC__PRE                                       0x0
#define SIO_HI_RA_RAM_S0_FLG_ACC__A                                         0x420013
#define SIO_HI_RA_RAM_S0_FLG_ACC__W                                         4
#define SIO_HI_RA_RAM_S0_FLG_ACC__M                                         0xF
#define SIO_HI_RA_RAM_S0_FLG_ACC__PRE                                       0x0

#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B                                0
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W                                2
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M                                0x3
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE                              0x0

#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B                            2
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W                            1
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M                            0x4
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE                          0x0

#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B                            3
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W                            1
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M                            0x8
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE                          0x0

#define SIO_HI_RA_RAM_S0_STATE__A                                           0x420014
#define SIO_HI_RA_RAM_S0_STATE__W                                           1
#define SIO_HI_RA_RAM_S0_STATE__M                                           0x1
#define SIO_HI_RA_RAM_S0_STATE__PRE                                         0x0

#define   SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B                              0
#define   SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W                              1
#define   SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M                              0x1
#define   SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE                            0x0

#define SIO_HI_RA_RAM_S0_BLK_BNK__A                                         0x420015
#define SIO_HI_RA_RAM_S0_BLK_BNK__W                                         12
#define SIO_HI_RA_RAM_S0_BLK_BNK__M                                         0xFFF
#define SIO_HI_RA_RAM_S0_BLK_BNK__PRE                                       0x82

#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B                            0
#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W                            6
#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M                            0x3F
#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE                          0x2

#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B                            6
#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W                            6
#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M                            0xFC0
#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE                          0x80

#define SIO_HI_RA_RAM_S0_ADDR__A                                            0x420016
#define SIO_HI_RA_RAM_S0_ADDR__W                                            16
#define SIO_HI_RA_RAM_S0_ADDR__M                                            0xFFFF
#define SIO_HI_RA_RAM_S0_ADDR__PRE                                          0x0

#define   SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B                              0
#define   SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W                              16
#define   SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M                              0xFFFF
#define   SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE                            0x0

#define SIO_HI_RA_RAM_S0_CRC__A                                             0x420017
#define SIO_HI_RA_RAM_S0_CRC__W                                             16
#define SIO_HI_RA_RAM_S0_CRC__M                                             0xFFFF
#define SIO_HI_RA_RAM_S0_CRC__PRE                                           0x0

#define SIO_HI_RA_RAM_S0_BUFFER__A                                          0x420018
#define SIO_HI_RA_RAM_S0_BUFFER__W                                          16
#define SIO_HI_RA_RAM_S0_BUFFER__M                                          0xFFFF
#define SIO_HI_RA_RAM_S0_BUFFER__PRE                                        0x0

#define SIO_HI_RA_RAM_S0_RMWBUF__A                                          0x420019
#define SIO_HI_RA_RAM_S0_RMWBUF__W                                          16
#define SIO_HI_RA_RAM_S0_RMWBUF__M                                          0xFFFF
#define SIO_HI_RA_RAM_S0_RMWBUF__PRE                                        0x0

#define SIO_HI_RA_RAM_S0_FLG_VB__A                                          0x42001A
#define SIO_HI_RA_RAM_S0_FLG_VB__W                                          1
#define SIO_HI_RA_RAM_S0_FLG_VB__M                                          0x1
#define SIO_HI_RA_RAM_S0_FLG_VB__PRE                                        0x0

#define SIO_HI_RA_RAM_S0_TEMP0__A                                           0x42001B
#define SIO_HI_RA_RAM_S0_TEMP0__W                                           16
#define SIO_HI_RA_RAM_S0_TEMP0__M                                           0xFFFF
#define SIO_HI_RA_RAM_S0_TEMP0__PRE                                         0x0

#define SIO_HI_RA_RAM_S0_TEMP1__A                                           0x42001C
#define SIO_HI_RA_RAM_S0_TEMP1__W                                           16
#define SIO_HI_RA_RAM_S0_TEMP1__M                                           0xFFFF
#define SIO_HI_RA_RAM_S0_TEMP1__PRE                                         0x0

#define SIO_HI_RA_RAM_S0_OFFSET__A                                          0x42001D
#define SIO_HI_RA_RAM_S0_OFFSET__W                                          16
#define SIO_HI_RA_RAM_S0_OFFSET__M                                          0xFFFF
#define SIO_HI_RA_RAM_S0_OFFSET__PRE                                        0x0

#define SIO_HI_RA_RAM_S1_FLG_SMM__A                                         0x420020
#define SIO_HI_RA_RAM_S1_FLG_SMM__W                                         1
#define SIO_HI_RA_RAM_S1_FLG_SMM__M                                         0x1
#define SIO_HI_RA_RAM_S1_FLG_SMM__PRE                                       0x0

#define SIO_HI_RA_RAM_S1_DEV_ID__A                                          0x420021
#define SIO_HI_RA_RAM_S1_DEV_ID__W                                          7
#define SIO_HI_RA_RAM_S1_DEV_ID__M                                          0x7F
#define SIO_HI_RA_RAM_S1_DEV_ID__PRE                                        0x52

#define SIO_HI_RA_RAM_S1_FLG_CRC__A                                         0x420022
#define SIO_HI_RA_RAM_S1_FLG_CRC__W                                         1
#define SIO_HI_RA_RAM_S1_FLG_CRC__M                                         0x1
#define SIO_HI_RA_RAM_S1_FLG_CRC__PRE                                       0x0
#define SIO_HI_RA_RAM_S1_FLG_ACC__A                                         0x420023
#define SIO_HI_RA_RAM_S1_FLG_ACC__W                                         4
#define SIO_HI_RA_RAM_S1_FLG_ACC__M                                         0xF
#define SIO_HI_RA_RAM_S1_FLG_ACC__PRE                                       0x0

#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B                                0
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W                                2
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M                                0x3
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE                              0x0

#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B                            2
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W                            1
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M                            0x4
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE                          0x0

#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B                            3
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W                            1
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M                            0x8
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE                          0x0

#define SIO_HI_RA_RAM_S1_STATE__A                                           0x420024
#define SIO_HI_RA_RAM_S1_STATE__W                                           1
#define SIO_HI_RA_RAM_S1_STATE__M                                           0x1
#define SIO_HI_RA_RAM_S1_STATE__PRE                                         0x0

#define   SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B                              0
#define   SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W                              1
#define   SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M                              0x1
#define   SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE                            0x0

#define SIO_HI_RA_RAM_S1_BLK_BNK__A                                         0x420025
#define SIO_HI_RA_RAM_S1_BLK_BNK__W                                         12
#define SIO_HI_RA_RAM_S1_BLK_BNK__M                                         0xFFF
#define SIO_HI_RA_RAM_S1_BLK_BNK__PRE                                       0x82

#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B                            0
#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W                            6
#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M                            0x3F
#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE                          0x2

#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B                            6
#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W                            6
#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M                            0xFC0
#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE                          0x80

#define SIO_HI_RA_RAM_S1_ADDR__A                                            0x420026
#define SIO_HI_RA_RAM_S1_ADDR__W                                            16
#define SIO_HI_RA_RAM_S1_ADDR__M                                            0xFFFF
#define SIO_HI_RA_RAM_S1_ADDR__PRE                                          0x0

#define   SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B                              0
#define   SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W                              16
#define   SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M                              0xFFFF
#define   SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE                            0x0

#define SIO_HI_RA_RAM_S1_CRC__A                                             0x420027
#define SIO_HI_RA_RAM_S1_CRC__W                                             16
#define SIO_HI_RA_RAM_S1_CRC__M                                             0xFFFF
#define SIO_HI_RA_RAM_S1_CRC__PRE                                           0x0

#define SIO_HI_RA_RAM_S1_BUFFER__A                                          0x420028
#define SIO_HI_RA_RAM_S1_BUFFER__W                                          16
#define SIO_HI_RA_RAM_S1_BUFFER__M                                          0xFFFF
#define SIO_HI_RA_RAM_S1_BUFFER__PRE                                        0x0

#define SIO_HI_RA_RAM_S1_RMWBUF__A                                          0x420029
#define SIO_HI_RA_RAM_S1_RMWBUF__W                                          16
#define SIO_HI_RA_RAM_S1_RMWBUF__M                                          0xFFFF
#define SIO_HI_RA_RAM_S1_RMWBUF__PRE                                        0x0

#define SIO_HI_RA_RAM_S1_FLG_VB__A                                          0x42002A
#define SIO_HI_RA_RAM_S1_FLG_VB__W                                          1
#define SIO_HI_RA_RAM_S1_FLG_VB__M                                          0x1
#define SIO_HI_RA_RAM_S1_FLG_VB__PRE                                        0x0

#define SIO_HI_RA_RAM_S1_TEMP0__A                                           0x42002B
#define SIO_HI_RA_RAM_S1_TEMP0__W                                           16
#define SIO_HI_RA_RAM_S1_TEMP0__M                                           0xFFFF
#define SIO_HI_RA_RAM_S1_TEMP0__PRE                                         0x0

#define SIO_HI_RA_RAM_S1_TEMP1__A                                           0x42002C
#define SIO_HI_RA_RAM_S1_TEMP1__W                                           16
#define SIO_HI_RA_RAM_S1_TEMP1__M                                           0xFFFF
#define SIO_HI_RA_RAM_S1_TEMP1__PRE                                         0x0

#define SIO_HI_RA_RAM_S1_OFFSET__A                                          0x42002D
#define SIO_HI_RA_RAM_S1_OFFSET__W                                          16
#define SIO_HI_RA_RAM_S1_OFFSET__M                                          0xFFFF
#define SIO_HI_RA_RAM_S1_OFFSET__PRE                                        0x0
#define SIO_HI_RA_RAM_SEMA__A                                               0x420030
#define SIO_HI_RA_RAM_SEMA__W                                               1
#define SIO_HI_RA_RAM_SEMA__M                                               0x1
#define SIO_HI_RA_RAM_SEMA__PRE                                             0x0
#define   SIO_HI_RA_RAM_SEMA_FREE                                           0x0
#define   SIO_HI_RA_RAM_SEMA_BUSY                                           0x1

#define SIO_HI_RA_RAM_RES__A                                                0x420031
#define SIO_HI_RA_RAM_RES__W                                                3
#define SIO_HI_RA_RAM_RES__M                                                0x7
#define SIO_HI_RA_RAM_RES__PRE                                              0x0
#define   SIO_HI_RA_RAM_RES_OK                                              0x0
#define   SIO_HI_RA_RAM_RES_ERROR                                           0x1
#define   SIO_HI_RA_RAM_RES_I2C_START_FOUND                                 0x1
#define   SIO_HI_RA_RAM_RES_I2C_STOP_FOUND                                  0x2
#define   SIO_HI_RA_RAM_RES_I2C_ARB_LOST                                    0x3
#define   SIO_HI_RA_RAM_RES_I2C_ERROR                                       0x4

#define SIO_HI_RA_RAM_CMD__A                                                0x420032
#define SIO_HI_RA_RAM_CMD__W                                                4
#define SIO_HI_RA_RAM_CMD__M                                                0xF
#define SIO_HI_RA_RAM_CMD__PRE                                              0x0
#define   SIO_HI_RA_RAM_CMD_NULL                                            0x0
#define   SIO_HI_RA_RAM_CMD_UIO                                             0x1
#define   SIO_HI_RA_RAM_CMD_RESET                                           0x2
#define   SIO_HI_RA_RAM_CMD_CONFIG                                          0x3
#define   SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER                               0x4
#define   SIO_HI_RA_RAM_CMD_I2C_TRANSMIT                                    0x5
#define   SIO_HI_RA_RAM_CMD_EXEC                                            0x6
#define   SIO_HI_RA_RAM_CMD_BRDCTRL                                         0x7
#define   SIO_HI_RA_RAM_CMD_ATOMIC_COPY                                     0x8

#define SIO_HI_RA_RAM_PAR_1__A                                              0x420033
#define SIO_HI_RA_RAM_PAR_1__W                                              16
#define SIO_HI_RA_RAM_PAR_1__M                                              0xFFFF
#define SIO_HI_RA_RAM_PAR_1__PRE                                            0x0
#define   SIO_HI_RA_RAM_PAR_1_PAR1__B                                       0
#define   SIO_HI_RA_RAM_PAR_1_PAR1__W                                       16
#define   SIO_HI_RA_RAM_PAR_1_PAR1__M                                       0xFFFF
#define   SIO_HI_RA_RAM_PAR_1_PAR1__PRE                                     0x0
#define     SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY                                0x3945

#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B                                0
#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W                                6
#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M                                0x3F
#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B                                6
#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W                                6
#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M                                0xFC0
#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B                                 0
#define   SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W                                 1
#define   SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M                                 0x1
#define   SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE                               0x0

#define   SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B                                  1
#define   SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W                                  1
#define   SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M                                  0x2
#define   SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE                                0x0
#define     SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE                           0x0
#define     SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE                            0x2

#define   SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B                                  0
#define   SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W                                  10
#define   SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M                                  0x3FF
#define   SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE                                0x0

#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B                                0
#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W                                6
#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M                                0x3F
#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B                                6
#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W                                6
#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M                                0xFC0
#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE                              0x0

#define SIO_HI_RA_RAM_PAR_2__A                                              0x420034
#define SIO_HI_RA_RAM_PAR_2__W                                              16
#define SIO_HI_RA_RAM_PAR_2__M                                              0xFFFF
#define SIO_HI_RA_RAM_PAR_2__PRE                                            0x0
#define   SIO_HI_RA_RAM_PAR_2_PAR2__B                                       0
#define   SIO_HI_RA_RAM_PAR_2_PAR2__W                                       16
#define   SIO_HI_RA_RAM_PAR_2_PAR2__M                                       0xFFFF
#define   SIO_HI_RA_RAM_PAR_2_PAR2__PRE                                     0x0

#define   SIO_HI_RA_RAM_PAR_2_CFG_DIV__B                                    0
#define   SIO_HI_RA_RAM_PAR_2_CFG_DIV__W                                    7
#define   SIO_HI_RA_RAM_PAR_2_CFG_DIV__M                                    0x7F
#define   SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE                                  0x25

#define   SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B                                0
#define   SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W                                16
#define   SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M                                0xFFFF
#define   SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B                                  0
#define   SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W                                  16
#define   SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M                                  0xFFFF
#define   SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE                                0x0

#define   SIO_HI_RA_RAM_PAR_2_BRD_CFG__B                                    2
#define   SIO_HI_RA_RAM_PAR_2_BRD_CFG__W                                    1
#define   SIO_HI_RA_RAM_PAR_2_BRD_CFG__M                                    0x4
#define   SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE                                  0x0
#define     SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN                                0x0
#define     SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED                              0x4

#define   SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B                                0
#define   SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W                                16
#define   SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M                                0xFFFF
#define   SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE                              0x0

#define SIO_HI_RA_RAM_PAR_3__A                                              0x420035
#define SIO_HI_RA_RAM_PAR_3__W                                              16
#define SIO_HI_RA_RAM_PAR_3__M                                              0xFFFF
#define SIO_HI_RA_RAM_PAR_3__PRE                                            0x0
#define   SIO_HI_RA_RAM_PAR_3_PAR3__B                                       0
#define   SIO_HI_RA_RAM_PAR_3_PAR3__W                                       16
#define   SIO_HI_RA_RAM_PAR_3_PAR3__M                                       0xFFFF
#define   SIO_HI_RA_RAM_PAR_3_PAR3__PRE                                     0x0

#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B                                0
#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W                                7
#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M                                0x7F
#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE                              0x3F

#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B                                7
#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W                                7
#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M                                0x3F80
#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE                              0x1F80

#define   SIO_HI_RA_RAM_PAR_3_ITX_LEN__B                                    0
#define   SIO_HI_RA_RAM_PAR_3_ITX_LEN__W                                    16
#define   SIO_HI_RA_RAM_PAR_3_ITX_LEN__M                                    0xFFFF
#define   SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE                                  0x0

#define   SIO_HI_RA_RAM_PAR_3_ACP_LEN__B                                    0
#define   SIO_HI_RA_RAM_PAR_3_ACP_LEN__W                                    3
#define   SIO_HI_RA_RAM_PAR_3_ACP_LEN__M                                    0x7
#define   SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE                                  0x0

#define   SIO_HI_RA_RAM_PAR_3_ACP_RW__B                                     3
#define   SIO_HI_RA_RAM_PAR_3_ACP_RW__W                                     1
#define   SIO_HI_RA_RAM_PAR_3_ACP_RW__M                                     0x8
#define   SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE                                   0x0
#define     SIO_HI_RA_RAM_PAR_3_ACP_RW_READ                                 0x0
#define     SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE                                0x8

#define SIO_HI_RA_RAM_PAR_4__A                                              0x420036
#define SIO_HI_RA_RAM_PAR_4__W                                              16
#define SIO_HI_RA_RAM_PAR_4__M                                              0xFFFF
#define SIO_HI_RA_RAM_PAR_4__PRE                                            0x0
#define   SIO_HI_RA_RAM_PAR_4_PAR4__B                                       0
#define   SIO_HI_RA_RAM_PAR_4_PAR4__W                                       16
#define   SIO_HI_RA_RAM_PAR_4_PAR4__M                                       0xFFFF
#define   SIO_HI_RA_RAM_PAR_4_PAR4__PRE                                     0x0

#define   SIO_HI_RA_RAM_PAR_4_CFG_WUP__B                                    0
#define   SIO_HI_RA_RAM_PAR_4_CFG_WUP__W                                    8
#define   SIO_HI_RA_RAM_PAR_4_CFG_WUP__M                                    0xFF
#define   SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE                                  0xC1

#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B                                0
#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W                                6
#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M                                0x3F
#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B                                6
#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W                                6
#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M                                0xFC0
#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B                                0
#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W                                6
#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M                                0x3F
#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B                                6
#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W                                6
#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M                                0xFC0
#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE                              0x0

#define SIO_HI_RA_RAM_PAR_5__A                                              0x420037
#define SIO_HI_RA_RAM_PAR_5__W                                              16
#define SIO_HI_RA_RAM_PAR_5__M                                              0xFFFF
#define SIO_HI_RA_RAM_PAR_5__PRE                                            0x0
#define   SIO_HI_RA_RAM_PAR_5_PAR5__B                                       0
#define   SIO_HI_RA_RAM_PAR_5_PAR5__W                                       16
#define   SIO_HI_RA_RAM_PAR_5_PAR5__M                                       0xFFFF
#define   SIO_HI_RA_RAM_PAR_5_PAR5__PRE                                     0x0

#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B                                   0
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W                                   1
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M                                   0x1
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE                                 0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE                           0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE                              0x1

#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B                                   1
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W                                   1
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M                                   0x2
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE                                 0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE                           0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE                              0x2

#define   SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B                                  3
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W                                  1
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M                                  0x8
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE                                0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE                             0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ                               0x8

#define   SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B                                  5
#define   SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W                                  1
#define   SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M                                  0x20
#define   SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE                                0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE                           0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE                            0x20

#define   SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B                                0
#define   SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W                                16
#define   SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M                                0xFFFF
#define   SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B                                0
#define   SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W                                16
#define   SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M                                0xFFFF
#define   SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE                              0x0

#define SIO_HI_RA_RAM_PAR_6__A                                              0x420038
#define SIO_HI_RA_RAM_PAR_6__W                                              16
#define SIO_HI_RA_RAM_PAR_6__M                                              0xFFFF
#define SIO_HI_RA_RAM_PAR_6__PRE                                            0x95FF
#define   SIO_HI_RA_RAM_PAR_6_PAR6__B                                       0
#define   SIO_HI_RA_RAM_PAR_6_PAR6__W                                       16
#define   SIO_HI_RA_RAM_PAR_6_PAR6__M                                       0xFFFF
#define   SIO_HI_RA_RAM_PAR_6_PAR6__PRE                                     0x0

#define   SIO_HI_RA_RAM_PAR_6_CFG_TOD__B                                    0
#define   SIO_HI_RA_RAM_PAR_6_CFG_TOD__W                                    8
#define   SIO_HI_RA_RAM_PAR_6_CFG_TOD__M                                    0xFF
#define   SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE                                  0xFF

#define   SIO_HI_RA_RAM_PAR_6_CFG_WDD__B                                    8
#define   SIO_HI_RA_RAM_PAR_6_CFG_WDD__W                                    8
#define   SIO_HI_RA_RAM_PAR_6_CFG_WDD__M                                    0xFF00
#define   SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE                                  0x9500

#define SIO_HI_RA_RAM_AB_TEMP__A                                            0x42006E
#define SIO_HI_RA_RAM_AB_TEMP__W                                            16
#define SIO_HI_RA_RAM_AB_TEMP__M                                            0xFFFF
#define SIO_HI_RA_RAM_AB_TEMP__PRE                                          0x0

#define SIO_HI_RA_RAM_I2C_CTL__A                                            0x42006F
#define SIO_HI_RA_RAM_I2C_CTL__W                                            16
#define SIO_HI_RA_RAM_I2C_CTL__M                                            0xFFFF
#define SIO_HI_RA_RAM_I2C_CTL__PRE                                          0x0

#define SIO_HI_RA_RAM_VB_ENTRY0__A                                          0x420070
#define SIO_HI_RA_RAM_VB_ENTRY0__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY0__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY0__PRE                                        0x0

#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B                             0
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W                             4
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M                             0xF
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE                           0x0

#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B                             4
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W                             4
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M                             0xF0
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE                           0x0

#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B                            8
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W                            4
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M                            0xF00
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE                          0x0

#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B                            12
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W                            4
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M                            0xF000
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE                          0x0

#define SIO_HI_RA_RAM_VB_OFFSET0__A                                         0x420071
#define SIO_HI_RA_RAM_VB_OFFSET0__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET0__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET0__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B                           0
#define   SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W                           16
#define   SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M                           0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE                         0x0

#define SIO_HI_RA_RAM_VB_ENTRY1__A                                          0x420072
#define SIO_HI_RA_RAM_VB_ENTRY1__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY1__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY1__PRE                                        0x0
#define SIO_HI_RA_RAM_VB_OFFSET1__A                                         0x420073
#define SIO_HI_RA_RAM_VB_OFFSET1__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET1__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET1__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B                            0
#define   SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W                            16
#define   SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M                            0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE                          0x0

#define SIO_HI_RA_RAM_VB_ENTRY2__A                                          0x420074
#define SIO_HI_RA_RAM_VB_ENTRY2__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY2__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY2__PRE                                        0x0
#define SIO_HI_RA_RAM_VB_OFFSET2__A                                         0x420075
#define SIO_HI_RA_RAM_VB_OFFSET2__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET2__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET2__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B                            0
#define   SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W                            16
#define   SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M                            0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE                          0x0

#define SIO_HI_RA_RAM_VB_ENTRY3__A                                          0x420076
#define SIO_HI_RA_RAM_VB_ENTRY3__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY3__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY3__PRE                                        0x0
#define SIO_HI_RA_RAM_VB_OFFSET3__A                                         0x420077
#define SIO_HI_RA_RAM_VB_OFFSET3__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET3__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET3__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B                            0
#define   SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W                            16
#define   SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M                            0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE                          0x0

#define SIO_HI_RA_RAM_VB_ENTRY4__A                                          0x420078
#define SIO_HI_RA_RAM_VB_ENTRY4__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY4__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY4__PRE                                        0x0
#define SIO_HI_RA_RAM_VB_OFFSET4__A                                         0x420079
#define SIO_HI_RA_RAM_VB_OFFSET4__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET4__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET4__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B                            0
#define   SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W                            16
#define   SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M                            0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE                          0x0

#define SIO_HI_RA_RAM_VB_ENTRY5__A                                          0x42007A
#define SIO_HI_RA_RAM_VB_ENTRY5__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY5__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY5__PRE                                        0x0
#define SIO_HI_RA_RAM_VB_OFFSET5__A                                         0x42007B
#define SIO_HI_RA_RAM_VB_OFFSET5__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET5__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET5__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B                            0
#define   SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W                            16
#define   SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M                            0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE                          0x0

#define SIO_HI_RA_RAM_VB_ENTRY6__A                                          0x42007C
#define SIO_HI_RA_RAM_VB_ENTRY6__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY6__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY6__PRE                                        0x0
#define SIO_HI_RA_RAM_VB_OFFSET6__A                                         0x42007D
#define SIO_HI_RA_RAM_VB_OFFSET6__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET6__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET6__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B                            0
#define   SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W                            16
#define   SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M                            0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE                          0x0

#define SIO_HI_RA_RAM_VB_ENTRY7__A                                          0x42007E
#define SIO_HI_RA_RAM_VB_ENTRY7__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY7__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY7__PRE                                        0x0
#define SIO_HI_RA_RAM_VB_OFFSET7__A                                         0x42007F
#define SIO_HI_RA_RAM_VB_OFFSET7__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET7__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET7__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B                            0
#define   SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W                            16
#define   SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M                            0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE                          0x0

#define SIO_HI_IF_RAM_TRP_BPT_0__A                                          0x430000
#define SIO_HI_IF_RAM_TRP_BPT_0__W                                          12
#define SIO_HI_IF_RAM_TRP_BPT_0__M                                          0xFFF
#define SIO_HI_IF_RAM_TRP_BPT_0__PRE                                        0x0
#define SIO_HI_IF_RAM_TRP_BPT_1__A                                          0x430001
#define SIO_HI_IF_RAM_TRP_BPT_1__W                                          12
#define SIO_HI_IF_RAM_TRP_BPT_1__M                                          0xFFF
#define SIO_HI_IF_RAM_TRP_BPT_1__PRE                                        0x0
#define SIO_HI_IF_RAM_TRP_STK_0__A                                          0x430002
#define SIO_HI_IF_RAM_TRP_STK_0__W                                          12
#define SIO_HI_IF_RAM_TRP_STK_0__M                                          0xFFF
#define SIO_HI_IF_RAM_TRP_STK_0__PRE                                        0x0
#define SIO_HI_IF_RAM_TRP_STK_1__A                                          0x430003
#define SIO_HI_IF_RAM_TRP_STK_1__W                                          12
#define SIO_HI_IF_RAM_TRP_STK_1__M                                          0xFFF
#define SIO_HI_IF_RAM_TRP_STK_1__PRE                                        0x0
#define SIO_HI_IF_RAM_FUN_BASE__A                                           0x430300
#define SIO_HI_IF_RAM_FUN_BASE__W                                           12
#define SIO_HI_IF_RAM_FUN_BASE__M                                           0xFFF
#define SIO_HI_IF_RAM_FUN_BASE__PRE                                         0x0

#define SIO_HI_IF_COMM_EXEC__A                                              0x440000
#define SIO_HI_IF_COMM_EXEC__W                                              2
#define SIO_HI_IF_COMM_EXEC__M                                              0x3
#define SIO_HI_IF_COMM_EXEC__PRE                                            0x0
#define   SIO_HI_IF_COMM_EXEC_STOP                                          0x0
#define   SIO_HI_IF_COMM_EXEC_ACTIVE                                        0x1
#define   SIO_HI_IF_COMM_EXEC_HOLD                                          0x2
#define   SIO_HI_IF_COMM_EXEC_STEP                                          0x3

#define SIO_HI_IF_COMM_STATE__A                                             0x440001
#define SIO_HI_IF_COMM_STATE__W                                             10
#define SIO_HI_IF_COMM_STATE__M                                             0x3FF
#define SIO_HI_IF_COMM_STATE__PRE                                           0x0
#define SIO_HI_IF_COMM_INT_REQ__A                                           0x440003
#define SIO_HI_IF_COMM_INT_REQ__W                                           1
#define SIO_HI_IF_COMM_INT_REQ__M                                           0x1
#define SIO_HI_IF_COMM_INT_REQ__PRE                                         0x0
#define SIO_HI_IF_COMM_INT_STA__A                                           0x440005
#define SIO_HI_IF_COMM_INT_STA__W                                           1
#define SIO_HI_IF_COMM_INT_STA__M                                           0x1
#define SIO_HI_IF_COMM_INT_STA__PRE                                         0x0
#define   SIO_HI_IF_COMM_INT_STA_STAT__B                                    0
#define   SIO_HI_IF_COMM_INT_STA_STAT__W                                    1
#define   SIO_HI_IF_COMM_INT_STA_STAT__M                                    0x1
#define   SIO_HI_IF_COMM_INT_STA_STAT__PRE                                  0x0

#define SIO_HI_IF_COMM_INT_MSK__A                                           0x440006
#define SIO_HI_IF_COMM_INT_MSK__W                                           1
#define SIO_HI_IF_COMM_INT_MSK__M                                           0x1
#define SIO_HI_IF_COMM_INT_MSK__PRE                                         0x0
#define   SIO_HI_IF_COMM_INT_MSK_STAT__B                                    0
#define   SIO_HI_IF_COMM_INT_MSK_STAT__W                                    1
#define   SIO_HI_IF_COMM_INT_MSK_STAT__M                                    0x1
#define   SIO_HI_IF_COMM_INT_MSK_STAT__PRE                                  0x0

#define SIO_HI_IF_COMM_INT_STM__A                                           0x440007
#define SIO_HI_IF_COMM_INT_STM__W                                           1
#define SIO_HI_IF_COMM_INT_STM__M                                           0x1
#define SIO_HI_IF_COMM_INT_STM__PRE                                         0x0
#define   SIO_HI_IF_COMM_INT_STM_STAT__B                                    0
#define   SIO_HI_IF_COMM_INT_STM_STAT__W                                    1
#define   SIO_HI_IF_COMM_INT_STM_STAT__M                                    0x1
#define   SIO_HI_IF_COMM_INT_STM_STAT__PRE                                  0x0

#define SIO_HI_IF_STK_0__A                                                  0x440010
#define SIO_HI_IF_STK_0__W                                                  10
#define SIO_HI_IF_STK_0__M                                                  0x3FF
#define SIO_HI_IF_STK_0__PRE                                                0x2

#define   SIO_HI_IF_STK_0_ADDR__B                                           0
#define   SIO_HI_IF_STK_0_ADDR__W                                           10
#define   SIO_HI_IF_STK_0_ADDR__M                                           0x3FF
#define   SIO_HI_IF_STK_0_ADDR__PRE                                         0x2

#define SIO_HI_IF_STK_1__A                                                  0x440011
#define SIO_HI_IF_STK_1__W                                                  10
#define SIO_HI_IF_STK_1__M                                                  0x3FF
#define SIO_HI_IF_STK_1__PRE                                                0x2
#define   SIO_HI_IF_STK_1_ADDR__B                                           0
#define   SIO_HI_IF_STK_1_ADDR__W                                           10
#define   SIO_HI_IF_STK_1_ADDR__M                                           0x3FF
#define   SIO_HI_IF_STK_1_ADDR__PRE                                         0x2

#define SIO_HI_IF_STK_2__A                                                  0x440012
#define SIO_HI_IF_STK_2__W                                                  10
#define SIO_HI_IF_STK_2__M                                                  0x3FF
#define SIO_HI_IF_STK_2__PRE                                                0x2
#define   SIO_HI_IF_STK_2_ADDR__B                                           0
#define   SIO_HI_IF_STK_2_ADDR__W                                           10
#define   SIO_HI_IF_STK_2_ADDR__M                                           0x3FF
#define   SIO_HI_IF_STK_2_ADDR__PRE                                         0x2

#define SIO_HI_IF_STK_3__A                                                  0x440013
#define SIO_HI_IF_STK_3__W                                                  10
#define SIO_HI_IF_STK_3__M                                                  0x3FF
#define SIO_HI_IF_STK_3__PRE                                                0x2

#define   SIO_HI_IF_STK_3_ADDR__B                                           0
#define   SIO_HI_IF_STK_3_ADDR__W                                           10
#define   SIO_HI_IF_STK_3_ADDR__M                                           0x3FF
#define   SIO_HI_IF_STK_3_ADDR__PRE                                         0x2

#define SIO_HI_IF_BPT_IDX__A                                                0x44001F
#define SIO_HI_IF_BPT_IDX__W                                                1
#define SIO_HI_IF_BPT_IDX__M                                                0x1
#define SIO_HI_IF_BPT_IDX__PRE                                              0x0

#define   SIO_HI_IF_BPT_IDX_ADDR__B                                         0
#define   SIO_HI_IF_BPT_IDX_ADDR__W                                         1
#define   SIO_HI_IF_BPT_IDX_ADDR__M                                         0x1
#define   SIO_HI_IF_BPT_IDX_ADDR__PRE                                       0x0

#define SIO_HI_IF_BPT__A                                                    0x440020
#define SIO_HI_IF_BPT__W                                                    10
#define SIO_HI_IF_BPT__M                                                    0x3FF
#define SIO_HI_IF_BPT__PRE                                                  0x2

#define   SIO_HI_IF_BPT_ADDR__B                                             0
#define   SIO_HI_IF_BPT_ADDR__W                                             10
#define   SIO_HI_IF_BPT_ADDR__M                                             0x3FF
#define   SIO_HI_IF_BPT_ADDR__PRE                                           0x2

#define SIO_CC_COMM_EXEC__A                                                 0x450000
#define SIO_CC_COMM_EXEC__W                                                 2
#define SIO_CC_COMM_EXEC__M                                                 0x3
#define SIO_CC_COMM_EXEC__PRE                                               0x0
#define   SIO_CC_COMM_EXEC_STOP                                             0x0
#define   SIO_CC_COMM_EXEC_ACTIVE                                           0x1
#define   SIO_CC_COMM_EXEC_HOLD                                             0x2

#define SIO_CC_PLL_MODE__A                                                  0x450010
#define SIO_CC_PLL_MODE__W                                                  6
#define SIO_CC_PLL_MODE__M                                                  0x3F
#define SIO_CC_PLL_MODE__PRE                                                0x0

#define   SIO_CC_PLL_MODE_FREF_SEL__B                                       0
#define   SIO_CC_PLL_MODE_FREF_SEL__W                                       2
#define   SIO_CC_PLL_MODE_FREF_SEL__M                                       0x3
#define   SIO_CC_PLL_MODE_FREF_SEL__PRE                                     0x0
#define     SIO_CC_PLL_MODE_FREF_SEL_OHW                                    0x0
#define     SIO_CC_PLL_MODE_FREF_SEL_27_00                                  0x1
#define     SIO_CC_PLL_MODE_FREF_SEL_20_25                                  0x2
#define     SIO_CC_PLL_MODE_FREF_SEL_4_00                                   0x3

#define   SIO_CC_PLL_MODE_LOCKSEL__B                                        2
#define   SIO_CC_PLL_MODE_LOCKSEL__W                                        2
#define   SIO_CC_PLL_MODE_LOCKSEL__M                                        0xC
#define   SIO_CC_PLL_MODE_LOCKSEL__PRE                                      0x0

#define   SIO_CC_PLL_MODE_BYPASS__B                                         4
#define   SIO_CC_PLL_MODE_BYPASS__W                                         2
#define   SIO_CC_PLL_MODE_BYPASS__M                                         0x30
#define   SIO_CC_PLL_MODE_BYPASS__PRE                                       0x0
#define     SIO_CC_PLL_MODE_BYPASS_OHW                                      0x0
#define     SIO_CC_PLL_MODE_BYPASS_OFF                                      0x10
#define     SIO_CC_PLL_MODE_BYPASS_ON                                       0x20

#define SIO_CC_PLL_TEST__A                                                  0x450011
#define SIO_CC_PLL_TEST__W                                                  8
#define SIO_CC_PLL_TEST__M                                                  0xFF
#define SIO_CC_PLL_TEST__PRE                                                0x0

#define SIO_CC_PLL_LOCK__A                                                  0x450012
#define SIO_CC_PLL_LOCK__W                                                  1
#define SIO_CC_PLL_LOCK__M                                                  0x1
#define SIO_CC_PLL_LOCK__PRE                                                0x0
#define SIO_CC_CLK_MODE__A                                                  0x450014
#define SIO_CC_CLK_MODE__W                                                  5
#define SIO_CC_CLK_MODE__M                                                  0x1F
#define SIO_CC_CLK_MODE__PRE                                                0x0

#define   SIO_CC_CLK_MODE_DELAY__B                                          0
#define   SIO_CC_CLK_MODE_DELAY__W                                          4
#define   SIO_CC_CLK_MODE_DELAY__M                                          0xF
#define   SIO_CC_CLK_MODE_DELAY__PRE                                        0x0

#define   SIO_CC_CLK_MODE_INVERT__B                                         4
#define   SIO_CC_CLK_MODE_INVERT__W                                         1
#define   SIO_CC_CLK_MODE_INVERT__M                                         0x10
#define   SIO_CC_CLK_MODE_INVERT__PRE                                       0x0

#define SIO_CC_PWD_MODE__A                                                  0x450015
#define SIO_CC_PWD_MODE__W                                                  3
#define SIO_CC_PWD_MODE__M                                                  0x7
#define SIO_CC_PWD_MODE__PRE                                                0x0

#define   SIO_CC_PWD_MODE_LEVEL__B                                          0
#define   SIO_CC_PWD_MODE_LEVEL__W                                          2
#define   SIO_CC_PWD_MODE_LEVEL__M                                          0x3
#define   SIO_CC_PWD_MODE_LEVEL__PRE                                        0x0
#define     SIO_CC_PWD_MODE_LEVEL_NONE                                      0x0
#define     SIO_CC_PWD_MODE_LEVEL_CLOCK                                     0x1
#define     SIO_CC_PWD_MODE_LEVEL_PLL                                       0x2
#define     SIO_CC_PWD_MODE_LEVEL_OSC                                       0x3

#define   SIO_CC_PWD_MODE_USE_LOCK__B                                       2
#define   SIO_CC_PWD_MODE_USE_LOCK__W                                       1
#define   SIO_CC_PWD_MODE_USE_LOCK__M                                       0x4
#define   SIO_CC_PWD_MODE_USE_LOCK__PRE                                     0x0

#define SIO_CC_SOFT_RST__A                                                  0x450016
#define SIO_CC_SOFT_RST__W                                                  2
#define SIO_CC_SOFT_RST__M                                                  0x3
#define SIO_CC_SOFT_RST__PRE                                                0x0

#define   SIO_CC_SOFT_RST_SYS__B                                            0
#define   SIO_CC_SOFT_RST_SYS__W                                            1
#define   SIO_CC_SOFT_RST_SYS__M                                            0x1
#define   SIO_CC_SOFT_RST_SYS__PRE                                          0x0

#define   SIO_CC_SOFT_RST_OSC__B                                            1
#define   SIO_CC_SOFT_RST_OSC__W                                            1
#define   SIO_CC_SOFT_RST_OSC__M                                            0x2
#define   SIO_CC_SOFT_RST_OSC__PRE                                          0x0

#define SIO_CC_UPDATE__A                                                    0x450017
#define SIO_CC_UPDATE__W                                                    16
#define SIO_CC_UPDATE__M                                                    0xFFFF
#define SIO_CC_UPDATE__PRE                                                  0x0
#define   SIO_CC_UPDATE_KEY                                                 0xFABA

#define SIO_SA_COMM_EXEC__A                                                 0x460000
#define SIO_SA_COMM_EXEC__W                                                 2
#define SIO_SA_COMM_EXEC__M                                                 0x3
#define SIO_SA_COMM_EXEC__PRE                                               0x0
#define   SIO_SA_COMM_EXEC_STOP                                             0x0
#define   SIO_SA_COMM_EXEC_ACTIVE                                           0x1
#define   SIO_SA_COMM_EXEC_HOLD                                             0x2

#define SIO_SA_COMM_INT_REQ__A                                              0x460003
#define SIO_SA_COMM_INT_REQ__W                                              1
#define SIO_SA_COMM_INT_REQ__M                                              0x1
#define SIO_SA_COMM_INT_REQ__PRE                                            0x0
#define SIO_SA_COMM_INT_STA__A                                              0x460005
#define SIO_SA_COMM_INT_STA__W                                              4
#define SIO_SA_COMM_INT_STA__M                                              0xF
#define SIO_SA_COMM_INT_STA__PRE                                            0x0

#define   SIO_SA_COMM_INT_STA_TR_END_INT_STA__B                             0
#define   SIO_SA_COMM_INT_STA_TR_END_INT_STA__W                             1
#define   SIO_SA_COMM_INT_STA_TR_END_INT_STA__M                             0x1
#define   SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE                           0x0

#define   SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B                          1
#define   SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W                          1
#define   SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M                          0x2
#define   SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE                        0x0

#define   SIO_SA_COMM_INT_STA_RX_END_INT_STA__B                             2
#define   SIO_SA_COMM_INT_STA_RX_END_INT_STA__W                             1
#define   SIO_SA_COMM_INT_STA_RX_END_INT_STA__M                             0x4
#define   SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE                           0x0

#define   SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B                           3
#define   SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W                           1
#define   SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M                           0x8
#define   SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE                         0x0

#define SIO_SA_COMM_INT_MSK__A                                              0x460006
#define SIO_SA_COMM_INT_MSK__W                                              4
#define SIO_SA_COMM_INT_MSK__M                                              0xF
#define SIO_SA_COMM_INT_MSK__PRE                                            0x0

#define   SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B                            0
#define   SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W                            1
#define   SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M                            0x1
#define   SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE                          0x0

#define   SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B                         1
#define   SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W                         1
#define   SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M                         0x2
#define   SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE                       0x0

#define   SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B                            2
#define   SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W                            1
#define   SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M                            0x4
#define   SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE                          0x0

#define   SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B                          3
#define   SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W                          1
#define   SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M                          0x8
#define   SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE                        0x0

#define SIO_SA_COMM_INT_STM__A                                              0x460007
#define SIO_SA_COMM_INT_STM__W                                              4
#define SIO_SA_COMM_INT_STM__M                                              0xF
#define SIO_SA_COMM_INT_STM__PRE                                            0x0

#define   SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B                            0
#define   SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W                            1
#define   SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M                            0x1
#define   SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE                          0x0

#define   SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B                         1
#define   SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W                         1
#define   SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M                         0x2
#define   SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE                       0x0

#define   SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B                            2
#define   SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W                            1
#define   SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M                            0x4
#define   SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE                          0x0

#define   SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B                          3
#define   SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W                          1
#define   SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M                          0x8
#define   SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE                        0x0

#define SIO_SA_PRESCALER__A                                                 0x460010
#define SIO_SA_PRESCALER__W                                                 13
#define SIO_SA_PRESCALER__M                                                 0x1FFF
#define SIO_SA_PRESCALER__PRE                                               0x18B7
#define SIO_SA_TX_DATA0__A                                                  0x460011
#define SIO_SA_TX_DATA0__W                                                  16
#define SIO_SA_TX_DATA0__M                                                  0xFFFF
#define SIO_SA_TX_DATA0__PRE                                                0x0
#define SIO_SA_TX_DATA1__A                                                  0x460012
#define SIO_SA_TX_DATA1__W                                                  16
#define SIO_SA_TX_DATA1__M                                                  0xFFFF
#define SIO_SA_TX_DATA1__PRE                                                0x0
#define SIO_SA_TX_DATA2__A                                                  0x460013
#define SIO_SA_TX_DATA2__W                                                  16
#define SIO_SA_TX_DATA2__M                                                  0xFFFF
#define SIO_SA_TX_DATA2__PRE                                                0x0
#define SIO_SA_TX_DATA3__A                                                  0x460014
#define SIO_SA_TX_DATA3__W                                                  16
#define SIO_SA_TX_DATA3__M                                                  0xFFFF
#define SIO_SA_TX_DATA3__PRE                                                0x0
#define SIO_SA_TX_LENGTH__A                                                 0x460015
#define SIO_SA_TX_LENGTH__W                                                 6
#define SIO_SA_TX_LENGTH__M                                                 0x3F
#define SIO_SA_TX_LENGTH__PRE                                               0x0
#define SIO_SA_TX_COMMAND__A                                                0x460016
#define SIO_SA_TX_COMMAND__W                                                2
#define SIO_SA_TX_COMMAND__M                                                0x3
#define SIO_SA_TX_COMMAND__PRE                                              0x3

#define   SIO_SA_TX_COMMAND_TX_INVERT__B                                    0
#define   SIO_SA_TX_COMMAND_TX_INVERT__W                                    1
#define   SIO_SA_TX_COMMAND_TX_INVERT__M                                    0x1
#define   SIO_SA_TX_COMMAND_TX_INVERT__PRE                                  0x1

#define   SIO_SA_TX_COMMAND_TX_ENABLE__B                                    1
#define   SIO_SA_TX_COMMAND_TX_ENABLE__W                                    1
#define   SIO_SA_TX_COMMAND_TX_ENABLE__M                                    0x2
#define   SIO_SA_TX_COMMAND_TX_ENABLE__PRE                                  0x2

#define SIO_SA_TX_STATUS__A                                                 0x460017
#define SIO_SA_TX_STATUS__W                                                 2
#define SIO_SA_TX_STATUS__M                                                 0x3
#define SIO_SA_TX_STATUS__PRE                                               0x0

#define   SIO_SA_TX_STATUS_BUSY__B                                          0
#define   SIO_SA_TX_STATUS_BUSY__W                                          1
#define   SIO_SA_TX_STATUS_BUSY__M                                          0x1
#define   SIO_SA_TX_STATUS_BUSY__PRE                                        0x0

#define   SIO_SA_TX_STATUS_BUFF_FULL__B                                     1
#define   SIO_SA_TX_STATUS_BUFF_FULL__W                                     1
#define   SIO_SA_TX_STATUS_BUFF_FULL__M                                     0x2
#define   SIO_SA_TX_STATUS_BUFF_FULL__PRE                                   0x0

#define SIO_SA_RX_DATA0__A                                                  0x460018
#define SIO_SA_RX_DATA0__W                                                  16
#define SIO_SA_RX_DATA0__M                                                  0xFFFF
#define SIO_SA_RX_DATA0__PRE                                                0x0
#define SIO_SA_RX_DATA1__A                                                  0x460019
#define SIO_SA_RX_DATA1__W                                                  16
#define SIO_SA_RX_DATA1__M                                                  0xFFFF
#define SIO_SA_RX_DATA1__PRE                                                0x0
#define SIO_SA_RX_LENGTH__A                                                 0x46001A
#define SIO_SA_RX_LENGTH__W                                                 6
#define SIO_SA_RX_LENGTH__M                                                 0x3F
#define SIO_SA_RX_LENGTH__PRE                                               0x0
#define SIO_SA_RX_COMMAND__A                                                0x46001B
#define SIO_SA_RX_COMMAND__W                                                1
#define SIO_SA_RX_COMMAND__M                                                0x1
#define SIO_SA_RX_COMMAND__PRE                                              0x1

#define   SIO_SA_RX_COMMAND_RX_INVERT__B                                    0
#define   SIO_SA_RX_COMMAND_RX_INVERT__W                                    1
#define   SIO_SA_RX_COMMAND_RX_INVERT__M                                    0x1
#define   SIO_SA_RX_COMMAND_RX_INVERT__PRE                                  0x1

#define SIO_SA_RX_STATUS__A                                                 0x46001C
#define SIO_SA_RX_STATUS__W                                                 2
#define SIO_SA_RX_STATUS__M                                                 0x3
#define SIO_SA_RX_STATUS__PRE                                               0x0

#define   SIO_SA_RX_STATUS_BUSY__B                                          0
#define   SIO_SA_RX_STATUS_BUSY__W                                          1
#define   SIO_SA_RX_STATUS_BUSY__M                                          0x1
#define   SIO_SA_RX_STATUS_BUSY__PRE                                        0x0

#define   SIO_SA_RX_STATUS_BUFF_FULL__B                                     1
#define   SIO_SA_RX_STATUS_BUFF_FULL__W                                     1
#define   SIO_SA_RX_STATUS_BUFF_FULL__M                                     0x2
#define   SIO_SA_RX_STATUS_BUFF_FULL__PRE                                   0x0

#define SIO_PDR_COMM_EXEC__A                                                0x7F0000
#define SIO_PDR_COMM_EXEC__W                                                2
#define SIO_PDR_COMM_EXEC__M                                                0x3
#define SIO_PDR_COMM_EXEC__PRE                                              0x0
#define   SIO_PDR_COMM_EXEC_STOP                                            0x0
#define   SIO_PDR_COMM_EXEC_ACTIVE                                          0x1
#define   SIO_PDR_COMM_EXEC_HOLD                                            0x2

#define SIO_PDR_MON_CFG__A                                                  0x7F0010
#define SIO_PDR_MON_CFG__W                                                  2
#define SIO_PDR_MON_CFG__M                                                  0x3
#define SIO_PDR_MON_CFG__PRE                                                0x0

#define   SIO_PDR_MON_CFG_OSEL__B                                           0
#define   SIO_PDR_MON_CFG_OSEL__W                                           1
#define   SIO_PDR_MON_CFG_OSEL__M                                           0x1
#define   SIO_PDR_MON_CFG_OSEL__PRE                                         0x0

#define   SIO_PDR_MON_CFG_IACT__B                                           1
#define   SIO_PDR_MON_CFG_IACT__W                                           1
#define   SIO_PDR_MON_CFG_IACT__M                                           0x2
#define   SIO_PDR_MON_CFG_IACT__PRE                                         0x0

#define SIO_PDR_FDB_CFG__A                                                  0x7F0011
#define SIO_PDR_FDB_CFG__W                                                  2
#define SIO_PDR_FDB_CFG__M                                                  0x3
#define SIO_PDR_FDB_CFG__PRE                                                0x0
#define   SIO_PDR_FDB_CFG_SEL__B                                            0
#define   SIO_PDR_FDB_CFG_SEL__W                                            2
#define   SIO_PDR_FDB_CFG_SEL__M                                            0x3
#define   SIO_PDR_FDB_CFG_SEL__PRE                                          0x0

#define SIO_PDR_SMA_RX_SEL__A                                               0x7F0012
#define SIO_PDR_SMA_RX_SEL__W                                               4
#define SIO_PDR_SMA_RX_SEL__M                                               0xF
#define SIO_PDR_SMA_RX_SEL__PRE                                             0x0
#define   SIO_PDR_SMA_RX_SEL_SEL__B                                         0
#define   SIO_PDR_SMA_RX_SEL_SEL__W                                         4
#define   SIO_PDR_SMA_RX_SEL_SEL__M                                         0xF
#define   SIO_PDR_SMA_RX_SEL_SEL__PRE                                       0x0

#define SIO_PDR_SMA_TX_SILENT__A                                            0x7F0013
#define SIO_PDR_SMA_TX_SILENT__W                                            1
#define SIO_PDR_SMA_TX_SILENT__M                                            0x1
#define SIO_PDR_SMA_TX_SILENT__PRE                                          0x0
#define SIO_PDR_UIO_IN_LO__A                                                0x7F0014
#define SIO_PDR_UIO_IN_LO__W                                                16
#define SIO_PDR_UIO_IN_LO__M                                                0xFFFF
#define SIO_PDR_UIO_IN_LO__PRE                                              0x0
#define   SIO_PDR_UIO_IN_LO_DATA__B                                         0
#define   SIO_PDR_UIO_IN_LO_DATA__W                                         16
#define   SIO_PDR_UIO_IN_LO_DATA__M                                         0xFFFF
#define   SIO_PDR_UIO_IN_LO_DATA__PRE                                       0x0

#define SIO_PDR_UIO_IN_HI__A                                                0x7F0015
#define SIO_PDR_UIO_IN_HI__W                                                14
#define SIO_PDR_UIO_IN_HI__M                                                0x3FFF
#define SIO_PDR_UIO_IN_HI__PRE                                              0x0
#define   SIO_PDR_UIO_IN_HI_DATA__B                                         0
#define   SIO_PDR_UIO_IN_HI_DATA__W                                         14
#define   SIO_PDR_UIO_IN_HI_DATA__M                                         0x3FFF
#define   SIO_PDR_UIO_IN_HI_DATA__PRE                                       0x0

#define SIO_PDR_UIO_OUT_LO__A                                               0x7F0016
#define SIO_PDR_UIO_OUT_LO__W                                               16
#define SIO_PDR_UIO_OUT_LO__M                                               0xFFFF
#define SIO_PDR_UIO_OUT_LO__PRE                                             0x0
#define   SIO_PDR_UIO_OUT_LO_DATA__B                                        0
#define   SIO_PDR_UIO_OUT_LO_DATA__W                                        16
#define   SIO_PDR_UIO_OUT_LO_DATA__M                                        0xFFFF
#define   SIO_PDR_UIO_OUT_LO_DATA__PRE                                      0x0

#define SIO_PDR_UIO_OUT_HI__A                                               0x7F0017
#define SIO_PDR_UIO_OUT_HI__W                                               14
#define SIO_PDR_UIO_OUT_HI__M                                               0x3FFF
#define SIO_PDR_UIO_OUT_HI__PRE                                             0x0
#define   SIO_PDR_UIO_OUT_HI_DATA__B                                        0
#define   SIO_PDR_UIO_OUT_HI_DATA__W                                        14
#define   SIO_PDR_UIO_OUT_HI_DATA__M                                        0x3FFF
#define   SIO_PDR_UIO_OUT_HI_DATA__PRE                                      0x0

#define SIO_PDR_PWM1_MODE__A                                                0x7F0018
#define SIO_PDR_PWM1_MODE__W                                                2
#define SIO_PDR_PWM1_MODE__M                                                0x3
#define SIO_PDR_PWM1_MODE__PRE                                              0x0
#define SIO_PDR_PWM1_PRESCALE__A                                            0x7F0019
#define SIO_PDR_PWM1_PRESCALE__W                                            6
#define SIO_PDR_PWM1_PRESCALE__M                                            0x3F
#define SIO_PDR_PWM1_PRESCALE__PRE                                          0x0
#define SIO_PDR_PWM1_VALUE__A                                               0x7F001A
#define SIO_PDR_PWM1_VALUE__W                                               11
#define SIO_PDR_PWM1_VALUE__M                                               0x7FF
#define SIO_PDR_PWM1_VALUE__PRE                                             0x0
#define SIO_PDR_PWM2_MODE__A                                                0x7F001C
#define SIO_PDR_PWM2_MODE__W                                                2
#define SIO_PDR_PWM2_MODE__M                                                0x3
#define SIO_PDR_PWM2_MODE__PRE                                              0x0
#define SIO_PDR_PWM2_PRESCALE__A                                            0x7F001D
#define SIO_PDR_PWM2_PRESCALE__W                                            6
#define SIO_PDR_PWM2_PRESCALE__M                                            0x3F
#define SIO_PDR_PWM2_PRESCALE__PRE                                          0x0
#define SIO_PDR_PWM2_VALUE__A                                               0x7F001E
#define SIO_PDR_PWM2_VALUE__W                                               11
#define SIO_PDR_PWM2_VALUE__M                                               0x7FF
#define SIO_PDR_PWM2_VALUE__PRE                                             0x0
#define SIO_PDR_OHW_CFG__A                                                  0x7F001F
#define SIO_PDR_OHW_CFG__W                                                  7
#define SIO_PDR_OHW_CFG__M                                                  0x7F
#define SIO_PDR_OHW_CFG__PRE                                                0x0

#define   SIO_PDR_OHW_CFG_FREF_SEL__B                                       0
#define   SIO_PDR_OHW_CFG_FREF_SEL__W                                       2
#define   SIO_PDR_OHW_CFG_FREF_SEL__M                                       0x3
#define   SIO_PDR_OHW_CFG_FREF_SEL__PRE                                     0x0

#define   SIO_PDR_OHW_CFG_BYPASS__B                                         2
#define   SIO_PDR_OHW_CFG_BYPASS__W                                         1
#define   SIO_PDR_OHW_CFG_BYPASS__M                                         0x4
#define   SIO_PDR_OHW_CFG_BYPASS__PRE                                       0x0

#define   SIO_PDR_OHW_CFG_ASEL__B                                           3
#define   SIO_PDR_OHW_CFG_ASEL__W                                           3
#define   SIO_PDR_OHW_CFG_ASEL__M                                           0x38
#define   SIO_PDR_OHW_CFG_ASEL__PRE                                         0x0

#define   SIO_PDR_OHW_CFG_SPEED__B                                          6
#define   SIO_PDR_OHW_CFG_SPEED__W                                          1
#define   SIO_PDR_OHW_CFG_SPEED__M                                          0x40
#define   SIO_PDR_OHW_CFG_SPEED__PRE                                        0x0

#define SIO_PDR_I2S_WS_CFG__A                                               0x7F0020
#define SIO_PDR_I2S_WS_CFG__W                                               9
#define SIO_PDR_I2S_WS_CFG__M                                               0x1FF
#define SIO_PDR_I2S_WS_CFG__PRE                                             0x10
#define   SIO_PDR_I2S_WS_CFG_MODE__B                                        0
#define   SIO_PDR_I2S_WS_CFG_MODE__W                                        3
#define   SIO_PDR_I2S_WS_CFG_MODE__M                                        0x7
#define   SIO_PDR_I2S_WS_CFG_MODE__PRE                                      0x0
#define   SIO_PDR_I2S_WS_CFG_DRIVE__B                                       3
#define   SIO_PDR_I2S_WS_CFG_DRIVE__W                                       3
#define   SIO_PDR_I2S_WS_CFG_DRIVE__M                                       0x38
#define   SIO_PDR_I2S_WS_CFG_DRIVE__PRE                                     0x10
#define   SIO_PDR_I2S_WS_CFG_KEEP__B                                        6
#define   SIO_PDR_I2S_WS_CFG_KEEP__W                                        2
#define   SIO_PDR_I2S_WS_CFG_KEEP__M                                        0xC0
#define   SIO_PDR_I2S_WS_CFG_KEEP__PRE                                      0x0
#define   SIO_PDR_I2S_WS_CFG_UIO__B                                         8
#define   SIO_PDR_I2S_WS_CFG_UIO__W                                         1
#define   SIO_PDR_I2S_WS_CFG_UIO__M                                         0x100
#define   SIO_PDR_I2S_WS_CFG_UIO__PRE                                       0x0

#define SIO_PDR_GPIO_CFG__A                                                 0x7F0021
#define SIO_PDR_GPIO_CFG__W                                                 9
#define SIO_PDR_GPIO_CFG__M                                                 0x1FF
#define SIO_PDR_GPIO_CFG__PRE                                               0x10
#define   SIO_PDR_GPIO_CFG_MODE__B                                          0
#define   SIO_PDR_GPIO_CFG_MODE__W                                          3
#define   SIO_PDR_GPIO_CFG_MODE__M                                          0x7
#define   SIO_PDR_GPIO_CFG_MODE__PRE                                        0x0
#define   SIO_PDR_GPIO_CFG_DRIVE__B                                         3
#define   SIO_PDR_GPIO_CFG_DRIVE__W                                         3
#define   SIO_PDR_GPIO_CFG_DRIVE__M                                         0x38
#define   SIO_PDR_GPIO_CFG_DRIVE__PRE                                       0x10
#define   SIO_PDR_GPIO_CFG_KEEP__B                                          6
#define   SIO_PDR_GPIO_CFG_KEEP__W                                          2
#define   SIO_PDR_GPIO_CFG_KEEP__M                                          0xC0
#define   SIO_PDR_GPIO_CFG_KEEP__PRE                                        0x0
#define   SIO_PDR_GPIO_CFG_UIO__B                                           8
#define   SIO_PDR_GPIO_CFG_UIO__W                                           1
#define   SIO_PDR_GPIO_CFG_UIO__M                                           0x100
#define   SIO_PDR_GPIO_CFG_UIO__PRE                                         0x0

#define SIO_PDR_IRQN_CFG__A                                                 0x7F0022
#define SIO_PDR_IRQN_CFG__W                                                 9
#define SIO_PDR_IRQN_CFG__M                                                 0x1FF
#define SIO_PDR_IRQN_CFG__PRE                                               0x10
#define   SIO_PDR_IRQN_CFG_MODE__B                                          0
#define   SIO_PDR_IRQN_CFG_MODE__W                                          3
#define   SIO_PDR_IRQN_CFG_MODE__M                                          0x7
#define   SIO_PDR_IRQN_CFG_MODE__PRE                                        0x0
#define   SIO_PDR_IRQN_CFG_DRIVE__B                                         3
#define   SIO_PDR_IRQN_CFG_DRIVE__W                                         3
#define   SIO_PDR_IRQN_CFG_DRIVE__M                                         0x38
#define   SIO_PDR_IRQN_CFG_DRIVE__PRE                                       0x10
#define   SIO_PDR_IRQN_CFG_KEEP__B                                          6
#define   SIO_PDR_IRQN_CFG_KEEP__W                                          2
#define   SIO_PDR_IRQN_CFG_KEEP__M                                          0xC0
#define   SIO_PDR_IRQN_CFG_KEEP__PRE                                        0x0
#define   SIO_PDR_IRQN_CFG_UIO__B                                           8
#define   SIO_PDR_IRQN_CFG_UIO__W                                           1
#define   SIO_PDR_IRQN_CFG_UIO__M                                           0x100
#define   SIO_PDR_IRQN_CFG_UIO__PRE                                         0x0

#define SIO_PDR_OOB_CRX_CFG__A                                              0x7F0023
#define SIO_PDR_OOB_CRX_CFG__W                                              9
#define SIO_PDR_OOB_CRX_CFG__M                                              0x1FF
#define SIO_PDR_OOB_CRX_CFG__PRE                                            0x10
#define   SIO_PDR_OOB_CRX_CFG_MODE__B                                       0
#define   SIO_PDR_OOB_CRX_CFG_MODE__W                                       3
#define   SIO_PDR_OOB_CRX_CFG_MODE__M                                       0x7
#define   SIO_PDR_OOB_CRX_CFG_MODE__PRE                                     0x0
#define   SIO_PDR_OOB_CRX_CFG_DRIVE__B                                      3
#define   SIO_PDR_OOB_CRX_CFG_DRIVE__W                                      3
#define   SIO_PDR_OOB_CRX_CFG_DRIVE__M                                      0x38
#define   SIO_PDR_OOB_CRX_CFG_DRIVE__PRE                                    0x10
#define   SIO_PDR_OOB_CRX_CFG_KEEP__B                                       6
#define   SIO_PDR_OOB_CRX_CFG_KEEP__W                                       2
#define   SIO_PDR_OOB_CRX_CFG_KEEP__M                                       0xC0
#define   SIO_PDR_OOB_CRX_CFG_KEEP__PRE                                     0x0
#define   SIO_PDR_OOB_CRX_CFG_UIO__B                                        8
#define   SIO_PDR_OOB_CRX_CFG_UIO__W                                        1
#define   SIO_PDR_OOB_CRX_CFG_UIO__M                                        0x100
#define   SIO_PDR_OOB_CRX_CFG_UIO__PRE                                      0x0

#define SIO_PDR_OOB_DRX_CFG__A                                              0x7F0024
#define SIO_PDR_OOB_DRX_CFG__W                                              9
#define SIO_PDR_OOB_DRX_CFG__M                                              0x1FF
#define SIO_PDR_OOB_DRX_CFG__PRE                                            0x10
#define   SIO_PDR_OOB_DRX_CFG_MODE__B                                       0
#define   SIO_PDR_OOB_DRX_CFG_MODE__W                                       3
#define   SIO_PDR_OOB_DRX_CFG_MODE__M                                       0x7
#define   SIO_PDR_OOB_DRX_CFG_MODE__PRE                                     0x0
#define   SIO_PDR_OOB_DRX_CFG_DRIVE__B                                      3
#define   SIO_PDR_OOB_DRX_CFG_DRIVE__W                                      3
#define   SIO_PDR_OOB_DRX_CFG_DRIVE__M                                      0x38
#define   SIO_PDR_OOB_DRX_CFG_DRIVE__PRE                                    0x10
#define   SIO_PDR_OOB_DRX_CFG_KEEP__B                                       6
#define   SIO_PDR_OOB_DRX_CFG_KEEP__W                                       2
#define   SIO_PDR_OOB_DRX_CFG_KEEP__M                                       0xC0
#define   SIO_PDR_OOB_DRX_CFG_KEEP__PRE                                     0x0
#define   SIO_PDR_OOB_DRX_CFG_UIO__B                                        8
#define   SIO_PDR_OOB_DRX_CFG_UIO__W                                        1
#define   SIO_PDR_OOB_DRX_CFG_UIO__M                                        0x100
#define   SIO_PDR_OOB_DRX_CFG_UIO__PRE                                      0x0

#define SIO_PDR_MSTRT_CFG__A                                                0x7F0025
#define SIO_PDR_MSTRT_CFG__W                                                9
#define SIO_PDR_MSTRT_CFG__M                                                0x1FF
#define SIO_PDR_MSTRT_CFG__PRE                                              0x50
#define   SIO_PDR_MSTRT_CFG_MODE__B                                         0
#define   SIO_PDR_MSTRT_CFG_MODE__W                                         3
#define   SIO_PDR_MSTRT_CFG_MODE__M                                         0x7
#define   SIO_PDR_MSTRT_CFG_MODE__PRE                                       0x0
#define   SIO_PDR_MSTRT_CFG_DRIVE__B                                        3
#define   SIO_PDR_MSTRT_CFG_DRIVE__W                                        3
#define   SIO_PDR_MSTRT_CFG_DRIVE__M                                        0x38
#define   SIO_PDR_MSTRT_CFG_DRIVE__PRE                                      0x10
#define   SIO_PDR_MSTRT_CFG_KEEP__B                                         6
#define   SIO_PDR_MSTRT_CFG_KEEP__W                                         2
#define   SIO_PDR_MSTRT_CFG_KEEP__M                                         0xC0
#define   SIO_PDR_MSTRT_CFG_KEEP__PRE                                       0x40
#define   SIO_PDR_MSTRT_CFG_UIO__B                                          8
#define   SIO_PDR_MSTRT_CFG_UIO__W                                          1
#define   SIO_PDR_MSTRT_CFG_UIO__M                                          0x100
#define   SIO_PDR_MSTRT_CFG_UIO__PRE                                        0x0

#define SIO_PDR_MERR_CFG__A                                                 0x7F0026
#define SIO_PDR_MERR_CFG__W                                                 9
#define SIO_PDR_MERR_CFG__M                                                 0x1FF
#define SIO_PDR_MERR_CFG__PRE                                               0x50
#define   SIO_PDR_MERR_CFG_MODE__B                                          0
#define   SIO_PDR_MERR_CFG_MODE__W                                          3
#define   SIO_PDR_MERR_CFG_MODE__M                                          0x7
#define   SIO_PDR_MERR_CFG_MODE__PRE                                        0x0
#define   SIO_PDR_MERR_CFG_DRIVE__B                                         3
#define   SIO_PDR_MERR_CFG_DRIVE__W                                         3
#define   SIO_PDR_MERR_CFG_DRIVE__M                                         0x38
#define   SIO_PDR_MERR_CFG_DRIVE__PRE                                       0x10
#define   SIO_PDR_MERR_CFG_KEEP__B                                          6
#define   SIO_PDR_MERR_CFG_KEEP__W                                          2
#define   SIO_PDR_MERR_CFG_KEEP__M                                          0xC0
#define   SIO_PDR_MERR_CFG_KEEP__PRE                                        0x40
#define   SIO_PDR_MERR_CFG_UIO__B                                           8
#define   SIO_PDR_MERR_CFG_UIO__W                                           1
#define   SIO_PDR_MERR_CFG_UIO__M                                           0x100
#define   SIO_PDR_MERR_CFG_UIO__PRE                                         0x0

#define SIO_PDR_MCLK_CFG__A                                                 0x7F0028
#define SIO_PDR_MCLK_CFG__W                                                 9
#define SIO_PDR_MCLK_CFG__M                                                 0x1FF
#define SIO_PDR_MCLK_CFG__PRE                                               0x50
#define   SIO_PDR_MCLK_CFG_MODE__B                                          0
#define   SIO_PDR_MCLK_CFG_MODE__W                                          3
#define   SIO_PDR_MCLK_CFG_MODE__M                                          0x7
#define   SIO_PDR_MCLK_CFG_MODE__PRE                                        0x0
#define   SIO_PDR_MCLK_CFG_DRIVE__B                                         3
#define   SIO_PDR_MCLK_CFG_DRIVE__W                                         3
#define   SIO_PDR_MCLK_CFG_DRIVE__M                                         0x38
#define   SIO_PDR_MCLK_CFG_DRIVE__PRE                                       0x10
#define   SIO_PDR_MCLK_CFG_KEEP__B                                          6
#define   SIO_PDR_MCLK_CFG_KEEP__W                                          2
#define   SIO_PDR_MCLK_CFG_KEEP__M                                          0xC0
#define   SIO_PDR_MCLK_CFG_KEEP__PRE                                        0x40
#define   SIO_PDR_MCLK_CFG_UIO__B                                           8
#define   SIO_PDR_MCLK_CFG_UIO__W                                           1
#define   SIO_PDR_MCLK_CFG_UIO__M                                           0x100
#define   SIO_PDR_MCLK_CFG_UIO__PRE                                         0x0

#define SIO_PDR_MVAL_CFG__A                                                 0x7F0029
#define SIO_PDR_MVAL_CFG__W                                                 9
#define SIO_PDR_MVAL_CFG__M                                                 0x1FF
#define SIO_PDR_MVAL_CFG__PRE                                               0x50
#define   SIO_PDR_MVAL_CFG_MODE__B                                          0
#define   SIO_PDR_MVAL_CFG_MODE__W                                          3
#define   SIO_PDR_MVAL_CFG_MODE__M                                          0x7
#define   SIO_PDR_MVAL_CFG_MODE__PRE                                        0x0
#define   SIO_PDR_MVAL_CFG_DRIVE__B                                         3
#define   SIO_PDR_MVAL_CFG_DRIVE__W                                         3
#define   SIO_PDR_MVAL_CFG_DRIVE__M                                         0x38
#define   SIO_PDR_MVAL_CFG_DRIVE__PRE                                       0x10
#define   SIO_PDR_MVAL_CFG_KEEP__B                                          6
#define   SIO_PDR_MVAL_CFG_KEEP__W                                          2
#define   SIO_PDR_MVAL_CFG_KEEP__M                                          0xC0
#define   SIO_PDR_MVAL_CFG_KEEP__PRE                                        0x40
#define   SIO_PDR_MVAL_CFG_UIO__B                                           8
#define   SIO_PDR_MVAL_CFG_UIO__W                                           1
#define   SIO_PDR_MVAL_CFG_UIO__M                                           0x100
#define   SIO_PDR_MVAL_CFG_UIO__PRE                                         0x0

#define SIO_PDR_MD0_CFG__A                                                  0x7F002A
#define SIO_PDR_MD0_CFG__W                                                  9
#define SIO_PDR_MD0_CFG__M                                                  0x1FF
#define SIO_PDR_MD0_CFG__PRE                                                0x50
#define   SIO_PDR_MD0_CFG_MODE__B                                           0
#define   SIO_PDR_MD0_CFG_MODE__W                                           3
#define   SIO_PDR_MD0_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD0_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD0_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD0_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD0_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD0_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD0_CFG_KEEP__B                                           6
#define   SIO_PDR_MD0_CFG_KEEP__W                                           2
#define   SIO_PDR_MD0_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD0_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD0_CFG_UIO__B                                            8
#define   SIO_PDR_MD0_CFG_UIO__W                                            1
#define   SIO_PDR_MD0_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD0_CFG_UIO__PRE                                          0x0

#define SIO_PDR_MD1_CFG__A                                                  0x7F002B
#define SIO_PDR_MD1_CFG__W                                                  9
#define SIO_PDR_MD1_CFG__M                                                  0x1FF
#define SIO_PDR_MD1_CFG__PRE                                                0x50
#define   SIO_PDR_MD1_CFG_MODE__B                                           0
#define   SIO_PDR_MD1_CFG_MODE__W                                           3
#define   SIO_PDR_MD1_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD1_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD1_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD1_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD1_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD1_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD1_CFG_KEEP__B                                           6
#define   SIO_PDR_MD1_CFG_KEEP__W                                           2
#define   SIO_PDR_MD1_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD1_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD1_CFG_UIO__B                                            8
#define   SIO_PDR_MD1_CFG_UIO__W                                            1
#define   SIO_PDR_MD1_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD1_CFG_UIO__PRE                                          0x0

#define SIO_PDR_MD2_CFG__A                                                  0x7F002C
#define SIO_PDR_MD2_CFG__W                                                  9
#define SIO_PDR_MD2_CFG__M                                                  0x1FF
#define SIO_PDR_MD2_CFG__PRE                                                0x50
#define   SIO_PDR_MD2_CFG_MODE__B                                           0
#define   SIO_PDR_MD2_CFG_MODE__W                                           3
#define   SIO_PDR_MD2_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD2_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD2_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD2_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD2_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD2_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD2_CFG_KEEP__B                                           6
#define   SIO_PDR_MD2_CFG_KEEP__W                                           2
#define   SIO_PDR_MD2_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD2_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD2_CFG_UIO__B                                            8
#define   SIO_PDR_MD2_CFG_UIO__W                                            1
#define   SIO_PDR_MD2_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD2_CFG_UIO__PRE                                          0x0

#define SIO_PDR_MD3_CFG__A                                                  0x7F002D
#define SIO_PDR_MD3_CFG__W                                                  9
#define SIO_PDR_MD3_CFG__M                                                  0x1FF
#define SIO_PDR_MD3_CFG__PRE                                                0x50
#define   SIO_PDR_MD3_CFG_MODE__B                                           0
#define   SIO_PDR_MD3_CFG_MODE__W                                           3
#define   SIO_PDR_MD3_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD3_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD3_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD3_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD3_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD3_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD3_CFG_KEEP__B                                           6
#define   SIO_PDR_MD3_CFG_KEEP__W                                           2
#define   SIO_PDR_MD3_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD3_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD3_CFG_UIO__B                                            8
#define   SIO_PDR_MD3_CFG_UIO__W                                            1
#define   SIO_PDR_MD3_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD3_CFG_UIO__PRE                                          0x0

#define SIO_PDR_MD4_CFG__A                                                  0x7F002F
#define SIO_PDR_MD4_CFG__W                                                  9
#define SIO_PDR_MD4_CFG__M                                                  0x1FF
#define SIO_PDR_MD4_CFG__PRE                                                0x50
#define   SIO_PDR_MD4_CFG_MODE__B                                           0
#define   SIO_PDR_MD4_CFG_MODE__W                                           3
#define   SIO_PDR_MD4_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD4_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD4_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD4_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD4_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD4_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD4_CFG_KEEP__B                                           6
#define   SIO_PDR_MD4_CFG_KEEP__W                                           2
#define   SIO_PDR_MD4_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD4_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD4_CFG_UIO__B                                            8
#define   SIO_PDR_MD4_CFG_UIO__W                                            1
#define   SIO_PDR_MD4_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD4_CFG_UIO__PRE                                          0x0

#define SIO_PDR_MD5_CFG__A                                                  0x7F0030
#define SIO_PDR_MD5_CFG__W                                                  9
#define SIO_PDR_MD5_CFG__M                                                  0x1FF
#define SIO_PDR_MD5_CFG__PRE                                                0x50
#define   SIO_PDR_MD5_CFG_MODE__B                                           0
#define   SIO_PDR_MD5_CFG_MODE__W                                           3
#define   SIO_PDR_MD5_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD5_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD5_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD5_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD5_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD5_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD5_CFG_KEEP__B                                           6
#define   SIO_PDR_MD5_CFG_KEEP__W                                           2
#define   SIO_PDR_MD5_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD5_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD5_CFG_UIO__B                                            8
#define   SIO_PDR_MD5_CFG_UIO__W                                            1
#define   SIO_PDR_MD5_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD5_CFG_UIO__PRE                                          0x0

#define SIO_PDR_MD6_CFG__A                                                  0x7F0031
#define SIO_PDR_MD6_CFG__W                                                  9
#define SIO_PDR_MD6_CFG__M                                                  0x1FF
#define SIO_PDR_MD6_CFG__PRE                                                0x50
#define   SIO_PDR_MD6_CFG_MODE__B                                           0
#define   SIO_PDR_MD6_CFG_MODE__W                                           3
#define   SIO_PDR_MD6_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD6_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD6_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD6_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD6_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD6_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD6_CFG_KEEP__B                                           6
#define   SIO_PDR_MD6_CFG_KEEP__W                                           2
#define   SIO_PDR_MD6_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD6_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD6_CFG_UIO__B                                            8
#define   SIO_PDR_MD6_CFG_UIO__W                                            1
#define   SIO_PDR_MD6_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD6_CFG_UIO__PRE                                          0x0

#define SIO_PDR_MD7_CFG__A                                                  0x7F0032
#define SIO_PDR_MD7_CFG__W                                                  9
#define SIO_PDR_MD7_CFG__M                                                  0x1FF
#define SIO_PDR_MD7_CFG__PRE                                                0x50
#define   SIO_PDR_MD7_CFG_MODE__B                                           0
#define   SIO_PDR_MD7_CFG_MODE__W                                           3
#define   SIO_PDR_MD7_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD7_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD7_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD7_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD7_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD7_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD7_CFG_KEEP__B                                           6
#define   SIO_PDR_MD7_CFG_KEEP__W                                           2
#define   SIO_PDR_MD7_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD7_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD7_CFG_UIO__B                                            8
#define   SIO_PDR_MD7_CFG_UIO__W                                            1
#define   SIO_PDR_MD7_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD7_CFG_UIO__PRE                                          0x0

#define SIO_PDR_I2C_SCL1_CFG__A                                             0x7F0033
#define SIO_PDR_I2C_SCL1_CFG__W                                             9
#define SIO_PDR_I2C_SCL1_CFG__M                                             0x1FF
#define SIO_PDR_I2C_SCL1_CFG__PRE                                           0x11
#define   SIO_PDR_I2C_SCL1_CFG_MODE__B                                      0
#define   SIO_PDR_I2C_SCL1_CFG_MODE__W                                      3
#define   SIO_PDR_I2C_SCL1_CFG_MODE__M                                      0x7
#define   SIO_PDR_I2C_SCL1_CFG_MODE__PRE                                    0x1
#define   SIO_PDR_I2C_SCL1_CFG_DRIVE__B                                     3
#define   SIO_PDR_I2C_SCL1_CFG_DRIVE__W                                     3
#define   SIO_PDR_I2C_SCL1_CFG_DRIVE__M                                     0x38
#define   SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE                                   0x10
#define   SIO_PDR_I2C_SCL1_CFG_KEEP__B                                      6
#define   SIO_PDR_I2C_SCL1_CFG_KEEP__W                                      2
#define   SIO_PDR_I2C_SCL1_CFG_KEEP__M                                      0xC0
#define   SIO_PDR_I2C_SCL1_CFG_KEEP__PRE                                    0x0
#define   SIO_PDR_I2C_SCL1_CFG_UIO__B                                       8
#define   SIO_PDR_I2C_SCL1_CFG_UIO__W                                       1
#define   SIO_PDR_I2C_SCL1_CFG_UIO__M                                       0x100
#define   SIO_PDR_I2C_SCL1_CFG_UIO__PRE                                     0x0

#define SIO_PDR_I2C_SDA1_CFG__A                                             0x7F0034
#define SIO_PDR_I2C_SDA1_CFG__W                                             9
#define SIO_PDR_I2C_SDA1_CFG__M                                             0x1FF
#define SIO_PDR_I2C_SDA1_CFG__PRE                                           0x11
#define   SIO_PDR_I2C_SDA1_CFG_MODE__B                                      0
#define   SIO_PDR_I2C_SDA1_CFG_MODE__W                                      3
#define   SIO_PDR_I2C_SDA1_CFG_MODE__M                                      0x7
#define   SIO_PDR_I2C_SDA1_CFG_MODE__PRE                                    0x1
#define   SIO_PDR_I2C_SDA1_CFG_DRIVE__B                                     3
#define   SIO_PDR_I2C_SDA1_CFG_DRIVE__W                                     3
#define   SIO_PDR_I2C_SDA1_CFG_DRIVE__M                                     0x38
#define   SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE                                   0x10
#define   SIO_PDR_I2C_SDA1_CFG_KEEP__B                                      6
#define   SIO_PDR_I2C_SDA1_CFG_KEEP__W                                      2
#define   SIO_PDR_I2C_SDA1_CFG_KEEP__M                                      0xC0
#define   SIO_PDR_I2C_SDA1_CFG_KEEP__PRE                                    0x0
#define   SIO_PDR_I2C_SDA1_CFG_UIO__B                                       8
#define   SIO_PDR_I2C_SDA1_CFG_UIO__W                                       1
#define   SIO_PDR_I2C_SDA1_CFG_UIO__M                                       0x100
#define   SIO_PDR_I2C_SDA1_CFG_UIO__PRE                                     0x0

#define SIO_PDR_VSYNC_CFG__A                                                0x7F0036
#define SIO_PDR_VSYNC_CFG__W                                                9
#define SIO_PDR_VSYNC_CFG__M                                                0x1FF
#define SIO_PDR_VSYNC_CFG__PRE                                              0x10
#define   SIO_PDR_VSYNC_CFG_MODE__B                                         0
#define   SIO_PDR_VSYNC_CFG_MODE__W                                         3
#define   SIO_PDR_VSYNC_CFG_MODE__M                                         0x7
#define   SIO_PDR_VSYNC_CFG_MODE__PRE                                       0x0
#define   SIO_PDR_VSYNC_CFG_DRIVE__B                                        3
#define   SIO_PDR_VSYNC_CFG_DRIVE__W                                        3
#define   SIO_PDR_VSYNC_CFG_DRIVE__M                                        0x38
#define   SIO_PDR_VSYNC_CFG_DRIVE__PRE                                      0x10
#define   SIO_PDR_VSYNC_CFG_KEEP__B                                         6
#define   SIO_PDR_VSYNC_CFG_KEEP__W                                         2
#define   SIO_PDR_VSYNC_CFG_KEEP__M                                         0xC0
#define   SIO_PDR_VSYNC_CFG_KEEP__PRE                                       0x0
#define   SIO_PDR_VSYNC_CFG_UIO__B                                          8
#define   SIO_PDR_VSYNC_CFG_UIO__W                                          1
#define   SIO_PDR_VSYNC_CFG_UIO__M                                          0x100
#define   SIO_PDR_VSYNC_CFG_UIO__PRE                                        0x0

#define SIO_PDR_SMA_RX_CFG__A                                               0x7F0037
#define SIO_PDR_SMA_RX_CFG__W                                               9
#define SIO_PDR_SMA_RX_CFG__M                                               0x1FF
#define SIO_PDR_SMA_RX_CFG__PRE                                             0x10
#define   SIO_PDR_SMA_RX_CFG_MODE__B                                        0
#define   SIO_PDR_SMA_RX_CFG_MODE__W                                        3
#define   SIO_PDR_SMA_RX_CFG_MODE__M                                        0x7
#define   SIO_PDR_SMA_RX_CFG_MODE__PRE                                      0x0
#define   SIO_PDR_SMA_RX_CFG_DRIVE__B                                       3
#define   SIO_PDR_SMA_RX_CFG_DRIVE__W                                       3
#define   SIO_PDR_SMA_RX_CFG_DRIVE__M                                       0x38
#define   SIO_PDR_SMA_RX_CFG_DRIVE__PRE                                     0x10
#define   SIO_PDR_SMA_RX_CFG_KEEP__B                                        6
#define   SIO_PDR_SMA_RX_CFG_KEEP__W                                        2
#define   SIO_PDR_SMA_RX_CFG_KEEP__M                                        0xC0
#define   SIO_PDR_SMA_RX_CFG_KEEP__PRE                                      0x0
#define   SIO_PDR_SMA_RX_CFG_UIO__B                                         8
#define   SIO_PDR_SMA_RX_CFG_UIO__W                                         1
#define   SIO_PDR_SMA_RX_CFG_UIO__M                                         0x100
#define   SIO_PDR_SMA_RX_CFG_UIO__PRE                                       0x0

#define SIO_PDR_SMA_TX_CFG__A                                               0x7F0038
#define SIO_PDR_SMA_TX_CFG__W                                               9
#define SIO_PDR_SMA_TX_CFG__M                                               0x1FF
#define SIO_PDR_SMA_TX_CFG__PRE                                             0x90
#define   SIO_PDR_SMA_TX_CFG_MODE__B                                        0
#define   SIO_PDR_SMA_TX_CFG_MODE__W                                        3
#define   SIO_PDR_SMA_TX_CFG_MODE__M                                        0x7
#define   SIO_PDR_SMA_TX_CFG_MODE__PRE                                      0x0
#define   SIO_PDR_SMA_TX_CFG_DRIVE__B                                       3
#define   SIO_PDR_SMA_TX_CFG_DRIVE__W                                       3
#define   SIO_PDR_SMA_TX_CFG_DRIVE__M                                       0x38
#define   SIO_PDR_SMA_TX_CFG_DRIVE__PRE                                     0x10
#define   SIO_PDR_SMA_TX_CFG_KEEP__B                                        6
#define   SIO_PDR_SMA_TX_CFG_KEEP__W                                        2
#define   SIO_PDR_SMA_TX_CFG_KEEP__M                                        0xC0
#define   SIO_PDR_SMA_TX_CFG_KEEP__PRE                                      0x80
#define   SIO_PDR_SMA_TX_CFG_UIO__B                                         8
#define   SIO_PDR_SMA_TX_CFG_UIO__W                                         1
#define   SIO_PDR_SMA_TX_CFG_UIO__M                                         0x100
#define   SIO_PDR_SMA_TX_CFG_UIO__PRE                                       0x0

#define SIO_PDR_I2C_SDA2_CFG__A                                             0x7F003F
#define SIO_PDR_I2C_SDA2_CFG__W                                             9
#define SIO_PDR_I2C_SDA2_CFG__M                                             0x1FF
#define SIO_PDR_I2C_SDA2_CFG__PRE                                           0x11
#define   SIO_PDR_I2C_SDA2_CFG_MODE__B                                      0
#define   SIO_PDR_I2C_SDA2_CFG_MODE__W                                      3
#define   SIO_PDR_I2C_SDA2_CFG_MODE__M                                      0x7
#define   SIO_PDR_I2C_SDA2_CFG_MODE__PRE                                    0x1
#define   SIO_PDR_I2C_SDA2_CFG_DRIVE__B                                     3
#define   SIO_PDR_I2C_SDA2_CFG_DRIVE__W                                     3
#define   SIO_PDR_I2C_SDA2_CFG_DRIVE__M                                     0x38
#define   SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE                                   0x10
#define   SIO_PDR_I2C_SDA2_CFG_KEEP__B                                      6
#define   SIO_PDR_I2C_SDA2_CFG_KEEP__W                                      2
#define   SIO_PDR_I2C_SDA2_CFG_KEEP__M                                      0xC0
#define   SIO_PDR_I2C_SDA2_CFG_KEEP__PRE                                    0x0
#define   SIO_PDR_I2C_SDA2_CFG_UIO__B                                       8
#define   SIO_PDR_I2C_SDA2_CFG_UIO__W                                       1
#define   SIO_PDR_I2C_SDA2_CFG_UIO__M                                       0x100
#define   SIO_PDR_I2C_SDA2_CFG_UIO__PRE                                     0x0

#define SIO_PDR_I2C_SCL2_CFG__A                                             0x7F0040
#define SIO_PDR_I2C_SCL2_CFG__W                                             9
#define SIO_PDR_I2C_SCL2_CFG__M                                             0x1FF
#define SIO_PDR_I2C_SCL2_CFG__PRE                                           0x11
#define   SIO_PDR_I2C_SCL2_CFG_MODE__B                                      0
#define   SIO_PDR_I2C_SCL2_CFG_MODE__W                                      3
#define   SIO_PDR_I2C_SCL2_CFG_MODE__M                                      0x7
#define   SIO_PDR_I2C_SCL2_CFG_MODE__PRE                                    0x1
#define   SIO_PDR_I2C_SCL2_CFG_DRIVE__B                                     3
#define   SIO_PDR_I2C_SCL2_CFG_DRIVE__W                                     3
#define   SIO_PDR_I2C_SCL2_CFG_DRIVE__M                                     0x38
#define   SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE                                   0x10
#define   SIO_PDR_I2C_SCL2_CFG_KEEP__B                                      6
#define   SIO_PDR_I2C_SCL2_CFG_KEEP__W                                      2
#define   SIO_PDR_I2C_SCL2_CFG_KEEP__M                                      0xC0
#define   SIO_PDR_I2C_SCL2_CFG_KEEP__PRE                                    0x0
#define   SIO_PDR_I2C_SCL2_CFG_UIO__B                                       8
#define   SIO_PDR_I2C_SCL2_CFG_UIO__W                                       1
#define   SIO_PDR_I2C_SCL2_CFG_UIO__M                                       0x100
#define   SIO_PDR_I2C_SCL2_CFG_UIO__PRE                                     0x0

#define SIO_PDR_I2S_CL_CFG__A                                               0x7F0041
#define SIO_PDR_I2S_CL_CFG__W                                               9
#define SIO_PDR_I2S_CL_CFG__M                                               0x1FF
#define SIO_PDR_I2S_CL_CFG__PRE                                             0x10
#define   SIO_PDR_I2S_CL_CFG_MODE__B                                        0
#define   SIO_PDR_I2S_CL_CFG_MODE__W                                        3
#define   SIO_PDR_I2S_CL_CFG_MODE__M                                        0x7
#define   SIO_PDR_I2S_CL_CFG_MODE__PRE                                      0x0
#define   SIO_PDR_I2S_CL_CFG_DRIVE__B                                       3
#define   SIO_PDR_I2S_CL_CFG_DRIVE__W                                       3
#define   SIO_PDR_I2S_CL_CFG_DRIVE__M                                       0x38
#define   SIO_PDR_I2S_CL_CFG_DRIVE__PRE                                     0x10
#define   SIO_PDR_I2S_CL_CFG_KEEP__B                                        6
#define   SIO_PDR_I2S_CL_CFG_KEEP__W                                        2
#define   SIO_PDR_I2S_CL_CFG_KEEP__M                                        0xC0
#define   SIO_PDR_I2S_CL_CFG_KEEP__PRE                                      0x0
#define   SIO_PDR_I2S_CL_CFG_UIO__B                                         8
#define   SIO_PDR_I2S_CL_CFG_UIO__W                                         1
#define   SIO_PDR_I2S_CL_CFG_UIO__M                                         0x100
#define   SIO_PDR_I2S_CL_CFG_UIO__PRE                                       0x0

#define SIO_PDR_I2S_DA_CFG__A                                               0x7F0042
#define SIO_PDR_I2S_DA_CFG__W                                               9
#define SIO_PDR_I2S_DA_CFG__M                                               0x1FF
#define SIO_PDR_I2S_DA_CFG__PRE                                             0x10
#define   SIO_PDR_I2S_DA_CFG_MODE__B                                        0
#define   SIO_PDR_I2S_DA_CFG_MODE__W                                        3
#define   SIO_PDR_I2S_DA_CFG_MODE__M                                        0x7
#define   SIO_PDR_I2S_DA_CFG_MODE__PRE                                      0x0
#define   SIO_PDR_I2S_DA_CFG_DRIVE__B                                       3
#define   SIO_PDR_I2S_DA_CFG_DRIVE__W                                       3
#define   SIO_PDR_I2S_DA_CFG_DRIVE__M                                       0x38
#define   SIO_PDR_I2S_DA_CFG_DRIVE__PRE                                     0x10
#define   SIO_PDR_I2S_DA_CFG_KEEP__B                                        6
#define   SIO_PDR_I2S_DA_CFG_KEEP__W                                        2
#define   SIO_PDR_I2S_DA_CFG_KEEP__M                                        0xC0
#define   SIO_PDR_I2S_DA_CFG_KEEP__PRE                                      0x0
#define   SIO_PDR_I2S_DA_CFG_UIO__B                                         8
#define   SIO_PDR_I2S_DA_CFG_UIO__W                                         1
#define   SIO_PDR_I2S_DA_CFG_UIO__M                                         0x100
#define   SIO_PDR_I2S_DA_CFG_UIO__PRE                                       0x0

#define SIO_PDR_GPIO_GPIO_FNC__A                                            0x7F0050
#define SIO_PDR_GPIO_GPIO_FNC__W                                            2
#define SIO_PDR_GPIO_GPIO_FNC__M                                            0x3
#define SIO_PDR_GPIO_GPIO_FNC__PRE                                          0x0
#define   SIO_PDR_GPIO_GPIO_FNC_SEL__B                                      0
#define   SIO_PDR_GPIO_GPIO_FNC_SEL__W                                      2
#define   SIO_PDR_GPIO_GPIO_FNC_SEL__M                                      0x3
#define   SIO_PDR_GPIO_GPIO_FNC_SEL__PRE                                    0x0

#define SIO_PDR_IRQN_GPIO_FNC__A                                            0x7F0051
#define SIO_PDR_IRQN_GPIO_FNC__W                                            2
#define SIO_PDR_IRQN_GPIO_FNC__M                                            0x3
#define SIO_PDR_IRQN_GPIO_FNC__PRE                                          0x0
#define   SIO_PDR_IRQN_GPIO_FNC_SEL__B                                      0
#define   SIO_PDR_IRQN_GPIO_FNC_SEL__W                                      2
#define   SIO_PDR_IRQN_GPIO_FNC_SEL__M                                      0x3
#define   SIO_PDR_IRQN_GPIO_FNC_SEL__PRE                                    0x0

#define SIO_PDR_MSTRT_GPIO_FNC__A                                           0x7F0052
#define SIO_PDR_MSTRT_GPIO_FNC__W                                           2
#define SIO_PDR_MSTRT_GPIO_FNC__M                                           0x3
#define SIO_PDR_MSTRT_GPIO_FNC__PRE                                         0x0
#define   SIO_PDR_MSTRT_GPIO_FNC_SEL__B                                     0
#define   SIO_PDR_MSTRT_GPIO_FNC_SEL__W                                     2
#define   SIO_PDR_MSTRT_GPIO_FNC_SEL__M                                     0x3
#define   SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE                                   0x0

#define SIO_PDR_MERR_GPIO_FNC__A                                            0x7F0053
#define SIO_PDR_MERR_GPIO_FNC__W                                            2
#define SIO_PDR_MERR_GPIO_FNC__M                                            0x3
#define SIO_PDR_MERR_GPIO_FNC__PRE                                          0x0
#define   SIO_PDR_MERR_GPIO_FNC_SEL__B                                      0
#define   SIO_PDR_MERR_GPIO_FNC_SEL__W                                      2
#define   SIO_PDR_MERR_GPIO_FNC_SEL__M                                      0x3
#define   SIO_PDR_MERR_GPIO_FNC_SEL__PRE                                    0x0

#define SIO_PDR_MCLK_GPIO_FNC__A                                            0x7F0054
#define SIO_PDR_MCLK_GPIO_FNC__W                                            2
#define SIO_PDR_MCLK_GPIO_FNC__M                                            0x3
#define SIO_PDR_MCLK_GPIO_FNC__PRE                                          0x0
#define   SIO_PDR_MCLK_GPIO_FNC_SEL__B                                      0
#define   SIO_PDR_MCLK_GPIO_FNC_SEL__W                                      2
#define   SIO_PDR_MCLK_GPIO_FNC_SEL__M                                      0x3
#define   SIO_PDR_MCLK_GPIO_FNC_SEL__PRE                                    0x0

#define SIO_PDR_MVAL_GPIO_FNC__A                                            0x7F0055
#define SIO_PDR_MVAL_GPIO_FNC__W                                            2
#define SIO_PDR_MVAL_GPIO_FNC__M                                            0x3
#define SIO_PDR_MVAL_GPIO_FNC__PRE                                          0x0
#define   SIO_PDR_MVAL_GPIO_FNC_SEL__B                                      0
#define   SIO_PDR_MVAL_GPIO_FNC_SEL__W                                      2
#define   SIO_PDR_MVAL_GPIO_FNC_SEL__M                                      0x3
#define   SIO_PDR_MVAL_GPIO_FNC_SEL__PRE                                    0x0

#define SIO_PDR_MD0_GPIO_FNC__A                                             0x7F0056
#define SIO_PDR_MD0_GPIO_FNC__W                                             2
#define SIO_PDR_MD0_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD0_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD0_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD0_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD0_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD0_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_MD1_GPIO_FNC__A                                             0x7F0057
#define SIO_PDR_MD1_GPIO_FNC__W                                             2
#define SIO_PDR_MD1_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD1_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD1_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD1_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD1_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD1_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_MD2_GPIO_FNC__A                                             0x7F0058
#define SIO_PDR_MD2_GPIO_FNC__W                                             2
#define SIO_PDR_MD2_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD2_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD2_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD2_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD2_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD2_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_MD3_GPIO_FNC__A                                             0x7F0059
#define SIO_PDR_MD3_GPIO_FNC__W                                             2
#define SIO_PDR_MD3_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD3_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD3_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD3_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD3_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD3_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_MD4_GPIO_FNC__A                                             0x7F005A
#define SIO_PDR_MD4_GPIO_FNC__W                                             2
#define SIO_PDR_MD4_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD4_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD4_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD4_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD4_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD4_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_MD5_GPIO_FNC__A                                             0x7F005B
#define SIO_PDR_MD5_GPIO_FNC__W                                             2
#define SIO_PDR_MD5_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD5_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD5_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD5_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD5_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD5_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_MD6_GPIO_FNC__A                                             0x7F005C
#define SIO_PDR_MD6_GPIO_FNC__W                                             2
#define SIO_PDR_MD6_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD6_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD6_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD6_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD6_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD6_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_MD7_GPIO_FNC__A                                             0x7F005D
#define SIO_PDR_MD7_GPIO_FNC__W                                             2
#define SIO_PDR_MD7_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD7_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD7_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD7_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD7_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD7_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_SMA_RX_GPIO_FNC__A                                          0x7F005E
#define SIO_PDR_SMA_RX_GPIO_FNC__W                                          2
#define SIO_PDR_SMA_RX_GPIO_FNC__M                                          0x3
#define SIO_PDR_SMA_RX_GPIO_FNC__PRE                                        0x0
#define   SIO_PDR_SMA_RX_GPIO_FNC_SEL__B                                    0
#define   SIO_PDR_SMA_RX_GPIO_FNC_SEL__W                                    2
#define   SIO_PDR_SMA_RX_GPIO_FNC_SEL__M                                    0x3
#define   SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE                                  0x0

#define SIO_PDR_SMA_TX_GPIO_FNC__A                                          0x7F005F
#define SIO_PDR_SMA_TX_GPIO_FNC__W                                          2
#define SIO_PDR_SMA_TX_GPIO_FNC__M                                          0x3
#define SIO_PDR_SMA_TX_GPIO_FNC__PRE                                        0x0
#define   SIO_PDR_SMA_TX_GPIO_FNC_SEL__B                                    0
#define   SIO_PDR_SMA_TX_GPIO_FNC_SEL__W                                    2
#define   SIO_PDR_SMA_TX_GPIO_FNC_SEL__M                                    0x3
#define   SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE                                  0x0

#define VSB_COMM_EXEC__A                                                    0x1C00000
#define VSB_COMM_EXEC__W                                                    2
#define VSB_COMM_EXEC__M                                                    0x3
#define VSB_COMM_EXEC__PRE                                                  0x0
#define   VSB_COMM_EXEC_STOP                                                0x0
#define   VSB_COMM_EXEC_ACTIVE                                              0x1
#define   VSB_COMM_EXEC_HOLD                                                0x2

#define VSB_COMM_MB__A                                                      0x1C00002
#define VSB_COMM_MB__W                                                      16
#define VSB_COMM_MB__M                                                      0xFFFF
#define VSB_COMM_MB__PRE                                                    0x0
#define VSB_COMM_INT_REQ__A                                                 0x1C00003
#define VSB_COMM_INT_REQ__W                                                 1
#define VSB_COMM_INT_REQ__M                                                 0x1
#define VSB_COMM_INT_REQ__PRE                                               0x0

#define   VSB_COMM_INT_REQ_TOP_INT_REQ__B                                   0
#define   VSB_COMM_INT_REQ_TOP_INT_REQ__W                                   1
#define   VSB_COMM_INT_REQ_TOP_INT_REQ__M                                   0x1
#define   VSB_COMM_INT_REQ_TOP_INT_REQ__PRE                                 0x0

#define VSB_COMM_INT_STA__A                                                 0x1C00005
#define VSB_COMM_INT_STA__W                                                 16
#define VSB_COMM_INT_STA__M                                                 0xFFFF
#define VSB_COMM_INT_STA__PRE                                               0x0

#define VSB_COMM_INT_MSK__A                                                 0x1C00006
#define VSB_COMM_INT_MSK__W                                                 16
#define VSB_COMM_INT_MSK__M                                                 0xFFFF
#define VSB_COMM_INT_MSK__PRE                                               0x0

#define VSB_COMM_INT_STM__A                                                 0x1C00007
#define VSB_COMM_INT_STM__W                                                 16
#define VSB_COMM_INT_STM__M                                                 0xFFFF
#define VSB_COMM_INT_STM__PRE                                               0x0

#define VSB_TOP_COMM_EXEC__A                                                0x1C10000
#define VSB_TOP_COMM_EXEC__W                                                2
#define VSB_TOP_COMM_EXEC__M                                                0x3
#define VSB_TOP_COMM_EXEC__PRE                                              0x0
#define   VSB_TOP_COMM_EXEC_STOP                                            0x0
#define   VSB_TOP_COMM_EXEC_ACTIVE                                          0x1
#define   VSB_TOP_COMM_EXEC_HOLD                                            0x2

#define VSB_TOP_COMM_MB__A                                                  0x1C10002
#define VSB_TOP_COMM_MB__W                                                  10
#define VSB_TOP_COMM_MB__M                                                  0x3FF
#define VSB_TOP_COMM_MB__PRE                                                0x0

#define   VSB_TOP_COMM_MB_CTL__B                                            0
#define   VSB_TOP_COMM_MB_CTL__W                                            1
#define   VSB_TOP_COMM_MB_CTL__M                                            0x1
#define   VSB_TOP_COMM_MB_CTL__PRE                                          0x0
#define     VSB_TOP_COMM_MB_CTL_CTL_OFF                                     0x0
#define     VSB_TOP_COMM_MB_CTL_CTL_ON                                      0x1

#define   VSB_TOP_COMM_MB_OBS__B                                            1
#define   VSB_TOP_COMM_MB_OBS__W                                            1
#define   VSB_TOP_COMM_MB_OBS__M                                            0x2
#define   VSB_TOP_COMM_MB_OBS__PRE                                          0x0
#define     VSB_TOP_COMM_MB_OBS_OBS_OFF                                     0x0
#define     VSB_TOP_COMM_MB_OBS_OBS_ON                                      0x2

#define   VSB_TOP_COMM_MB_MUX_CTL__B                                        2
#define   VSB_TOP_COMM_MB_MUX_CTL__W                                        4
#define   VSB_TOP_COMM_MB_MUX_CTL__M                                        0x3C
#define   VSB_TOP_COMM_MB_MUX_CTL__PRE                                      0x0

#define   VSB_TOP_COMM_MB_MUX_OBS__B                                        6
#define   VSB_TOP_COMM_MB_MUX_OBS__W                                        4
#define   VSB_TOP_COMM_MB_MUX_OBS__M                                        0x3C0
#define   VSB_TOP_COMM_MB_MUX_OBS__PRE                                      0x0
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_FEC                                 0x0
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM                                 0x40
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM_AMPLITUDE                       0x80
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_1                             0xC0
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2                             0x100
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_1                               0x140
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_2                               0x180
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_1                               0x1C0
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_2                               0x200

#define VSB_TOP_COMM_INT_REQ__A                                             0x1C10003
#define VSB_TOP_COMM_INT_REQ__W                                             1
#define VSB_TOP_COMM_INT_REQ__M                                             0x1
#define VSB_TOP_COMM_INT_REQ__PRE                                           0x0
#define VSB_TOP_COMM_INT_STA__A                                             0x1C10005
#define VSB_TOP_COMM_INT_STA__W                                             6
#define VSB_TOP_COMM_INT_STA__M                                             0x3F
#define VSB_TOP_COMM_INT_STA__PRE                                           0x0

#define   VSB_TOP_COMM_INT_STA_FIELD_INT_STA__B                             0
#define   VSB_TOP_COMM_INT_STA_FIELD_INT_STA__W                             1
#define   VSB_TOP_COMM_INT_STA_FIELD_INT_STA__M                             0x1
#define   VSB_TOP_COMM_INT_STA_FIELD_INT_STA__PRE                           0x0

#define   VSB_TOP_COMM_INT_STA_LOCK_STA__B                                  1
#define   VSB_TOP_COMM_INT_STA_LOCK_STA__W                                  1
#define   VSB_TOP_COMM_INT_STA_LOCK_STA__M                                  0x2
#define   VSB_TOP_COMM_INT_STA_LOCK_STA__PRE                                0x0

#define   VSB_TOP_COMM_INT_STA_UNLOCK_STA__B                                2
#define   VSB_TOP_COMM_INT_STA_UNLOCK_STA__W                                1
#define   VSB_TOP_COMM_INT_STA_UNLOCK_STA__M                                0x4
#define   VSB_TOP_COMM_INT_STA_UNLOCK_STA__PRE                              0x0

#define   VSB_TOP_COMM_INT_STA_TAPREADER_STA__B                             3
#define   VSB_TOP_COMM_INT_STA_TAPREADER_STA__W                             1
#define   VSB_TOP_COMM_INT_STA_TAPREADER_STA__M                             0x8
#define   VSB_TOP_COMM_INT_STA_TAPREADER_STA__PRE                           0x0

#define   VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__B                           4
#define   VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__W                           1
#define   VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__M                           0x10
#define   VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__PRE                         0x0

#define   VSB_TOP_COMM_INT_STA_MERSER_STA__B                                5
#define   VSB_TOP_COMM_INT_STA_MERSER_STA__W                                1
#define   VSB_TOP_COMM_INT_STA_MERSER_STA__M                                0x20
#define   VSB_TOP_COMM_INT_STA_MERSER_STA__PRE                              0x0

#define VSB_TOP_COMM_INT_MSK__A                                             0x1C10006
#define VSB_TOP_COMM_INT_MSK__W                                             6
#define VSB_TOP_COMM_INT_MSK__M                                             0x3F
#define VSB_TOP_COMM_INT_MSK__PRE                                           0x0

#define   VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__B                             0
#define   VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__W                             1
#define   VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__M                             0x1
#define   VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__PRE                           0x0

#define   VSB_TOP_COMM_INT_MSK_LOCK_MSK__B                                  1
#define   VSB_TOP_COMM_INT_MSK_LOCK_MSK__W                                  1
#define   VSB_TOP_COMM_INT_MSK_LOCK_MSK__M                                  0x2
#define   VSB_TOP_COMM_INT_MSK_LOCK_MSK__PRE                                0x0

#define   VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__B                                2
#define   VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__W                                1
#define   VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__M                                0x4
#define   VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__PRE                              0x0

#define   VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__B                             3
#define   VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__W                             1
#define   VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__M                             0x8
#define   VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__PRE                           0x0

#define   VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__B                           4
#define   VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__W                           1
#define   VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__M                           0x10
#define   VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__PRE                         0x0

#define   VSB_TOP_COMM_INT_MSK_MERSER_MSK__B                                5
#define   VSB_TOP_COMM_INT_MSK_MERSER_MSK__W                                1
#define   VSB_TOP_COMM_INT_MSK_MERSER_MSK__M                                0x20
#define   VSB_TOP_COMM_INT_MSK_MERSER_MSK__PRE                              0x0

#define VSB_TOP_COMM_INT_STM__A                                             0x1C10007
#define VSB_TOP_COMM_INT_STM__W                                             6
#define VSB_TOP_COMM_INT_STM__M                                             0x3F
#define VSB_TOP_COMM_INT_STM__PRE                                           0x0

#define   VSB_TOP_COMM_INT_STM_FIELD_INT_STM__B                             0
#define   VSB_TOP_COMM_INT_STM_FIELD_INT_STM__W                             1
#define   VSB_TOP_COMM_INT_STM_FIELD_INT_STM__M                             0x1
#define   VSB_TOP_COMM_INT_STM_FIELD_INT_STM__PRE                           0x0

#define   VSB_TOP_COMM_INT_STM_LOCK_STM__B                                  1
#define   VSB_TOP_COMM_INT_STM_LOCK_STM__W                                  1
#define   VSB_TOP_COMM_INT_STM_LOCK_STM__M                                  0x2
#define   VSB_TOP_COMM_INT_STM_LOCK_STM__PRE                                0x0

#define   VSB_TOP_COMM_INT_STM_UNLOCK_STM__B                                2
#define   VSB_TOP_COMM_INT_STM_UNLOCK_STM__W                                1
#define   VSB_TOP_COMM_INT_STM_UNLOCK_STM__M                                0x4
#define   VSB_TOP_COMM_INT_STM_UNLOCK_STM__PRE                              0x0

#define   VSB_TOP_COMM_INT_STM_TAPREADER_STM__B                             3
#define   VSB_TOP_COMM_INT_STM_TAPREADER_STM__W                             1
#define   VSB_TOP_COMM_INT_STM_TAPREADER_STM__M                             0x8
#define   VSB_TOP_COMM_INT_STM_TAPREADER_STM__PRE                           0x0

#define   VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__B                           4
#define   VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__W                           1
#define   VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__M                           0x10
#define   VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__PRE                         0x0

#define   VSB_TOP_COMM_INT_STM_MERSER_STM__B                                5
#define   VSB_TOP_COMM_INT_STM_MERSER_STM__W                                1
#define   VSB_TOP_COMM_INT_STM_MERSER_STM__M                                0x20
#define   VSB_TOP_COMM_INT_STM_MERSER_STM__PRE                              0x0

#define VSB_TOP_CKGN1ACQ__A                                                 0x1C10010
#define VSB_TOP_CKGN1ACQ__W                                                 8
#define VSB_TOP_CKGN1ACQ__M                                                 0xFF
#define VSB_TOP_CKGN1ACQ__PRE                                               0x4

#define VSB_TOP_CKGN1TRK__A                                                 0x1C10011
#define VSB_TOP_CKGN1TRK__W                                                 8
#define VSB_TOP_CKGN1TRK__M                                                 0xFF
#define VSB_TOP_CKGN1TRK__PRE                                               0x0

#define VSB_TOP_CKGN2ACQ__A                                                 0x1C10012
#define VSB_TOP_CKGN2ACQ__W                                                 8
#define VSB_TOP_CKGN2ACQ__M                                                 0xFF
#define VSB_TOP_CKGN2ACQ__PRE                                               0x2

#define VSB_TOP_CKGN2TRK__A                                                 0x1C10013
#define VSB_TOP_CKGN2TRK__W                                                 8
#define VSB_TOP_CKGN2TRK__M                                                 0xFF
#define VSB_TOP_CKGN2TRK__PRE                                               0x1

#define VSB_TOP_CKGN3__A                                                    0x1C10014
#define VSB_TOP_CKGN3__W                                                    8
#define VSB_TOP_CKGN3__M                                                    0xFF
#define VSB_TOP_CKGN3__PRE                                                  0x5

#define VSB_TOP_CYGN1ACQ__A                                                 0x1C10015
#define VSB_TOP_CYGN1ACQ__W                                                 8
#define VSB_TOP_CYGN1ACQ__M                                                 0xFF
#define VSB_TOP_CYGN1ACQ__PRE                                               0x3

#define VSB_TOP_CYGN1TRK__A                                                 0x1C10016
#define VSB_TOP_CYGN1TRK__W                                                 8
#define VSB_TOP_CYGN1TRK__M                                                 0xFF
#define VSB_TOP_CYGN1TRK__PRE                                               0x0

#define VSB_TOP_CYGN2ACQ__A                                                 0x1C10017
#define VSB_TOP_CYGN2ACQ__W                                                 8
#define VSB_TOP_CYGN2ACQ__M                                                 0xFF
#define VSB_TOP_CYGN2ACQ__PRE                                               0x3

#define VSB_TOP_CYGN2TRK__A                                                 0x1C10018
#define VSB_TOP_CYGN2TRK__W                                                 8
#define VSB_TOP_CYGN2TRK__M                                                 0xFF
#define VSB_TOP_CYGN2TRK__PRE                                               0x2

#define VSB_TOP_CYGN3__A                                                    0x1C10019
#define VSB_TOP_CYGN3__W                                                    8
#define VSB_TOP_CYGN3__M                                                    0xFF
#define VSB_TOP_CYGN3__PRE                                                  0x6
#define VSB_TOP_SYNCCTRLWORD__A                                             0x1C1001A
#define VSB_TOP_SYNCCTRLWORD__W                                             5
#define VSB_TOP_SYNCCTRLWORD__M                                             0x1F
#define VSB_TOP_SYNCCTRLWORD__PRE                                           0x0

#define   VSB_TOP_SYNCCTRLWORD_PRST__B                                      0
#define   VSB_TOP_SYNCCTRLWORD_PRST__W                                      1
#define   VSB_TOP_SYNCCTRLWORD_PRST__M                                      0x1
#define   VSB_TOP_SYNCCTRLWORD_PRST__PRE                                    0x0

#define   VSB_TOP_SYNCCTRLWORD_DCFREEZ__B                                   1
#define   VSB_TOP_SYNCCTRLWORD_DCFREEZ__W                                   1
#define   VSB_TOP_SYNCCTRLWORD_DCFREEZ__M                                   0x2
#define   VSB_TOP_SYNCCTRLWORD_DCFREEZ__PRE                                 0x0

#define   VSB_TOP_SYNCCTRLWORD_INVCNST__B                                   2
#define   VSB_TOP_SYNCCTRLWORD_INVCNST__W                                   1
#define   VSB_TOP_SYNCCTRLWORD_INVCNST__M                                   0x4
#define   VSB_TOP_SYNCCTRLWORD_INVCNST__PRE                                 0x0

#define   VSB_TOP_SYNCCTRLWORD_CPUAGCRST__B                                 3
#define   VSB_TOP_SYNCCTRLWORD_CPUAGCRST__W                                 1
#define   VSB_TOP_SYNCCTRLWORD_CPUAGCRST__M                                 0x8
#define   VSB_TOP_SYNCCTRLWORD_CPUAGCRST__PRE                               0x0

#define   VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__B                               4
#define   VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__W                               1
#define   VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__M                               0x10
#define   VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__PRE                             0x0

#define VSB_TOP_MAINSMUP__A                                                 0x1C1001B
#define VSB_TOP_MAINSMUP__W                                                 8
#define VSB_TOP_MAINSMUP__M                                                 0xFF
#define VSB_TOP_MAINSMUP__PRE                                               0xFF

#define VSB_TOP_EQSMUP__A                                                   0x1C1001C
#define VSB_TOP_EQSMUP__W                                                   8
#define VSB_TOP_EQSMUP__M                                                   0xFF
#define VSB_TOP_EQSMUP__PRE                                                 0xFF
#define VSB_TOP_SYSMUXCTRL__A                                               0x1C1001D
#define VSB_TOP_SYSMUXCTRL__W                                               13
#define VSB_TOP_SYSMUXCTRL__M                                               0x1FFF
#define VSB_TOP_SYSMUXCTRL__PRE                                             0x0

#define   VSB_TOP_SYSMUXCTRL_CYLK_STATIC__B                                 0
#define   VSB_TOP_SYSMUXCTRL_CYLK_STATIC__W                                 1
#define   VSB_TOP_SYSMUXCTRL_CYLK_STATIC__M                                 0x1
#define   VSB_TOP_SYSMUXCTRL_CYLK_STATIC__PRE                               0x0

#define   VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__B                             1
#define   VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__W                             1
#define   VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__M                             0x2
#define   VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__PRE                           0x0

#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__B                            2
#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__W                            1
#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__M                            0x4
#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__PRE                          0x0

#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__B                        3
#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__W                        1
#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__M                        0x8
#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__PRE                      0x0

#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__B                            4
#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__W                            1
#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__M                            0x10
#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__PRE                          0x0

#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__B                        5
#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__W                        1
#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__M                        0x20
#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__PRE                      0x0

#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__B                            6
#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__W                            1
#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__M                            0x40
#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__PRE                          0x0

#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__B                        7
#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__W                        1
#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__M                        0x80
#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__PRE                      0x0

#define   VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__B                              8
#define   VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__W                              4
#define   VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__M                              0xF00
#define   VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__PRE                            0x0

#define   VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__B                          12
#define   VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__W                          1
#define   VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__M                          0x1000
#define   VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__PRE                        0x0

#define VSB_TOP_SNRTH_RCA1__A                                               0x1C1001E
#define VSB_TOP_SNRTH_RCA1__W                                               8
#define VSB_TOP_SNRTH_RCA1__M                                               0xFF
#define VSB_TOP_SNRTH_RCA1__PRE                                             0x53

#define   VSB_TOP_SNRTH_RCA1_DN__B                                          0
#define   VSB_TOP_SNRTH_RCA1_DN__W                                          4
#define   VSB_TOP_SNRTH_RCA1_DN__M                                          0xF
#define   VSB_TOP_SNRTH_RCA1_DN__PRE                                        0x3

#define   VSB_TOP_SNRTH_RCA1_UP__B                                          4
#define   VSB_TOP_SNRTH_RCA1_UP__W                                          4
#define   VSB_TOP_SNRTH_RCA1_UP__M                                          0xF0
#define   VSB_TOP_SNRTH_RCA1_UP__PRE                                        0x50

#define VSB_TOP_SNRTH_RCA2__A                                               0x1C1001F
#define VSB_TOP_SNRTH_RCA2__W                                               8
#define VSB_TOP_SNRTH_RCA2__M                                               0xFF
#define VSB_TOP_SNRTH_RCA2__PRE                                             0x75

#define   VSB_TOP_SNRTH_RCA2_DN__B                                          0
#define   VSB_TOP_SNRTH_RCA2_DN__W                                          4
#define   VSB_TOP_SNRTH_RCA2_DN__M                                          0xF
#define   VSB_TOP_SNRTH_RCA2_DN__PRE                                        0x5

#define   VSB_TOP_SNRTH_RCA2_UP__B                                          4
#define   VSB_TOP_SNRTH_RCA2_UP__W                                          4
#define   VSB_TOP_SNRTH_RCA2_UP__M                                          0xF0
#define   VSB_TOP_SNRTH_RCA2_UP__PRE                                        0x70

#define VSB_TOP_SNRTH_DDM1__A                                               0x1C10020
#define VSB_TOP_SNRTH_DDM1__W                                               8
#define VSB_TOP_SNRTH_DDM1__M                                               0xFF
#define VSB_TOP_SNRTH_DDM1__PRE                                             0xCA

#define   VSB_TOP_SNRTH_DDM1_DN__B                                          0
#define   VSB_TOP_SNRTH_DDM1_DN__W                                          4
#define   VSB_TOP_SNRTH_DDM1_DN__M                                          0xF
#define   VSB_TOP_SNRTH_DDM1_DN__PRE                                        0xA

#define   VSB_TOP_SNRTH_DDM1_UP__B                                          4
#define   VSB_TOP_SNRTH_DDM1_UP__W                                          4
#define   VSB_TOP_SNRTH_DDM1_UP__M                                          0xF0
#define   VSB_TOP_SNRTH_DDM1_UP__PRE                                        0xC0

#define VSB_TOP_SNRTH_DDM2__A                                               0x1C10021
#define VSB_TOP_SNRTH_DDM2__W                                               8
#define VSB_TOP_SNRTH_DDM2__M                                               0xFF
#define VSB_TOP_SNRTH_DDM2__PRE                                             0xCA

#define   VSB_TOP_SNRTH_DDM2_DN__B                                          0
#define   VSB_TOP_SNRTH_DDM2_DN__W                                          4
#define   VSB_TOP_SNRTH_DDM2_DN__M                                          0xF
#define   VSB_TOP_SNRTH_DDM2_DN__PRE                                        0xA

#define   VSB_TOP_SNRTH_DDM2_UP__B                                          4
#define   VSB_TOP_SNRTH_DDM2_UP__W                                          4
#define   VSB_TOP_SNRTH_DDM2_UP__M                                          0xF0
#define   VSB_TOP_SNRTH_DDM2_UP__PRE                                        0xC0

#define VSB_TOP_SNRTH_PT__A                                                 0x1C10022
#define VSB_TOP_SNRTH_PT__W                                                 8
#define VSB_TOP_SNRTH_PT__M                                                 0xFF
#define VSB_TOP_SNRTH_PT__PRE                                               0xD8

#define   VSB_TOP_SNRTH_PT_DN__B                                            0
#define   VSB_TOP_SNRTH_PT_DN__W                                            4
#define   VSB_TOP_SNRTH_PT_DN__M                                            0xF
#define   VSB_TOP_SNRTH_PT_DN__PRE                                          0x8

#define   VSB_TOP_SNRTH_PT_UP__B                                            4
#define   VSB_TOP_SNRTH_PT_UP__W                                            4
#define   VSB_TOP_SNRTH_PT_UP__M                                            0xF0
#define   VSB_TOP_SNRTH_PT_UP__PRE                                          0xD0

#define VSB_TOP_CYSMSTATES__A                                               0x1C10023
#define VSB_TOP_CYSMSTATES__W                                               8
#define VSB_TOP_CYSMSTATES__M                                               0xFF
#define VSB_TOP_CYSMSTATES__PRE                                             0x0

#define   VSB_TOP_CYSMSTATES_SYSST__B                                       0
#define   VSB_TOP_CYSMSTATES_SYSST__W                                       4
#define   VSB_TOP_CYSMSTATES_SYSST__M                                       0xF
#define   VSB_TOP_CYSMSTATES_SYSST__PRE                                     0x0

#define   VSB_TOP_CYSMSTATES_EQST__B                                        4
#define   VSB_TOP_CYSMSTATES_EQST__W                                        4
#define   VSB_TOP_CYSMSTATES_EQST__M                                        0xF0
#define   VSB_TOP_CYSMSTATES_EQST__PRE                                      0x0

#define VSB_TOP_SMALL_NOTCH_CONTROL__A                                      0x1C10024
#define VSB_TOP_SMALL_NOTCH_CONTROL__W                                      8
#define VSB_TOP_SMALL_NOTCH_CONTROL__M                                      0xFF
#define VSB_TOP_SMALL_NOTCH_CONTROL__PRE                                    0x0

#define   VSB_TOP_SMALL_NOTCH_CONTROL_GO__B                                 0
#define   VSB_TOP_SMALL_NOTCH_CONTROL_GO__W                                 1
#define   VSB_TOP_SMALL_NOTCH_CONTROL_GO__M                                 0x1
#define   VSB_TOP_SMALL_NOTCH_CONTROL_GO__PRE                               0x0

#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__B                            1
#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__W                            1
#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__M                            0x2
#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__PRE                          0x0

#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__B                            2
#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__W                            1
#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__M                            0x4
#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__PRE                          0x0

#define   VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__B                              3
#define   VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__W                              4
#define   VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__M                              0x78
#define   VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__PRE                            0x0

#define   VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__B                         7
#define   VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__W                         1
#define   VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__M                         0x80
#define   VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__PRE                       0x0

#define VSB_TOP_TAPREADCYC__A                                               0x1C10025
#define VSB_TOP_TAPREADCYC__W                                               9
#define VSB_TOP_TAPREADCYC__M                                               0x1FF
#define VSB_TOP_TAPREADCYC__PRE                                             0x1

#define VSB_TOP_VALIDPKLVL__A                                               0x1C10026
#define VSB_TOP_VALIDPKLVL__W                                               13
#define VSB_TOP_VALIDPKLVL__M                                               0x1FFF
#define VSB_TOP_VALIDPKLVL__PRE                                             0x100

#define VSB_TOP_CENTROID_FINE_DELAY__A                                      0x1C10027
#define VSB_TOP_CENTROID_FINE_DELAY__W                                      10
#define VSB_TOP_CENTROID_FINE_DELAY__M                                      0x3FF
#define VSB_TOP_CENTROID_FINE_DELAY__PRE                                    0xFF

#define VSB_TOP_CENTROID_SMACH_DELAY__A                                     0x1C10028
#define VSB_TOP_CENTROID_SMACH_DELAY__W                                     10
#define VSB_TOP_CENTROID_SMACH_DELAY__M                                     0x3FF
#define VSB_TOP_CENTROID_SMACH_DELAY__PRE                                   0x1FF

#define VSB_TOP_SNR__A                                                      0x1C10029
#define VSB_TOP_SNR__W                                                      14
#define VSB_TOP_SNR__M                                                      0x3FFF
#define VSB_TOP_SNR__PRE                                                    0x0
#define VSB_TOP_LOCKSTATUS__A                                               0x1C1002A
#define VSB_TOP_LOCKSTATUS__W                                               7
#define VSB_TOP_LOCKSTATUS__M                                               0x7F
#define VSB_TOP_LOCKSTATUS__PRE                                             0x0

#define   VSB_TOP_LOCKSTATUS_VSBMODE__B                                     0
#define   VSB_TOP_LOCKSTATUS_VSBMODE__W                                     4
#define   VSB_TOP_LOCKSTATUS_VSBMODE__M                                     0xF
#define   VSB_TOP_LOCKSTATUS_VSBMODE__PRE                                   0x0

#define   VSB_TOP_LOCKSTATUS_FRMLOCK__B                                     4
#define   VSB_TOP_LOCKSTATUS_FRMLOCK__W                                     1
#define   VSB_TOP_LOCKSTATUS_FRMLOCK__M                                     0x10
#define   VSB_TOP_LOCKSTATUS_FRMLOCK__PRE                                   0x0

#define   VSB_TOP_LOCKSTATUS_CYLOCK__B                                      5
#define   VSB_TOP_LOCKSTATUS_CYLOCK__W                                      1
#define   VSB_TOP_LOCKSTATUS_CYLOCK__M                                      0x20
#define   VSB_TOP_LOCKSTATUS_CYLOCK__PRE                                    0x0

#define   VSB_TOP_LOCKSTATUS_DDMON__B                                       6
#define   VSB_TOP_LOCKSTATUS_DDMON__W                                       1
#define   VSB_TOP_LOCKSTATUS_DDMON__M                                       0x40
#define   VSB_TOP_LOCKSTATUS_DDMON__PRE                                     0x0

#define VSB_TOP_CTST__A                                                     0x1C1002B
#define VSB_TOP_CTST__W                                                     4
#define VSB_TOP_CTST__M                                                     0xF
#define VSB_TOP_CTST__PRE                                                   0x0
#define VSB_TOP_EQSMRSTCTRL__A                                              0x1C1002C
#define VSB_TOP_EQSMRSTCTRL__W                                              7
#define VSB_TOP_EQSMRSTCTRL__M                                              0x7F
#define VSB_TOP_EQSMRSTCTRL__PRE                                            0x0

#define   VSB_TOP_EQSMRSTCTRL_RCAON__B                                      0
#define   VSB_TOP_EQSMRSTCTRL_RCAON__W                                      1
#define   VSB_TOP_EQSMRSTCTRL_RCAON__M                                      0x1
#define   VSB_TOP_EQSMRSTCTRL_RCAON__PRE                                    0x0

#define   VSB_TOP_EQSMRSTCTRL_DFEON__B                                      1
#define   VSB_TOP_EQSMRSTCTRL_DFEON__W                                      1
#define   VSB_TOP_EQSMRSTCTRL_DFEON__M                                      0x2
#define   VSB_TOP_EQSMRSTCTRL_DFEON__PRE                                    0x0

#define   VSB_TOP_EQSMRSTCTRL_DDMEN1__B                                     2
#define   VSB_TOP_EQSMRSTCTRL_DDMEN1__W                                     1
#define   VSB_TOP_EQSMRSTCTRL_DDMEN1__M                                     0x4
#define   VSB_TOP_EQSMRSTCTRL_DDMEN1__PRE                                   0x0

#define   VSB_TOP_EQSMRSTCTRL_DDMEN2__B                                     3
#define   VSB_TOP_EQSMRSTCTRL_DDMEN2__W                                     1
#define   VSB_TOP_EQSMRSTCTRL_DDMEN2__M                                     0x8
#define   VSB_TOP_EQSMRSTCTRL_DDMEN2__PRE                                   0x0

#define   VSB_TOP_EQSMRSTCTRL_DIGIAGCON__B                                  4
#define   VSB_TOP_EQSMRSTCTRL_DIGIAGCON__W                                  1
#define   VSB_TOP_EQSMRSTCTRL_DIGIAGCON__M                                  0x10
#define   VSB_TOP_EQSMRSTCTRL_DIGIAGCON__PRE                                0x0

#define   VSB_TOP_EQSMRSTCTRL_PARAINITEN__B                                 5
#define   VSB_TOP_EQSMRSTCTRL_PARAINITEN__W                                 1
#define   VSB_TOP_EQSMRSTCTRL_PARAINITEN__M                                 0x20
#define   VSB_TOP_EQSMRSTCTRL_PARAINITEN__PRE                               0x0

#define   VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__B                            6
#define   VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__W                            1
#define   VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__M                            0x40
#define   VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__PRE                          0x0

#define VSB_TOP_EQSMTRNCTRL__A                                              0x1C1002D
#define VSB_TOP_EQSMTRNCTRL__W                                              7
#define VSB_TOP_EQSMTRNCTRL__M                                              0x7F
#define VSB_TOP_EQSMTRNCTRL__PRE                                            0x40

#define   VSB_TOP_EQSMTRNCTRL_RCAON__B                                      0
#define   VSB_TOP_EQSMTRNCTRL_RCAON__W                                      1
#define   VSB_TOP_EQSMTRNCTRL_RCAON__M                                      0x1
#define   VSB_TOP_EQSMTRNCTRL_RCAON__PRE                                    0x0

#define   VSB_TOP_EQSMTRNCTRL_DFEON__B                                      1
#define   VSB_TOP_EQSMTRNCTRL_DFEON__W                                      1
#define   VSB_TOP_EQSMTRNCTRL_DFEON__M                                      0x2
#define   VSB_TOP_EQSMTRNCTRL_DFEON__PRE                                    0x0

#define   VSB_TOP_EQSMTRNCTRL_DDMEN1__B                                     2
#define   VSB_TOP_EQSMTRNCTRL_DDMEN1__W                                     1
#define   VSB_TOP_EQSMTRNCTRL_DDMEN1__M                                     0x4
#define   VSB_TOP_EQSMTRNCTRL_DDMEN1__PRE                                   0x0

#define   VSB_TOP_EQSMTRNCTRL_DDMEN2__B                                     3
#define   VSB_TOP_EQSMTRNCTRL_DDMEN2__W                                     1
#define   VSB_TOP_EQSMTRNCTRL_DDMEN2__M                                     0x8
#define   VSB_TOP_EQSMTRNCTRL_DDMEN2__PRE                                   0x0

#define   VSB_TOP_EQSMTRNCTRL_DIGIAGCON__B                                  4
#define   VSB_TOP_EQSMTRNCTRL_DIGIAGCON__W                                  1
#define   VSB_TOP_EQSMTRNCTRL_DIGIAGCON__M                                  0x10
#define   VSB_TOP_EQSMTRNCTRL_DIGIAGCON__PRE                                0x0

#define   VSB_TOP_EQSMTRNCTRL_PARAINITEN__B                                 5
#define   VSB_TOP_EQSMTRNCTRL_PARAINITEN__W                                 1
#define   VSB_TOP_EQSMTRNCTRL_PARAINITEN__M                                 0x20
#define   VSB_TOP_EQSMTRNCTRL_PARAINITEN__PRE                               0x0

#define   VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__B                            6
#define   VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__W                            1
#define   VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__M                            0x40
#define   VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__PRE                          0x40

#define VSB_TOP_EQSMRCA1CTRL__A                                             0x1C1002E
#define VSB_TOP_EQSMRCA1CTRL__W                                             7
#define VSB_TOP_EQSMRCA1CTRL__M                                             0x7F
#define VSB_TOP_EQSMRCA1CTRL__PRE                                           0x1

#define   VSB_TOP_EQSMRCA1CTRL_RCAON__B                                     0
#define   VSB_TOP_EQSMRCA1CTRL_RCAON__W                                     1
#define   VSB_TOP_EQSMRCA1CTRL_RCAON__M                                     0x1
#define   VSB_TOP_EQSMRCA1CTRL_RCAON__PRE                                   0x1

#define   VSB_TOP_EQSMRCA1CTRL_DFEON__B                                     1
#define   VSB_TOP_EQSMRCA1CTRL_DFEON__W                                     1
#define   VSB_TOP_EQSMRCA1CTRL_DFEON__M                                     0x2
#define   VSB_TOP_EQSMRCA1CTRL_DFEON__PRE                                   0x0

#define   VSB_TOP_EQSMRCA1CTRL_DDMEN1__B                                    2
#define   VSB_TOP_EQSMRCA1CTRL_DDMEN1__W                                    1
#define   VSB_TOP_EQSMRCA1CTRL_DDMEN1__M                                    0x4
#define   VSB_TOP_EQSMRCA1CTRL_DDMEN1__PRE                                  0x0

#define   VSB_TOP_EQSMRCA1CTRL_DDMEN2__B                                    3
#define   VSB_TOP_EQSMRCA1CTRL_DDMEN2__W                                    1
#define   VSB_TOP_EQSMRCA1CTRL_DDMEN2__M                                    0x8
#define   VSB_TOP_EQSMRCA1CTRL_DDMEN2__PRE                                  0x0

#define   VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__B                                 4
#define   VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__W                                 1
#define   VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__M                                 0x10
#define   VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__PRE                               0x0

#define   VSB_TOP_EQSMRCA1CTRL_PARAINITEN__B                                5
#define   VSB_TOP_EQSMRCA1CTRL_PARAINITEN__W                                1
#define   VSB_TOP_EQSMRCA1CTRL_PARAINITEN__M                                0x20
#define   VSB_TOP_EQSMRCA1CTRL_PARAINITEN__PRE                              0x0

#define   VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__B                           6
#define   VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__W                           1
#define   VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__M                           0x40
#define   VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__PRE                         0x0

#define VSB_TOP_EQSMRCA2CTRL__A                                             0x1C1002F
#define VSB_TOP_EQSMRCA2CTRL__W                                             7
#define VSB_TOP_EQSMRCA2CTRL__M                                             0x7F
#define VSB_TOP_EQSMRCA2CTRL__PRE                                           0x3

#define   VSB_TOP_EQSMRCA2CTRL_RCAON__B                                     0
#define   VSB_TOP_EQSMRCA2CTRL_RCAON__W                                     1
#define   VSB_TOP_EQSMRCA2CTRL_RCAON__M                                     0x1
#define   VSB_TOP_EQSMRCA2CTRL_RCAON__PRE                                   0x1

#define   VSB_TOP_EQSMRCA2CTRL_DFEON__B                                     1
#define   VSB_TOP_EQSMRCA2CTRL_DFEON__W                                     1
#define   VSB_TOP_EQSMRCA2CTRL_DFEON__M                                     0x2
#define   VSB_TOP_EQSMRCA2CTRL_DFEON__PRE                                   0x2

#define   VSB_TOP_EQSMRCA2CTRL_DDMEN1__B                                    2
#define   VSB_TOP_EQSMRCA2CTRL_DDMEN1__W                                    1
#define   VSB_TOP_EQSMRCA2CTRL_DDMEN1__M                                    0x4
#define   VSB_TOP_EQSMRCA2CTRL_DDMEN1__PRE                                  0x0

#define   VSB_TOP_EQSMRCA2CTRL_DDMEN2__B                                    3
#define   VSB_TOP_EQSMRCA2CTRL_DDMEN2__W                                    1
#define   VSB_TOP_EQSMRCA2CTRL_DDMEN2__M                                    0x8
#define   VSB_TOP_EQSMRCA2CTRL_DDMEN2__PRE                                  0x0

#define   VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__B                                 4
#define   VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__W                                 1
#define   VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__M                                 0x10
#define   VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__PRE                               0x0

#define   VSB_TOP_EQSMRCA2CTRL_PARAINITEN__B                                5
#define   VSB_TOP_EQSMRCA2CTRL_PARAINITEN__W                                1
#define   VSB_TOP_EQSMRCA2CTRL_PARAINITEN__M                                0x20
#define   VSB_TOP_EQSMRCA2CTRL_PARAINITEN__PRE                              0x0

#define   VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__B                           6
#define   VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__W                           1
#define   VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__M                           0x40
#define   VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__PRE                         0x0

#define VSB_TOP_EQSMDDM1CTRL__A                                             0x1C10030
#define VSB_TOP_EQSMDDM1CTRL__W                                             7
#define VSB_TOP_EQSMDDM1CTRL__M                                             0x7F
#define VSB_TOP_EQSMDDM1CTRL__PRE                                           0x6

#define   VSB_TOP_EQSMDDM1CTRL_RCAON__B                                     0
#define   VSB_TOP_EQSMDDM1CTRL_RCAON__W                                     1
#define   VSB_TOP_EQSMDDM1CTRL_RCAON__M                                     0x1
#define   VSB_TOP_EQSMDDM1CTRL_RCAON__PRE                                   0x0

#define   VSB_TOP_EQSMDDM1CTRL_DFEON__B                                     1
#define   VSB_TOP_EQSMDDM1CTRL_DFEON__W                                     1
#define   VSB_TOP_EQSMDDM1CTRL_DFEON__M                                     0x2
#define   VSB_TOP_EQSMDDM1CTRL_DFEON__PRE                                   0x2

#define   VSB_TOP_EQSMDDM1CTRL_DDMEN1__B                                    2
#define   VSB_TOP_EQSMDDM1CTRL_DDMEN1__W                                    1
#define   VSB_TOP_EQSMDDM1CTRL_DDMEN1__M                                    0x4
#define   VSB_TOP_EQSMDDM1CTRL_DDMEN1__PRE                                  0x4

#define   VSB_TOP_EQSMDDM1CTRL_DDMEN2__B                                    3
#define   VSB_TOP_EQSMDDM1CTRL_DDMEN2__W                                    1
#define   VSB_TOP_EQSMDDM1CTRL_DDMEN2__M                                    0x8
#define   VSB_TOP_EQSMDDM1CTRL_DDMEN2__PRE                                  0x0

#define   VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__B                                 4
#define   VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__W                                 1
#define   VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__M                                 0x10
#define   VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__PRE                               0x0

#define   VSB_TOP_EQSMDDM1CTRL_PARAINITEN__B                                5
#define   VSB_TOP_EQSMDDM1CTRL_PARAINITEN__W                                1
#define   VSB_TOP_EQSMDDM1CTRL_PARAINITEN__M                                0x20
#define   VSB_TOP_EQSMDDM1CTRL_PARAINITEN__PRE                              0x0

#define   VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__B                           6
#define   VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__W                           1
#define   VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__M                           0x40
#define   VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__PRE                         0x0

#define VSB_TOP_EQSMDDM2CTRL__A                                             0x1C10031
#define VSB_TOP_EQSMDDM2CTRL__W                                             7
#define VSB_TOP_EQSMDDM2CTRL__M                                             0x7F
#define VSB_TOP_EQSMDDM2CTRL__PRE                                           0x1E

#define   VSB_TOP_EQSMDDM2CTRL_RCAON__B                                     0
#define   VSB_TOP_EQSMDDM2CTRL_RCAON__W                                     1
#define   VSB_TOP_EQSMDDM2CTRL_RCAON__M                                     0x1
#define   VSB_TOP_EQSMDDM2CTRL_RCAON__PRE                                   0x0

#define   VSB_TOP_EQSMDDM2CTRL_DFEON__B                                     1
#define   VSB_TOP_EQSMDDM2CTRL_DFEON__W                                     1
#define   VSB_TOP_EQSMDDM2CTRL_DFEON__M                                     0x2
#define   VSB_TOP_EQSMDDM2CTRL_DFEON__PRE                                   0x2

#define   VSB_TOP_EQSMDDM2CTRL_DDMEN1__B                                    2
#define   VSB_TOP_EQSMDDM2CTRL_DDMEN1__W                                    1
#define   VSB_TOP_EQSMDDM2CTRL_DDMEN1__M                                    0x4
#define   VSB_TOP_EQSMDDM2CTRL_DDMEN1__PRE                                  0x4

#define   VSB_TOP_EQSMDDM2CTRL_DDMEN2__B                                    3
#define   VSB_TOP_EQSMDDM2CTRL_DDMEN2__W                                    1
#define   VSB_TOP_EQSMDDM2CTRL_DDMEN2__M                                    0x8
#define   VSB_TOP_EQSMDDM2CTRL_DDMEN2__PRE                                  0x8

#define   VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__B                                 4
#define   VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__W                                 1
#define   VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__M                                 0x10
#define   VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__PRE                               0x10

#define   VSB_TOP_EQSMDDM2CTRL_PARAINITEN__B                                5
#define   VSB_TOP_EQSMDDM2CTRL_PARAINITEN__W                                1
#define   VSB_TOP_EQSMDDM2CTRL_PARAINITEN__M                                0x20
#define   VSB_TOP_EQSMDDM2CTRL_PARAINITEN__PRE                              0x0

#define   VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__B                           6
#define   VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__W                           1
#define   VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__M                           0x40
#define   VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__PRE                         0x0

#define VSB_TOP_SYSSMRSTCTRL__A                                             0x1C10032
#define VSB_TOP_SYSSMRSTCTRL__W                                             11
#define VSB_TOP_SYSSMRSTCTRL__M                                             0x7FF
#define VSB_TOP_SYSSMRSTCTRL__PRE                                           0x7F9

#define   VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__B                                  0
#define   VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__W                                  1
#define   VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__M                                  0x1
#define   VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__PRE                                0x1

#define   VSB_TOP_SYSSMRSTCTRL_CTCALEN__B                                   1
#define   VSB_TOP_SYSSMRSTCTRL_CTCALEN__W                                   1
#define   VSB_TOP_SYSSMRSTCTRL_CTCALEN__M                                   0x2
#define   VSB_TOP_SYSSMRSTCTRL_CTCALEN__PRE                                 0x0

#define   VSB_TOP_SYSSMRSTCTRL_STARTTRN__B                                  2
#define   VSB_TOP_SYSSMRSTCTRL_STARTTRN__W                                  1
#define   VSB_TOP_SYSSMRSTCTRL_STARTTRN__M                                  0x4
#define   VSB_TOP_SYSSMRSTCTRL_STARTTRN__PRE                                0x0

#define   VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__B                             3
#define   VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__W                             1
#define   VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__M                             0x8
#define   VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__PRE                           0x8

#define   VSB_TOP_SYSSMRSTCTRL_RSTCYDET__B                                  4
#define   VSB_TOP_SYSSMRSTCTRL_RSTCYDET__W                                  1
#define   VSB_TOP_SYSSMRSTCTRL_RSTCYDET__M                                  0x10
#define   VSB_TOP_SYSSMRSTCTRL_RSTCYDET__PRE                                0x10

#define   VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__B                                  5
#define   VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__W                                  1
#define   VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__M                                  0x20
#define   VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__PRE                                0x20

#define   VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__B                                  6
#define   VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__W                                  1
#define   VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__M                                  0x40
#define   VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__PRE                                0x40

#define   VSB_TOP_SYSSMRSTCTRL_CKFRZ__B                                     7
#define   VSB_TOP_SYSSMRSTCTRL_CKFRZ__W                                     1
#define   VSB_TOP_SYSSMRSTCTRL_CKFRZ__M                                     0x80
#define   VSB_TOP_SYSSMRSTCTRL_CKFRZ__PRE                                   0x80

#define   VSB_TOP_SYSSMRSTCTRL_CKBWSW__B                                    8
#define   VSB_TOP_SYSSMRSTCTRL_CKBWSW__W                                    1
#define   VSB_TOP_SYSSMRSTCTRL_CKBWSW__M                                    0x100
#define   VSB_TOP_SYSSMRSTCTRL_CKBWSW__PRE                                  0x100

#define   VSB_TOP_SYSSMRSTCTRL_NCOBWSW__B                                   9
#define   VSB_TOP_SYSSMRSTCTRL_NCOBWSW__W                                   1
#define   VSB_TOP_SYSSMRSTCTRL_NCOBWSW__M                                   0x200
#define   VSB_TOP_SYSSMRSTCTRL_NCOBWSW__PRE                                 0x200

#define   VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__B                           10
#define   VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__W                           1
#define   VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__M                           0x400
#define   VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__PRE                         0x400

#define VSB_TOP_SYSSMCYCTRL__A                                              0x1C10033
#define VSB_TOP_SYSSMCYCTRL__W                                              11
#define VSB_TOP_SYSSMCYCTRL__M                                              0x7FF
#define VSB_TOP_SYSSMCYCTRL__PRE                                            0x4E9

#define   VSB_TOP_SYSSMCYCTRL_RSTCTCAL__B                                   0
#define   VSB_TOP_SYSSMCYCTRL_RSTCTCAL__W                                   1
#define   VSB_TOP_SYSSMCYCTRL_RSTCTCAL__M                                   0x1
#define   VSB_TOP_SYSSMCYCTRL_RSTCTCAL__PRE                                 0x1

#define   VSB_TOP_SYSSMCYCTRL_CTCALEN__B                                    1
#define   VSB_TOP_SYSSMCYCTRL_CTCALEN__W                                    1
#define   VSB_TOP_SYSSMCYCTRL_CTCALEN__M                                    0x2
#define   VSB_TOP_SYSSMCYCTRL_CTCALEN__PRE                                  0x0

#define   VSB_TOP_SYSSMCYCTRL_STARTTRN__B                                   2
#define   VSB_TOP_SYSSMCYCTRL_STARTTRN__W                                   1
#define   VSB_TOP_SYSSMCYCTRL_STARTTRN__M                                   0x4
#define   VSB_TOP_SYSSMCYCTRL_STARTTRN__PRE                                 0x0

#define   VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__B                              3
#define   VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__W                              1
#define   VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__M                              0x8
#define   VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__PRE                            0x8

#define   VSB_TOP_SYSSMCYCTRL_RSTCYDET__B                                   4
#define   VSB_TOP_SYSSMCYCTRL_RSTCYDET__W                                   1
#define   VSB_TOP_SYSSMCYCTRL_RSTCYDET__M                                   0x10
#define   VSB_TOP_SYSSMCYCTRL_RSTCYDET__PRE                                 0x0

#define   VSB_TOP_SYSSMCYCTRL_RSTDCRMV__B                                   5
#define   VSB_TOP_SYSSMCYCTRL_RSTDCRMV__W                                   1
#define   VSB_TOP_SYSSMCYCTRL_RSTDCRMV__M                                   0x20
#define   VSB_TOP_SYSSMCYCTRL_RSTDCRMV__PRE                                 0x20

#define   VSB_TOP_SYSSMCYCTRL_RSTEQSIG__B                                   6
#define   VSB_TOP_SYSSMCYCTRL_RSTEQSIG__W                                   1
#define   VSB_TOP_SYSSMCYCTRL_RSTEQSIG__M                                   0x40
#define   VSB_TOP_SYSSMCYCTRL_RSTEQSIG__PRE                                 0x40

#define   VSB_TOP_SYSSMCYCTRL_CKFRZ__B                                      7
#define   VSB_TOP_SYSSMCYCTRL_CKFRZ__W                                      1
#define   VSB_TOP_SYSSMCYCTRL_CKFRZ__M                                      0x80
#define   VSB_TOP_SYSSMCYCTRL_CKFRZ__PRE                                    0x80

#define   VSB_TOP_SYSSMCYCTRL_CKBWSW__B                                     8
#define   VSB_TOP_SYSSMCYCTRL_CKBWSW__W                                     1
#define   VSB_TOP_SYSSMCYCTRL_CKBWSW__M                                     0x100
#define   VSB_TOP_SYSSMCYCTRL_CKBWSW__PRE                                   0x0

#define   VSB_TOP_SYSSMCYCTRL_NCOBWSW__B                                    9
#define   VSB_TOP_SYSSMCYCTRL_NCOBWSW__W                                    1
#define   VSB_TOP_SYSSMCYCTRL_NCOBWSW__M                                    0x200
#define   VSB_TOP_SYSSMCYCTRL_NCOBWSW__PRE                                  0x0

#define   VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__B                            10
#define   VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__W                            1
#define   VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__M                            0x400
#define   VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__PRE                          0x400

#define VSB_TOP_SYSSMTRNCTRL__A                                             0x1C10034
#define VSB_TOP_SYSSMTRNCTRL__W                                             11
#define VSB_TOP_SYSSMTRNCTRL__M                                             0x7FF
#define VSB_TOP_SYSSMTRNCTRL__PRE                                           0x204

#define   VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__B                                  0
#define   VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__W                                  1
#define   VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__M                                  0x1
#define   VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__PRE                                0x0

#define   VSB_TOP_SYSSMTRNCTRL_CTCALEN__B                                   1
#define   VSB_TOP_SYSSMTRNCTRL_CTCALEN__W                                   1
#define   VSB_TOP_SYSSMTRNCTRL_CTCALEN__M                                   0x2
#define   VSB_TOP_SYSSMTRNCTRL_CTCALEN__PRE                                 0x0

#define   VSB_TOP_SYSSMTRNCTRL_STARTTRN__B                                  2
#define   VSB_TOP_SYSSMTRNCTRL_STARTTRN__W                                  1
#define   VSB_TOP_SYSSMTRNCTRL_STARTTRN__M                                  0x4
#define   VSB_TOP_SYSSMTRNCTRL_STARTTRN__PRE                                0x4

#define   VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__B                             3
#define   VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__W                             1
#define   VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__M                             0x8
#define   VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__PRE                           0x0

#define   VSB_TOP_SYSSMTRNCTRL_RSTCYDET__B                                  4
#define   VSB_TOP_SYSSMTRNCTRL_RSTCYDET__W                                  1
#define   VSB_TOP_SYSSMTRNCTRL_RSTCYDET__M                                  0x10
#define   VSB_TOP_SYSSMTRNCTRL_RSTCYDET__PRE                                0x0

#define   VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__B                                  5
#define   VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__W                                  1
#define   VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__M                                  0x20
#define   VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__PRE                                0x0

#define   VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__B                                  6
#define   VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__W                                  1
#define   VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__M                                  0x40
#define   VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__PRE                                0x0

#define   VSB_TOP_SYSSMTRNCTRL_CKFRZ__B                                     7
#define   VSB_TOP_SYSSMTRNCTRL_CKFRZ__W                                     1
#define   VSB_TOP_SYSSMTRNCTRL_CKFRZ__M                                     0x80
#define   VSB_TOP_SYSSMTRNCTRL_CKFRZ__PRE                                   0x0

#define   VSB_TOP_SYSSMTRNCTRL_CKBWSW__B                                    8
#define   VSB_TOP_SYSSMTRNCTRL_CKBWSW__W                                    1
#define   VSB_TOP_SYSSMTRNCTRL_CKBWSW__M                                    0x100
#define   VSB_TOP_SYSSMTRNCTRL_CKBWSW__PRE                                  0x0

#define   VSB_TOP_SYSSMTRNCTRL_NCOBWSW__B                                   9
#define   VSB_TOP_SYSSMTRNCTRL_NCOBWSW__W                                   1
#define   VSB_TOP_SYSSMTRNCTRL_NCOBWSW__M                                   0x200
#define   VSB_TOP_SYSSMTRNCTRL_NCOBWSW__PRE                                 0x200

#define   VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__B                           10
#define   VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__W                           1
#define   VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M                           0x400
#define   VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__PRE                         0x0

#define VSB_TOP_SYSSMEQCTRL__A                                              0x1C10035
#define VSB_TOP_SYSSMEQCTRL__W                                              11
#define VSB_TOP_SYSSMEQCTRL__M                                              0x7FF
#define VSB_TOP_SYSSMEQCTRL__PRE                                            0x304

#define   VSB_TOP_SYSSMEQCTRL_RSTCTCAL__B                                   0
#define   VSB_TOP_SYSSMEQCTRL_RSTCTCAL__W                                   1
#define   VSB_TOP_SYSSMEQCTRL_RSTCTCAL__M                                   0x1
#define   VSB_TOP_SYSSMEQCTRL_RSTCTCAL__PRE                                 0x0

#define   VSB_TOP_SYSSMEQCTRL_CTCALEN__B                                    1
#define   VSB_TOP_SYSSMEQCTRL_CTCALEN__W                                    1
#define   VSB_TOP_SYSSMEQCTRL_CTCALEN__M                                    0x2
#define   VSB_TOP_SYSSMEQCTRL_CTCALEN__PRE                                  0x0

#define   VSB_TOP_SYSSMEQCTRL_STARTTRN__B                                   2
#define   VSB_TOP_SYSSMEQCTRL_STARTTRN__W                                   1
#define   VSB_TOP_SYSSMEQCTRL_STARTTRN__M                                   0x4
#define   VSB_TOP_SYSSMEQCTRL_STARTTRN__PRE                                 0x4

#define   VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__B                              3
#define   VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__W                              1
#define   VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__M                              0x8
#define   VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__PRE                            0x0

#define   VSB_TOP_SYSSMEQCTRL_RSTCYDET__B                                   4
#define   VSB_TOP_SYSSMEQCTRL_RSTCYDET__W                                   1
#define   VSB_TOP_SYSSMEQCTRL_RSTCYDET__M                                   0x10
#define   VSB_TOP_SYSSMEQCTRL_RSTCYDET__PRE                                 0x0

#define   VSB_TOP_SYSSMEQCTRL_RSTDCRMV__B                                   5
#define   VSB_TOP_SYSSMEQCTRL_RSTDCRMV__W                                   1
#define   VSB_TOP_SYSSMEQCTRL_RSTDCRMV__M                                   0x20
#define   VSB_TOP_SYSSMEQCTRL_RSTDCRMV__PRE                                 0x0

#define   VSB_TOP_SYSSMEQCTRL_RSTEQSIG__B                                   6
#define   VSB_TOP_SYSSMEQCTRL_RSTEQSIG__W                                   1
#define   VSB_TOP_SYSSMEQCTRL_RSTEQSIG__M                                   0x40
#define   VSB_TOP_SYSSMEQCTRL_RSTEQSIG__PRE                                 0x0

#define   VSB_TOP_SYSSMEQCTRL_CKFRZ__B                                      7
#define   VSB_TOP_SYSSMEQCTRL_CKFRZ__W                                      1
#define   VSB_TOP_SYSSMEQCTRL_CKFRZ__M                                      0x80
#define   VSB_TOP_SYSSMEQCTRL_CKFRZ__PRE                                    0x0

#define   VSB_TOP_SYSSMEQCTRL_CKBWSW__B                                     8
#define   VSB_TOP_SYSSMEQCTRL_CKBWSW__W                                     1
#define   VSB_TOP_SYSSMEQCTRL_CKBWSW__M                                     0x100
#define   VSB_TOP_SYSSMEQCTRL_CKBWSW__PRE                                   0x100

#define   VSB_TOP_SYSSMEQCTRL_NCOBWSW__B                                    9
#define   VSB_TOP_SYSSMEQCTRL_NCOBWSW__W                                    1
#define   VSB_TOP_SYSSMEQCTRL_NCOBWSW__M                                    0x200
#define   VSB_TOP_SYSSMEQCTRL_NCOBWSW__PRE                                  0x200

#define   VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__B                            10
#define   VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__W                            1
#define   VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__M                            0x400
#define   VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__PRE                          0x0

#define VSB_TOP_SYSSMAGCCTRL__A                                             0x1C10036
#define VSB_TOP_SYSSMAGCCTRL__W                                             11
#define VSB_TOP_SYSSMAGCCTRL__M                                             0x7FF
#define VSB_TOP_SYSSMAGCCTRL__PRE                                           0xF9

#define   VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__B                                  0
#define   VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__W                                  1
#define   VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__M                                  0x1
#define   VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__PRE                                0x1

#define   VSB_TOP_SYSSMAGCCTRL_CTCALEN__B                                   1
#define   VSB_TOP_SYSSMAGCCTRL_CTCALEN__W                                   1
#define   VSB_TOP_SYSSMAGCCTRL_CTCALEN__M                                   0x2
#define   VSB_TOP_SYSSMAGCCTRL_CTCALEN__PRE                                 0x0

#define   VSB_TOP_SYSSMAGCCTRL_STARTTRN__B                                  2
#define   VSB_TOP_SYSSMAGCCTRL_STARTTRN__W                                  1
#define   VSB_TOP_SYSSMAGCCTRL_STARTTRN__M                                  0x4
#define   VSB_TOP_SYSSMAGCCTRL_STARTTRN__PRE                                0x0

#define   VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__B                             3
#define   VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__W                             1
#define   VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__M                             0x8
#define   VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__PRE                           0x8

#define   VSB_TOP_SYSSMAGCCTRL_RSTCYDET__B                                  4
#define   VSB_TOP_SYSSMAGCCTRL_RSTCYDET__W                                  1
#define   VSB_TOP_SYSSMAGCCTRL_RSTCYDET__M                                  0x10
#define   VSB_TOP_SYSSMAGCCTRL_RSTCYDET__PRE                                0x10

#define   VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__B                                  5
#define   VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__W                                  1
#define   VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__M                                  0x20
#define   VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__PRE                                0x20

#define   VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__B                                  6
#define   VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__W                                  1
#define   VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__M                                  0x40
#define   VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__PRE                                0x40

#define   VSB_TOP_SYSSMAGCCTRL_CKFRZ__B                                     7
#define   VSB_TOP_SYSSMAGCCTRL_CKFRZ__W                                     1
#define   VSB_TOP_SYSSMAGCCTRL_CKFRZ__M                                     0x80
#define   VSB_TOP_SYSSMAGCCTRL_CKFRZ__PRE                                   0x80

#define   VSB_TOP_SYSSMAGCCTRL_CKBWSW__B                                    8
#define   VSB_TOP_SYSSMAGCCTRL_CKBWSW__W                                    1
#define   VSB_TOP_SYSSMAGCCTRL_CKBWSW__M                                    0x100
#define   VSB_TOP_SYSSMAGCCTRL_CKBWSW__PRE                                  0x0

#define   VSB_TOP_SYSSMAGCCTRL_NCOBWSW__B                                   9
#define   VSB_TOP_SYSSMAGCCTRL_NCOBWSW__W                                   1
#define   VSB_TOP_SYSSMAGCCTRL_NCOBWSW__M                                   0x200
#define   VSB_TOP_SYSSMAGCCTRL_NCOBWSW__PRE                                 0x0

#define   VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__B                           10
#define   VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__W                           1
#define   VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__M                           0x400
#define   VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__PRE                         0x0

#define VSB_TOP_SYSSMCTCTRL__A                                              0x1C10037
#define VSB_TOP_SYSSMCTCTRL__W                                              11
#define VSB_TOP_SYSSMCTCTRL__M                                              0x7FF
#define VSB_TOP_SYSSMCTCTRL__PRE                                            0x4A

#define   VSB_TOP_SYSSMCTCTRL_RSTCTCAL__B                                   0
#define   VSB_TOP_SYSSMCTCTRL_RSTCTCAL__W                                   1
#define   VSB_TOP_SYSSMCTCTRL_RSTCTCAL__M                                   0x1
#define   VSB_TOP_SYSSMCTCTRL_RSTCTCAL__PRE                                 0x0

#define   VSB_TOP_SYSSMCTCTRL_CTCALEN__B                                    1
#define   VSB_TOP_SYSSMCTCTRL_CTCALEN__W                                    1
#define   VSB_TOP_SYSSMCTCTRL_CTCALEN__M                                    0x2
#define   VSB_TOP_SYSSMCTCTRL_CTCALEN__PRE                                  0x2

#define   VSB_TOP_SYSSMCTCTRL_STARTTRN__B                                   2
#define   VSB_TOP_SYSSMCTCTRL_STARTTRN__W                                   1
#define   VSB_TOP_SYSSMCTCTRL_STARTTRN__M                                   0x4
#define   VSB_TOP_SYSSMCTCTRL_STARTTRN__PRE                                 0x0

#define   VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__B                              3
#define   VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__W                              1
#define   VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__M                              0x8
#define   VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__PRE                            0x8

#define   VSB_TOP_SYSSMCTCTRL_RSTCYDET__B                                   4
#define   VSB_TOP_SYSSMCTCTRL_RSTCYDET__W                                   1
#define   VSB_TOP_SYSSMCTCTRL_RSTCYDET__M                                   0x10
#define   VSB_TOP_SYSSMCTCTRL_RSTCYDET__PRE                                 0x0

#define   VSB_TOP_SYSSMCTCTRL_RSTDCRMV__B                                   5
#define   VSB_TOP_SYSSMCTCTRL_RSTDCRMV__W                                   1
#define   VSB_TOP_SYSSMCTCTRL_RSTDCRMV__M                                   0x20
#define   VSB_TOP_SYSSMCTCTRL_RSTDCRMV__PRE                                 0x0

#define   VSB_TOP_SYSSMCTCTRL_RSTEQSIG__B                                   6
#define   VSB_TOP_SYSSMCTCTRL_RSTEQSIG__W                                   1
#define   VSB_TOP_SYSSMCTCTRL_RSTEQSIG__M                                   0x40
#define   VSB_TOP_SYSSMCTCTRL_RSTEQSIG__PRE                                 0x40

#define   VSB_TOP_SYSSMCTCTRL_CKFRZ__B                                      7
#define   VSB_TOP_SYSSMCTCTRL_CKFRZ__W                                      1
#define   VSB_TOP_SYSSMCTCTRL_CKFRZ__M                                      0x80
#define   VSB_TOP_SYSSMCTCTRL_CKFRZ__PRE                                    0x0

#define   VSB_TOP_SYSSMCTCTRL_CKBWSW__B                                     8
#define   VSB_TOP_SYSSMCTCTRL_CKBWSW__W                                     1
#define   VSB_TOP_SYSSMCTCTRL_CKBWSW__M                                     0x100
#define   VSB_TOP_SYSSMCTCTRL_CKBWSW__PRE                                   0x0

#define   VSB_TOP_SYSSMCTCTRL_NCOBWSW__B                                    9
#define   VSB_TOP_SYSSMCTCTRL_NCOBWSW__W                                    1
#define   VSB_TOP_SYSSMCTCTRL_NCOBWSW__M                                    0x200
#define   VSB_TOP_SYSSMCTCTRL_NCOBWSW__PRE                                  0x0

#define   VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__B                            10
#define   VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__W                            1
#define   VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__M                            0x400
#define   VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__PRE                          0x0

#define VSB_TOP_EQCTRL__A                                                   0x1C10038
#define VSB_TOP_EQCTRL__W                                                   10
#define VSB_TOP_EQCTRL__M                                                   0x3FF
#define VSB_TOP_EQCTRL__PRE                                                 0x6

#define   VSB_TOP_EQCTRL_STASSIGNEN__B                                      0
#define   VSB_TOP_EQCTRL_STASSIGNEN__W                                      1
#define   VSB_TOP_EQCTRL_STASSIGNEN__M                                      0x1
#define   VSB_TOP_EQCTRL_STASSIGNEN__PRE                                    0x0

#define   VSB_TOP_EQCTRL_ORCANCMAEN__B                                      1
#define   VSB_TOP_EQCTRL_ORCANCMAEN__W                                      1
#define   VSB_TOP_EQCTRL_ORCANCMAEN__M                                      0x2
#define   VSB_TOP_EQCTRL_ORCANCMAEN__PRE                                    0x2

#define   VSB_TOP_EQCTRL_ODAGCGO__B                                         2
#define   VSB_TOP_EQCTRL_ODAGCGO__W                                         1
#define   VSB_TOP_EQCTRL_ODAGCGO__M                                         0x4
#define   VSB_TOP_EQCTRL_ODAGCGO__PRE                                       0x4

#define   VSB_TOP_EQCTRL_OPTGAIN__B                                         3
#define   VSB_TOP_EQCTRL_OPTGAIN__W                                         3
#define   VSB_TOP_EQCTRL_OPTGAIN__M                                         0x38
#define   VSB_TOP_EQCTRL_OPTGAIN__PRE                                       0x0

#define   VSB_TOP_EQCTRL_TAPRAMWRTEN__B                                     6
#define   VSB_TOP_EQCTRL_TAPRAMWRTEN__W                                     1
#define   VSB_TOP_EQCTRL_TAPRAMWRTEN__M                                     0x40
#define   VSB_TOP_EQCTRL_TAPRAMWRTEN__PRE                                   0x0

#define   VSB_TOP_EQCTRL_CMAGAIN__B                                         7
#define   VSB_TOP_EQCTRL_CMAGAIN__W                                         3
#define   VSB_TOP_EQCTRL_CMAGAIN__M                                         0x380
#define   VSB_TOP_EQCTRL_CMAGAIN__PRE                                       0x0

#define VSB_TOP_PREEQAGCCTRL__A                                             0x1C10039
#define VSB_TOP_PREEQAGCCTRL__W                                             5
#define VSB_TOP_PREEQAGCCTRL__M                                             0x1F
#define VSB_TOP_PREEQAGCCTRL__PRE                                           0x10

#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__B                             0
#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__W                             4
#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__M                             0xF
#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__PRE                           0x0

#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__B                               4
#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__W                               1
#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__M                               0x10
#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__PRE                             0x10

#define VSB_TOP_PREEQAGCPWRREFLVLHI__A                                      0x1C1003A
#define VSB_TOP_PREEQAGCPWRREFLVLHI__W                                      8
#define VSB_TOP_PREEQAGCPWRREFLVLHI__M                                      0xFF
#define VSB_TOP_PREEQAGCPWRREFLVLHI__PRE                                    0x0

#define VSB_TOP_PREEQAGCPWRREFLVLLO__A                                      0x1C1003B
#define VSB_TOP_PREEQAGCPWRREFLVLLO__W                                      16
#define VSB_TOP_PREEQAGCPWRREFLVLLO__M                                      0xFFFF
#define VSB_TOP_PREEQAGCPWRREFLVLLO__PRE                                    0x1D66

#define VSB_TOP_CORINGSEL__A                                                0x1C1003C
#define VSB_TOP_CORINGSEL__W                                                8
#define VSB_TOP_CORINGSEL__M                                                0xFF
#define VSB_TOP_CORINGSEL__PRE                                              0x3
#define VSB_TOP_BEDETCTRL__A                                                0x1C1003D
#define VSB_TOP_BEDETCTRL__W                                                9
#define VSB_TOP_BEDETCTRL__M                                                0x1FF
#define VSB_TOP_BEDETCTRL__PRE                                              0x145

#define   VSB_TOP_BEDETCTRL_MIXRATIO__B                                     0
#define   VSB_TOP_BEDETCTRL_MIXRATIO__W                                     3
#define   VSB_TOP_BEDETCTRL_MIXRATIO__M                                     0x7
#define   VSB_TOP_BEDETCTRL_MIXRATIO__PRE                                   0x5

#define   VSB_TOP_BEDETCTRL_CYOFFSEL__B                                     3
#define   VSB_TOP_BEDETCTRL_CYOFFSEL__W                                     1
#define   VSB_TOP_BEDETCTRL_CYOFFSEL__M                                     0x8
#define   VSB_TOP_BEDETCTRL_CYOFFSEL__PRE                                   0x0

#define   VSB_TOP_BEDETCTRL_DATAOFFSEL__B                                   4
#define   VSB_TOP_BEDETCTRL_DATAOFFSEL__W                                   1
#define   VSB_TOP_BEDETCTRL_DATAOFFSEL__M                                   0x10
#define   VSB_TOP_BEDETCTRL_DATAOFFSEL__PRE                                 0x0

#define   VSB_TOP_BEDETCTRL_BYPASS_DSQ__B                                   5
#define   VSB_TOP_BEDETCTRL_BYPASS_DSQ__W                                   1
#define   VSB_TOP_BEDETCTRL_BYPASS_DSQ__M                                   0x20
#define   VSB_TOP_BEDETCTRL_BYPASS_DSQ__PRE                                 0x0

#define   VSB_TOP_BEDETCTRL_BYPASS_PSQ__B                                   6
#define   VSB_TOP_BEDETCTRL_BYPASS_PSQ__W                                   1
#define   VSB_TOP_BEDETCTRL_BYPASS_PSQ__M                                   0x40
#define   VSB_TOP_BEDETCTRL_BYPASS_PSQ__PRE                                 0x40

#define   VSB_TOP_BEDETCTRL_BYPASS_CSQ__B                                   7
#define   VSB_TOP_BEDETCTRL_BYPASS_CSQ__W                                   1
#define   VSB_TOP_BEDETCTRL_BYPASS_CSQ__M                                   0x80
#define   VSB_TOP_BEDETCTRL_BYPASS_CSQ__PRE                                 0x0

#define   VSB_TOP_BEDETCTRL_BYPASS_DMP__B                                   8
#define   VSB_TOP_BEDETCTRL_BYPASS_DMP__W                                   1
#define   VSB_TOP_BEDETCTRL_BYPASS_DMP__M                                   0x100
#define   VSB_TOP_BEDETCTRL_BYPASS_DMP__PRE                                 0x100

#define VSB_TOP_LBAGCREFLVL__A                                              0x1C1003E
#define VSB_TOP_LBAGCREFLVL__W                                              12
#define VSB_TOP_LBAGCREFLVL__M                                              0xFFF
#define VSB_TOP_LBAGCREFLVL__PRE                                            0x200

#define VSB_TOP_UBAGCREFLVL__A                                              0x1C1003F
#define VSB_TOP_UBAGCREFLVL__W                                              12
#define VSB_TOP_UBAGCREFLVL__M                                              0xFFF
#define VSB_TOP_UBAGCREFLVL__PRE                                            0x400

#define VSB_TOP_NOTCH1_BIN_NUM__A                                           0x1C10040
#define VSB_TOP_NOTCH1_BIN_NUM__W                                           11
#define VSB_TOP_NOTCH1_BIN_NUM__M                                           0x7FF
#define VSB_TOP_NOTCH1_BIN_NUM__PRE                                         0xB2

#define VSB_TOP_NOTCH2_BIN_NUM__A                                           0x1C10041
#define VSB_TOP_NOTCH2_BIN_NUM__W                                           11
#define VSB_TOP_NOTCH2_BIN_NUM__M                                           0x7FF
#define VSB_TOP_NOTCH2_BIN_NUM__PRE                                         0x40B

#define VSB_TOP_NOTCH_START_BIN_NUM__A                                      0x1C10042
#define VSB_TOP_NOTCH_START_BIN_NUM__W                                      11
#define VSB_TOP_NOTCH_START_BIN_NUM__M                                      0x7FF
#define VSB_TOP_NOTCH_START_BIN_NUM__PRE                                    0x7C0

#define VSB_TOP_NOTCH_STOP_BIN_NUM__A                                       0x1C10043
#define VSB_TOP_NOTCH_STOP_BIN_NUM__W                                       11
#define VSB_TOP_NOTCH_STOP_BIN_NUM__M                                       0x7FF
#define VSB_TOP_NOTCH_STOP_BIN_NUM__PRE                                     0x43F

#define VSB_TOP_NOTCH_TEST_DURATION__A                                      0x1C10044
#define VSB_TOP_NOTCH_TEST_DURATION__W                                      11
#define VSB_TOP_NOTCH_TEST_DURATION__M                                      0x7FF
#define VSB_TOP_NOTCH_TEST_DURATION__PRE                                    0x7FF

#define VSB_TOP_RESULT_LARGE_PEAK_BIN__A                                    0x1C10045
#define VSB_TOP_RESULT_LARGE_PEAK_BIN__W                                    11
#define VSB_TOP_RESULT_LARGE_PEAK_BIN__M                                    0x7FF
#define VSB_TOP_RESULT_LARGE_PEAK_BIN__PRE                                  0x0

#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__A                                  0x1C10046
#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__W                                  16
#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__M                                  0xFFFF
#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__PRE                                0x0

#define VSB_TOP_RESULT_SMALL_PEAK_BIN__A                                    0x1C10047
#define VSB_TOP_RESULT_SMALL_PEAK_BIN__W                                    11
#define VSB_TOP_RESULT_SMALL_PEAK_BIN__M                                    0x7FF
#define VSB_TOP_RESULT_SMALL_PEAK_BIN__PRE                                  0x0

#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__A                                  0x1C10048
#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__W                                  16
#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__M                                  0xFFFF
#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__PRE                                0x0

#define VSB_TOP_NOTCH_SWEEP_RUNNING__A                                      0x1C10049
#define VSB_TOP_NOTCH_SWEEP_RUNNING__W                                      1
#define VSB_TOP_NOTCH_SWEEP_RUNNING__M                                      0x1
#define VSB_TOP_NOTCH_SWEEP_RUNNING__PRE                                    0x0

#define VSB_TOP_PREEQDAGCRATIO__A                                           0x1C1004A
#define VSB_TOP_PREEQDAGCRATIO__W                                           13
#define VSB_TOP_PREEQDAGCRATIO__M                                           0x1FFF
#define VSB_TOP_PREEQDAGCRATIO__PRE                                         0x0
#define VSB_TOP_AGC_TRUNCCTRL__A                                            0x1C1004B
#define VSB_TOP_AGC_TRUNCCTRL__W                                            4
#define VSB_TOP_AGC_TRUNCCTRL__M                                            0xF
#define VSB_TOP_AGC_TRUNCCTRL__PRE                                          0xF

#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__B                                0
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__W                                2
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__M                                0x3
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__PRE                              0x3

#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__B                                2
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__W                                1
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__M                                0x4
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__PRE                              0x4

#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__B                                 3
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__W                                 1
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__M                                 0x8
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__PRE                               0x8

#define VSB_TOP_BEAGC_DEADZONEINIT__A                                       0x1C1004C
#define VSB_TOP_BEAGC_DEADZONEINIT__W                                       8
#define VSB_TOP_BEAGC_DEADZONEINIT__M                                       0xFF
#define VSB_TOP_BEAGC_DEADZONEINIT__PRE                                     0x50

#define VSB_TOP_BEAGC_REFLEVEL__A                                           0x1C1004D
#define VSB_TOP_BEAGC_REFLEVEL__W                                           9
#define VSB_TOP_BEAGC_REFLEVEL__M                                           0x1FF
#define VSB_TOP_BEAGC_REFLEVEL__PRE                                         0xAE

#define VSB_TOP_BEAGC_GAINSHIFT__A                                          0x1C1004E
#define VSB_TOP_BEAGC_GAINSHIFT__W                                          3
#define VSB_TOP_BEAGC_GAINSHIFT__M                                          0x7
#define VSB_TOP_BEAGC_GAINSHIFT__PRE                                        0x3

#define VSB_TOP_BEAGC_REGINIT__A                                            0x1C1004F
#define VSB_TOP_BEAGC_REGINIT__W                                            15
#define VSB_TOP_BEAGC_REGINIT__M                                            0x7FFF
#define VSB_TOP_BEAGC_REGINIT__PRE                                          0x40

#define   VSB_TOP_BEAGC_REGINIT_BEAGC_RST__B                                14
#define   VSB_TOP_BEAGC_REGINIT_BEAGC_RST__W                                1
#define   VSB_TOP_BEAGC_REGINIT_BEAGC_RST__M                                0x4000
#define   VSB_TOP_BEAGC_REGINIT_BEAGC_RST__PRE                              0x0

#define VSB_TOP_BEAGC_SCALE__A                                              0x1C10050
#define VSB_TOP_BEAGC_SCALE__W                                              14
#define VSB_TOP_BEAGC_SCALE__M                                              0x3FFF
#define VSB_TOP_BEAGC_SCALE__PRE                                            0x0

#define VSB_TOP_CFAGC_DEADZONEINIT__A                                       0x1C10051
#define VSB_TOP_CFAGC_DEADZONEINIT__W                                       8
#define VSB_TOP_CFAGC_DEADZONEINIT__M                                       0xFF
#define VSB_TOP_CFAGC_DEADZONEINIT__PRE                                     0x50

#define VSB_TOP_CFAGC_REFLEVEL__A                                           0x1C10052
#define VSB_TOP_CFAGC_REFLEVEL__W                                           9
#define VSB_TOP_CFAGC_REFLEVEL__M                                           0x1FF
#define VSB_TOP_CFAGC_REFLEVEL__PRE                                         0xAE

#define VSB_TOP_CFAGC_GAINSHIFT__A                                          0x1C10053
#define VSB_TOP_CFAGC_GAINSHIFT__W                                          3
#define VSB_TOP_CFAGC_GAINSHIFT__M                                          0x7
#define VSB_TOP_CFAGC_GAINSHIFT__PRE                                        0x3

#define VSB_TOP_CFAGC_REGINIT__A                                            0x1C10054
#define VSB_TOP_CFAGC_REGINIT__W                                            15
#define VSB_TOP_CFAGC_REGINIT__M                                            0x7FFF
#define VSB_TOP_CFAGC_REGINIT__PRE                                          0x80

#define   VSB_TOP_CFAGC_REGINIT_CFAGC_RST__B                                14
#define   VSB_TOP_CFAGC_REGINIT_CFAGC_RST__W                                1
#define   VSB_TOP_CFAGC_REGINIT_CFAGC_RST__M                                0x4000
#define   VSB_TOP_CFAGC_REGINIT_CFAGC_RST__PRE                              0x0

#define VSB_TOP_CFAGC_SCALE__A                                              0x1C10055
#define VSB_TOP_CFAGC_SCALE__W                                              14
#define VSB_TOP_CFAGC_SCALE__M                                              0x3FFF
#define VSB_TOP_CFAGC_SCALE__PRE                                            0x0

#define VSB_TOP_CKTRKONCTL__A                                               0x1C10056
#define VSB_TOP_CKTRKONCTL__W                                               2
#define VSB_TOP_CKTRKONCTL__M                                               0x3
#define VSB_TOP_CKTRKONCTL__PRE                                             0x0

#define VSB_TOP_CYTRKONCTL__A                                               0x1C10057
#define VSB_TOP_CYTRKONCTL__W                                               2
#define VSB_TOP_CYTRKONCTL__M                                               0x3
#define VSB_TOP_CYTRKONCTL__PRE                                             0x0

#define VSB_TOP_PTONCTL__A                                                  0x1C10058
#define VSB_TOP_PTONCTL__W                                                  2
#define VSB_TOP_PTONCTL__M                                                  0x3
#define VSB_TOP_PTONCTL__PRE                                                0x0

#define VSB_TOP_NOTCH_SCALE_1__A                                            0x1C10059
#define VSB_TOP_NOTCH_SCALE_1__W                                            8
#define VSB_TOP_NOTCH_SCALE_1__M                                            0xFF
#define VSB_TOP_NOTCH_SCALE_1__PRE                                          0xA

#define VSB_TOP_NOTCH_SCALE_2__A                                            0x1C1005A
#define VSB_TOP_NOTCH_SCALE_2__W                                            8
#define VSB_TOP_NOTCH_SCALE_2__M                                            0xFF
#define VSB_TOP_NOTCH_SCALE_2__PRE                                          0xA

#define VSB_TOP_FIRSTLARGFFETAP__A                                          0x1C1005B
#define VSB_TOP_FIRSTLARGFFETAP__W                                          12
#define VSB_TOP_FIRSTLARGFFETAP__M                                          0xFFF
#define VSB_TOP_FIRSTLARGFFETAP__PRE                                        0x0

#define VSB_TOP_FIRSTLARGFFETAPADDR__A                                      0x1C1005C
#define VSB_TOP_FIRSTLARGFFETAPADDR__W                                      11
#define VSB_TOP_FIRSTLARGFFETAPADDR__M                                      0x7FF
#define VSB_TOP_FIRSTLARGFFETAPADDR__PRE                                    0x0

#define VSB_TOP_SECONDLARGFFETAP__A                                         0x1C1005D
#define VSB_TOP_SECONDLARGFFETAP__W                                         12
#define VSB_TOP_SECONDLARGFFETAP__M                                         0xFFF
#define VSB_TOP_SECONDLARGFFETAP__PRE                                       0x0

#define VSB_TOP_SECONDLARGFFETAPADDR__A                                     0x1C1005E
#define VSB_TOP_SECONDLARGFFETAPADDR__W                                     11
#define VSB_TOP_SECONDLARGFFETAPADDR__M                                     0x7FF
#define VSB_TOP_SECONDLARGFFETAPADDR__PRE                                   0x0

#define VSB_TOP_FIRSTLARGDFETAP__A                                          0x1C1005F
#define VSB_TOP_FIRSTLARGDFETAP__W                                          12
#define VSB_TOP_FIRSTLARGDFETAP__M                                          0xFFF
#define VSB_TOP_FIRSTLARGDFETAP__PRE                                        0x0

#define VSB_TOP_FIRSTLARGDFETAPADDR__A                                      0x1C10060
#define VSB_TOP_FIRSTLARGDFETAPADDR__W                                      11
#define VSB_TOP_FIRSTLARGDFETAPADDR__M                                      0x7FF
#define VSB_TOP_FIRSTLARGDFETAPADDR__PRE                                    0x0

#define VSB_TOP_SECONDLARGDFETAP__A                                         0x1C10061
#define VSB_TOP_SECONDLARGDFETAP__W                                         12
#define VSB_TOP_SECONDLARGDFETAP__M                                         0xFFF
#define VSB_TOP_SECONDLARGDFETAP__PRE                                       0x0

#define VSB_TOP_SECONDLARGDFETAPADDR__A                                     0x1C10062
#define VSB_TOP_SECONDLARGDFETAPADDR__W                                     11
#define VSB_TOP_SECONDLARGDFETAPADDR__M                                     0x7FF
#define VSB_TOP_SECONDLARGDFETAPADDR__PRE                                   0x0

#define VSB_TOP_PARAOWDBUS__A                                               0x1C10063
#define VSB_TOP_PARAOWDBUS__W                                               12
#define VSB_TOP_PARAOWDBUS__M                                               0xFFF
#define VSB_TOP_PARAOWDBUS__PRE                                             0x0
#define VSB_TOP_PARAOWCTRL__A                                               0x1C10064
#define VSB_TOP_PARAOWCTRL__W                                               7
#define VSB_TOP_PARAOWCTRL__M                                               0x7F
#define VSB_TOP_PARAOWCTRL__PRE                                             0x0

#define   VSB_TOP_PARAOWCTRL_PARAOWABUS__B                                  0
#define   VSB_TOP_PARAOWCTRL_PARAOWABUS__W                                  6
#define   VSB_TOP_PARAOWCTRL_PARAOWABUS__M                                  0x3F
#define   VSB_TOP_PARAOWCTRL_PARAOWABUS__PRE                                0x0

#define   VSB_TOP_PARAOWCTRL_PARAOWEN__B                                    6
#define   VSB_TOP_PARAOWCTRL_PARAOWEN__W                                    1
#define   VSB_TOP_PARAOWCTRL_PARAOWEN__M                                    0x40
#define   VSB_TOP_PARAOWCTRL_PARAOWEN__PRE                                  0x0

#define VSB_TOP_CURRENTSEGLOCAT__A                                          0x1C10065
#define VSB_TOP_CURRENTSEGLOCAT__W                                          10
#define VSB_TOP_CURRENTSEGLOCAT__M                                          0x3FF
#define VSB_TOP_CURRENTSEGLOCAT__PRE                                        0x0

#define VSB_TOP_MEASUREMENT_PERIOD__A                                       0x1C10066
#define VSB_TOP_MEASUREMENT_PERIOD__W                                       16
#define VSB_TOP_MEASUREMENT_PERIOD__M                                       0xFFFF
#define VSB_TOP_MEASUREMENT_PERIOD__PRE                                     0x0

#define VSB_TOP_NR_SYM_ERRS__A                                              0x1C10067
#define VSB_TOP_NR_SYM_ERRS__W                                              16
#define VSB_TOP_NR_SYM_ERRS__M                                              0xFFFF
#define VSB_TOP_NR_SYM_ERRS__PRE                                            0xFFFF

#define VSB_TOP_ERR_ENERGY_L__A                                             0x1C10068
#define VSB_TOP_ERR_ENERGY_L__W                                             16
#define VSB_TOP_ERR_ENERGY_L__M                                             0xFFFF
#define VSB_TOP_ERR_ENERGY_L__PRE                                           0xFFFF

#define VSB_TOP_ERR_ENERGY_H__A                                             0x1C10069
#define VSB_TOP_ERR_ENERGY_H__W                                             16
#define VSB_TOP_ERR_ENERGY_H__M                                             0xFFFF
#define VSB_TOP_ERR_ENERGY_H__PRE                                           0xFFFF

#define VSB_TOP_SLICER_SEL_8LEV__A                                          0x1C1006A
#define VSB_TOP_SLICER_SEL_8LEV__W                                          1
#define VSB_TOP_SLICER_SEL_8LEV__M                                          0x1
#define VSB_TOP_SLICER_SEL_8LEV__PRE                                        0x1

#define VSB_TOP_BNFIELD__A                                                  0x1C1006B
#define VSB_TOP_BNFIELD__W                                                  3
#define VSB_TOP_BNFIELD__M                                                  0x7
#define VSB_TOP_BNFIELD__PRE                                                0x3

#define VSB_TOP_CLPLASTNUM__A                                               0x1C1006C
#define VSB_TOP_CLPLASTNUM__W                                               8
#define VSB_TOP_CLPLASTNUM__M                                               0xFF
#define VSB_TOP_CLPLASTNUM__PRE                                             0x0

#define VSB_TOP_BNSQERR__A                                                  0x1C1006D
#define VSB_TOP_BNSQERR__W                                                  16
#define VSB_TOP_BNSQERR__M                                                  0xFFFF
#define VSB_TOP_BNSQERR__PRE                                                0x1AD

#define VSB_TOP_BNTHRESH__A                                                 0x1C1006E
#define VSB_TOP_BNTHRESH__W                                                 9
#define VSB_TOP_BNTHRESH__M                                                 0x1FF
#define VSB_TOP_BNTHRESH__PRE                                               0x120

#define VSB_TOP_BNCLPNUM__A                                                 0x1C1006F
#define VSB_TOP_BNCLPNUM__W                                                 16
#define VSB_TOP_BNCLPNUM__M                                                 0xFFFF
#define VSB_TOP_BNCLPNUM__PRE                                               0x0
#define VSB_TOP_PHASELOCKCTRL__A                                            0x1C10070
#define VSB_TOP_PHASELOCKCTRL__W                                            7
#define VSB_TOP_PHASELOCKCTRL__M                                            0x7F
#define VSB_TOP_PHASELOCKCTRL__PRE                                          0x0

#define   VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__B                           0
#define   VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__W                           1
#define   VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__M                           0x1
#define   VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__PRE                         0x0

#define   VSB_TOP_PHASELOCKCTRL_DFORCEPLL__B                                1
#define   VSB_TOP_PHASELOCKCTRL_DFORCEPLL__W                                1
#define   VSB_TOP_PHASELOCKCTRL_DFORCEPLL__M                                0x2
#define   VSB_TOP_PHASELOCKCTRL_DFORCEPLL__PRE                              0x0

#define   VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__B                           2
#define   VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__W                           1
#define   VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__M                           0x4
#define   VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__PRE                         0x0

#define   VSB_TOP_PHASELOCKCTRL_PFORCEPLL__B                                3
#define   VSB_TOP_PHASELOCKCTRL_PFORCEPLL__W                                1
#define   VSB_TOP_PHASELOCKCTRL_PFORCEPLL__M                                0x8
#define   VSB_TOP_PHASELOCKCTRL_PFORCEPLL__PRE                              0x0

#define   VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__B                           4
#define   VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__W                           1
#define   VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__M                           0x10
#define   VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__PRE                         0x0

#define   VSB_TOP_PHASELOCKCTRL_CFORCEPLL__B                                5
#define   VSB_TOP_PHASELOCKCTRL_CFORCEPLL__W                                1
#define   VSB_TOP_PHASELOCKCTRL_CFORCEPLL__M                                0x20
#define   VSB_TOP_PHASELOCKCTRL_CFORCEPLL__PRE                              0x0

#define   VSB_TOP_PHASELOCKCTRL_IQSWITCH__B                                 6
#define   VSB_TOP_PHASELOCKCTRL_IQSWITCH__W                                 1
#define   VSB_TOP_PHASELOCKCTRL_IQSWITCH__M                                 0x40
#define   VSB_TOP_PHASELOCKCTRL_IQSWITCH__PRE                               0x0

#define VSB_TOP_DLOCKACCUM__A                                               0x1C10071
#define VSB_TOP_DLOCKACCUM__W                                               16
#define VSB_TOP_DLOCKACCUM__M                                               0xFFFF
#define VSB_TOP_DLOCKACCUM__PRE                                             0x0

#define VSB_TOP_PLOCKACCUM__A                                               0x1C10072
#define VSB_TOP_PLOCKACCUM__W                                               16
#define VSB_TOP_PLOCKACCUM__M                                               0xFFFF
#define VSB_TOP_PLOCKACCUM__PRE                                             0x0

#define VSB_TOP_CLOCKACCUM__A                                               0x1C10073
#define VSB_TOP_CLOCKACCUM__W                                               16
#define VSB_TOP_CLOCKACCUM__M                                               0xFFFF
#define VSB_TOP_CLOCKACCUM__PRE                                             0x0

#define VSB_TOP_DCRMVACUMI__A                                               0x1C10074
#define VSB_TOP_DCRMVACUMI__W                                               10
#define VSB_TOP_DCRMVACUMI__M                                               0x3FF
#define VSB_TOP_DCRMVACUMI__PRE                                             0x0

#define VSB_TOP_DCRMVACUMQ__A                                               0x1C10075
#define VSB_TOP_DCRMVACUMQ__W                                               10
#define VSB_TOP_DCRMVACUMQ__M                                               0x3FF
#define VSB_TOP_DCRMVACUMQ__PRE                                             0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A                                0x1C20000
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__A                                0x1C20001
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__A                                0x1C20002
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__A                                0x1C20003
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__A                                0x1C20004
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__A                                0x1C20005
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__A                                0x1C20006
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__A                                0x1C20007
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__A                                0x1C20008
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__A                               0x1C20009
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__W                               12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__M                               0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__PRE                             0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__A                               0x1C2000A
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__W                               12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__M                               0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__PRE                             0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__A                               0x1C2000B
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__W                               12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__M                               0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__PRE                             0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__A                            0x1C2000C
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__A                            0x1C2000D
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__A                            0x1C2000E
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__A                            0x1C2000F
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__A                            0x1C20010
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__A                            0x1C20011
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__A                            0x1C20012
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__A                            0x1C20013
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__A                            0x1C20014
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__A                           0x1C20015
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__W                           12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__A                           0x1C20016
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__W                           12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__A                           0x1C20017
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__W                           12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__A                             0x1C20018
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__A                             0x1C20019
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__A                             0x1C2001A
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__A                             0x1C2001B
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__A                             0x1C2001C
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__A                             0x1C2001D
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__A                             0x1C2001E
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__A                             0x1C2001F
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__A                             0x1C20020
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__A                            0x1C20021
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__A                            0x1C20022
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__A                            0x1C20023
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__A                            0x1C20024
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__A                            0x1C20025
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__A                            0x1C20026
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__A                            0x1C20027
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__A                            0x1C20028
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__A                            0x1C20029
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__A                            0x1C2002A
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__A                            0x1C2002B
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__A                            0x1C2002C
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__A                           0x1C2002D
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__W                           12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__A                           0x1C2002E
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__W                           12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__A                           0x1C2002F
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__W                           12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__A                             0x1C20030
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__A                             0x1C20031
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__A                             0x1C20032
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__A                             0x1C20033
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__A                             0x1C20034
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__A                             0x1C20035
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__A                             0x1C20036
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__A                             0x1C20037
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__A                             0x1C20038
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__A                            0x1C20039
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__A                            0x1C2003A
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__A                            0x1C2003B
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__A                            0x1C2003C
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__A                            0x1C2003D
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__A                            0x1C2003E
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__A                            0x1C2003F
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__A                            0x1C20040
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__A                            0x1C20041
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__A                            0x1C20042
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__A                            0x1C20043
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__A                            0x1C20044
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__A                           0x1C20045
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__W                           12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__A                           0x1C20046
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__W                           12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__A                           0x1C20047
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__W                           12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__A                             0x1C20048
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__A                             0x1C20049
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__A                             0x1C2004A
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__A                             0x1C2004B
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__A                             0x1C2004C
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__A                             0x1C2004D
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__A                             0x1C2004E
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__A                             0x1C2004F
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__A                             0x1C20050
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__A                            0x1C20051
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__A                            0x1C20052
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__A                            0x1C20053
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__A                            0x1C20054
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__A                            0x1C20055
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__A                            0x1C20056
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__A                            0x1C20057
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__A                            0x1C20058
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__A                            0x1C20059
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__A                            0x1C2005A
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__A                            0x1C2005B
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__A                            0x1C2005C
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__A                           0x1C2005D
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__W                           12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__A                           0x1C2005E
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__W                           12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__A                           0x1C2005F
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__W                           12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__A                             0x1C20060
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__A                             0x1C20061
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__A                             0x1C20062
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__A                             0x1C20063
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__A                             0x1C20064
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__A                             0x1C20065
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__A                             0x1C20066
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__A                             0x1C20067
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__A                             0x1C20068
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__A                            0x1C20069
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__A                            0x1C2006A
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__A                            0x1C2006B
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__A                                   0x1C2006C
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__A                                   0x1C2006D
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__A                                   0x1C2006E
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__A                                   0x1C2006F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__A                                   0x1C20070
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__A                                   0x1C20071
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__A                                   0x1C20072
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__A                                   0x1C20073
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__A                                   0x1C20074
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__A                                  0x1C20075
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__W                                  7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__M                                  0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__PRE                                0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__A                                  0x1C20076
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__W                                  7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__M                                  0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__PRE                                0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__A                                  0x1C20077
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__W                                  7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__M                                  0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__PRE                                0x0
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__A                                    0x1C20078
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__PRE               0x0

#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__A                                    0x1C20079
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__PRE               0x0

#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__A                                    0x1C2007A
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__PRE               0x0

#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__A                                    0x1C2007B
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__PRE               0x0

#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__A                                    0x1C2007C
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__PRE               0x0

#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__A                                    0x1C2007D
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__PRE               0x0

#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__A                                    0x1C2007E
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__PRE               0x0

#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__A                                    0x1C2007F
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A                                    0x1C30000
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__A                                   0x1C30001
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__W                                   15
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__B              0
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__W              7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__B               8
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__W               7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__A                                   0x1C30002
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__W                                   15
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__B              0
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__W              7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__B               8
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__W               7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__A                                   0x1C30003
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__W                                   15
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__B              0
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__W              7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__B               8
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__W               7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__A                                    0x1C30004
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__A                                    0x1C30005
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__A                                    0x1C30006
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__A                                    0x1C30007
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__A                                    0x1C30008
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__A                                    0x1C30009
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__A                                    0x1C3000A
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__A                                    0x1C3000B
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__A                                    0x1C3000C
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__A                                   0x1C3000D
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__W                                   15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__B              0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__W              7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__B               8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__W               7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__A                                   0x1C3000E
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__W                                   15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__B              0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__W              7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__B               8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__W               7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__A                                   0x1C3000F
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__W                                   15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__B              0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__W              7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__B               8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__W               7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__A                                    0x1C30010
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__A                                    0x1C30011
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__A                                    0x1C30012
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__A                                    0x1C30013
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__A                                    0x1C30014
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__A                                    0x1C30015
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__A                                    0x1C30016
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__A                                    0x1C30017
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__A                                    0x1C30018
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__A                                   0x1C30019
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__W                                   15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__B              0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__W              7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__B               8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__W               7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__A                                   0x1C3001A
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__W                                   15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__B              0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__W              7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__B               8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__W               7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__A                                   0x1C3001B
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__W                                   15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__B              0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__W              7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__B               8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__W               7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__A                                    0x1C3001C
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__A                                    0x1C3001D
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__A                                    0x1C3001E
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__A                                    0x1C3001F
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__A                                    0x1C30020
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__A                                    0x1C30021
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__A                                    0x1C30022
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__A                                    0x1C30023
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__A                                    0x1C30024
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__A                                   0x1C30025
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__W                                   15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__B              0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__W              7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__B               8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__W               7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__A                                   0x1C30026
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__W                                   15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__B              0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__W              7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__B               8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__W               7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__A                                   0x1C30027
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__W                                   15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__B              0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__W              7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__B               8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__W               7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__PRE             0x0

#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__A                                 0x1C30028
#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__W                                 12
#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__M                                 0xFFF
#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__PRE                               0x0

#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__A                             0x1C30029
#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__W                             12
#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__M                             0xFFF
#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__PRE                           0x0

#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__A                              0x1C3002A
#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__W                              12
#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__M                              0xFFF
#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__PRE                            0x0

#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__A                             0x1C3002B
#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__W                             12
#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__M                             0xFFF
#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__PRE                           0x0

#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__A                              0x1C3002C
#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__W                              12
#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__M                              0xFFF
#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__PRE                            0x0

#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__A                             0x1C3002D
#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__W                             12
#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__M                             0xFFF
#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__PRE                           0x0

#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__A                              0x1C3002E
#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__W                              12
#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__M                              0xFFF
#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__PRE                            0x0

#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__A                             0x1C3002F
#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__W                             12
#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__M                             0xFFF
#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__PRE                           0x0

#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__A                              0x1C30030
#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__W                              12
#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__M                              0xFFF
#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__PRE                            0x0

#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__A                                    0x1C30031
#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__W                                    7
#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__M                                    0x7F
#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__PRE                                  0x0
#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__A                                     0x1C30032
#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__W                                     15
#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__M                                     0x7FFF
#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__PRE                                   0x0

#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__B                  0
#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__W                  7
#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__M                  0x7F
#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__PRE                0x0

#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__B                   8
#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__W                   7
#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__M                   0x7F00
#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__PRE                 0x0

#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__A                                     0x1C30033
#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__W                                     15
#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__M                                     0x7FFF
#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__PRE                                   0x0

#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__B                  0
#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__W                  7
#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__M                  0x7F
#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__PRE                0x0

#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__B                   8
#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__W                   7
#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__M                   0x7F00
#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__PRE                 0x0

#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__A                                     0x1C30034
#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__W                                     15
#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__M                                     0x7FFF
#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__PRE                                   0x0

#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__B                  0
#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__W                  7
#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__M                  0x7F
#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__PRE                0x0

#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__B                   8
#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__W                   7
#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__M                   0x7F00
#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__PRE                 0x0

#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__A                                     0x1C30035
#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__W                                     15
#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__M                                     0x7FFF
#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__PRE                                   0x0

#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__B                  0
#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__W                  7
#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__M                  0x7F
#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__PRE                0x0

#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__B                   8
#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__W                   7
#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__M                   0x7F00
#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__PRE                 0x0

#define VSB_TCMEQ_RAM__A                                                    0x1C40000

#define   VSB_TCMEQ_RAM_TCMEQ_RAM__B                                        0
#define   VSB_TCMEQ_RAM_TCMEQ_RAM__W                                        16
#define   VSB_TCMEQ_RAM_TCMEQ_RAM__M                                        0xFFFF
#define   VSB_TCMEQ_RAM_TCMEQ_RAM__PRE                                      0x0

#define VSB_FCPRE_RAM__A                                                    0x1C50000

#define   VSB_FCPRE_RAM_FCPRE_RAM__B                                        0
#define   VSB_FCPRE_RAM_FCPRE_RAM__W                                        16
#define   VSB_FCPRE_RAM_FCPRE_RAM__M                                        0xFFFF
#define   VSB_FCPRE_RAM_FCPRE_RAM__PRE                                      0x0

#define VSB_EQTAP_RAM__A                                                    0x1C60000

#define   VSB_EQTAP_RAM_EQTAP_RAM__B                                        0
#define   VSB_EQTAP_RAM_EQTAP_RAM__W                                        12
#define   VSB_EQTAP_RAM_EQTAP_RAM__M                                        0xFFF
#define   VSB_EQTAP_RAM_EQTAP_RAM__PRE                                      0x0

#endif