cvmx-spxx-defs.h
12.9 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
/***********************license start***************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2012 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
#ifndef __CVMX_SPXX_DEFS_H__
#define __CVMX_SPXX_DEFS_H__
#define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull)
union cvmx_spxx_bckprs_cnt {
uint64_t u64;
struct cvmx_spxx_bckprs_cnt_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t cnt:32;
#else
uint64_t cnt:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_spxx_bckprs_cnt_s cn38xx;
struct cvmx_spxx_bckprs_cnt_s cn38xxp2;
struct cvmx_spxx_bckprs_cnt_s cn58xx;
struct cvmx_spxx_bckprs_cnt_s cn58xxp1;
};
union cvmx_spxx_bist_stat {
uint64_t u64;
struct cvmx_spxx_bist_stat_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63:61;
uint64_t stat2:1;
uint64_t stat1:1;
uint64_t stat0:1;
#else
uint64_t stat0:1;
uint64_t stat1:1;
uint64_t stat2:1;
uint64_t reserved_3_63:61;
#endif
} s;
struct cvmx_spxx_bist_stat_s cn38xx;
struct cvmx_spxx_bist_stat_s cn38xxp2;
struct cvmx_spxx_bist_stat_s cn58xx;
struct cvmx_spxx_bist_stat_s cn58xxp1;
};
union cvmx_spxx_clk_ctl {
uint64_t u64;
struct cvmx_spxx_clk_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63:47;
uint64_t seetrn:1;
uint64_t reserved_12_15:4;
uint64_t clkdly:5;
uint64_t runbist:1;
uint64_t statdrv:1;
uint64_t statrcv:1;
uint64_t sndtrn:1;
uint64_t drptrn:1;
uint64_t rcvtrn:1;
uint64_t srxdlck:1;
#else
uint64_t srxdlck:1;
uint64_t rcvtrn:1;
uint64_t drptrn:1;
uint64_t sndtrn:1;
uint64_t statrcv:1;
uint64_t statdrv:1;
uint64_t runbist:1;
uint64_t clkdly:5;
uint64_t reserved_12_15:4;
uint64_t seetrn:1;
uint64_t reserved_17_63:47;
#endif
} s;
struct cvmx_spxx_clk_ctl_s cn38xx;
struct cvmx_spxx_clk_ctl_s cn38xxp2;
struct cvmx_spxx_clk_ctl_s cn58xx;
struct cvmx_spxx_clk_ctl_s cn58xxp1;
};
union cvmx_spxx_clk_stat {
uint64_t u64;
struct cvmx_spxx_clk_stat_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63:53;
uint64_t stxcal:1;
uint64_t reserved_9_9:1;
uint64_t srxtrn:1;
uint64_t s4clk1:1;
uint64_t s4clk0:1;
uint64_t d4clk1:1;
uint64_t d4clk0:1;
uint64_t reserved_0_3:4;
#else
uint64_t reserved_0_3:4;
uint64_t d4clk0:1;
uint64_t d4clk1:1;
uint64_t s4clk0:1;
uint64_t s4clk1:1;
uint64_t srxtrn:1;
uint64_t reserved_9_9:1;
uint64_t stxcal:1;
uint64_t reserved_11_63:53;
#endif
} s;
struct cvmx_spxx_clk_stat_s cn38xx;
struct cvmx_spxx_clk_stat_s cn38xxp2;
struct cvmx_spxx_clk_stat_s cn58xx;
struct cvmx_spxx_clk_stat_s cn58xxp1;
};
union cvmx_spxx_dbg_deskew_ctl {
uint64_t u64;
struct cvmx_spxx_dbg_deskew_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_30_63:34;
uint64_t fallnop:1;
uint64_t fall8:1;
uint64_t reserved_26_27:2;
uint64_t sstep_go:1;
uint64_t sstep:1;
uint64_t reserved_22_23:2;
uint64_t clrdly:1;
uint64_t dec:1;
uint64_t inc:1;
uint64_t mux:1;
uint64_t offset:5;
uint64_t bitsel:5;
uint64_t offdly:6;
uint64_t dllfrc:1;
uint64_t dlldis:1;
#else
uint64_t dlldis:1;
uint64_t dllfrc:1;
uint64_t offdly:6;
uint64_t bitsel:5;
uint64_t offset:5;
uint64_t mux:1;
uint64_t inc:1;
uint64_t dec:1;
uint64_t clrdly:1;
uint64_t reserved_22_23:2;
uint64_t sstep:1;
uint64_t sstep_go:1;
uint64_t reserved_26_27:2;
uint64_t fall8:1;
uint64_t fallnop:1;
uint64_t reserved_30_63:34;
#endif
} s;
struct cvmx_spxx_dbg_deskew_ctl_s cn38xx;
struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2;
struct cvmx_spxx_dbg_deskew_ctl_s cn58xx;
struct cvmx_spxx_dbg_deskew_ctl_s cn58xxp1;
};
union cvmx_spxx_dbg_deskew_state {
uint64_t u64;
struct cvmx_spxx_dbg_deskew_state_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
uint64_t testres:1;
uint64_t unxterm:1;
uint64_t muxsel:2;
uint64_t offset:5;
#else
uint64_t offset:5;
uint64_t muxsel:2;
uint64_t unxterm:1;
uint64_t testres:1;
uint64_t reserved_9_63:55;
#endif
} s;
struct cvmx_spxx_dbg_deskew_state_s cn38xx;
struct cvmx_spxx_dbg_deskew_state_s cn38xxp2;
struct cvmx_spxx_dbg_deskew_state_s cn58xx;
struct cvmx_spxx_dbg_deskew_state_s cn58xxp1;
};
union cvmx_spxx_drv_ctl {
uint64_t u64;
struct cvmx_spxx_drv_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_0_63:64;
#else
uint64_t reserved_0_63:64;
#endif
} s;
struct cvmx_spxx_drv_ctl_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
uint64_t stx4ncmp:4;
uint64_t stx4pcmp:4;
uint64_t srx4cmp:8;
#else
uint64_t srx4cmp:8;
uint64_t stx4pcmp:4;
uint64_t stx4ncmp:4;
uint64_t reserved_16_63:48;
#endif
} cn38xx;
struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2;
struct cvmx_spxx_drv_ctl_cn58xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_24_63:40;
uint64_t stx4ncmp:4;
uint64_t stx4pcmp:4;
uint64_t reserved_10_15:6;
uint64_t srx4cmp:10;
#else
uint64_t srx4cmp:10;
uint64_t reserved_10_15:6;
uint64_t stx4pcmp:4;
uint64_t stx4ncmp:4;
uint64_t reserved_24_63:40;
#endif
} cn58xx;
struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1;
};
union cvmx_spxx_err_ctl {
uint64_t u64;
struct cvmx_spxx_err_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
uint64_t prtnxa:1;
uint64_t dipcls:1;
uint64_t dippay:1;
uint64_t reserved_4_5:2;
uint64_t errcnt:4;
#else
uint64_t errcnt:4;
uint64_t reserved_4_5:2;
uint64_t dippay:1;
uint64_t dipcls:1;
uint64_t prtnxa:1;
uint64_t reserved_9_63:55;
#endif
} s;
struct cvmx_spxx_err_ctl_s cn38xx;
struct cvmx_spxx_err_ctl_s cn38xxp2;
struct cvmx_spxx_err_ctl_s cn58xx;
struct cvmx_spxx_err_ctl_s cn58xxp1;
};
union cvmx_spxx_int_dat {
uint64_t u64;
struct cvmx_spxx_int_dat_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t mul:1;
uint64_t reserved_14_30:17;
uint64_t calbnk:2;
uint64_t rsvop:4;
uint64_t prt:8;
#else
uint64_t prt:8;
uint64_t rsvop:4;
uint64_t calbnk:2;
uint64_t reserved_14_30:17;
uint64_t mul:1;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_spxx_int_dat_s cn38xx;
struct cvmx_spxx_int_dat_s cn38xxp2;
struct cvmx_spxx_int_dat_s cn58xx;
struct cvmx_spxx_int_dat_s cn58xxp1;
};
union cvmx_spxx_int_msk {
uint64_t u64;
struct cvmx_spxx_int_msk_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t calerr:1;
uint64_t syncerr:1;
uint64_t diperr:1;
uint64_t tpaovr:1;
uint64_t rsverr:1;
uint64_t drwnng:1;
uint64_t clserr:1;
uint64_t spiovr:1;
uint64_t reserved_2_3:2;
uint64_t abnorm:1;
uint64_t prtnxa:1;
#else
uint64_t prtnxa:1;
uint64_t abnorm:1;
uint64_t reserved_2_3:2;
uint64_t spiovr:1;
uint64_t clserr:1;
uint64_t drwnng:1;
uint64_t rsverr:1;
uint64_t tpaovr:1;
uint64_t diperr:1;
uint64_t syncerr:1;
uint64_t calerr:1;
uint64_t reserved_12_63:52;
#endif
} s;
struct cvmx_spxx_int_msk_s cn38xx;
struct cvmx_spxx_int_msk_s cn38xxp2;
struct cvmx_spxx_int_msk_s cn58xx;
struct cvmx_spxx_int_msk_s cn58xxp1;
};
union cvmx_spxx_int_reg {
uint64_t u64;
struct cvmx_spxx_int_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t spf:1;
uint64_t reserved_12_30:19;
uint64_t calerr:1;
uint64_t syncerr:1;
uint64_t diperr:1;
uint64_t tpaovr:1;
uint64_t rsverr:1;
uint64_t drwnng:1;
uint64_t clserr:1;
uint64_t spiovr:1;
uint64_t reserved_2_3:2;
uint64_t abnorm:1;
uint64_t prtnxa:1;
#else
uint64_t prtnxa:1;
uint64_t abnorm:1;
uint64_t reserved_2_3:2;
uint64_t spiovr:1;
uint64_t clserr:1;
uint64_t drwnng:1;
uint64_t rsverr:1;
uint64_t tpaovr:1;
uint64_t diperr:1;
uint64_t syncerr:1;
uint64_t calerr:1;
uint64_t reserved_12_30:19;
uint64_t spf:1;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_spxx_int_reg_s cn38xx;
struct cvmx_spxx_int_reg_s cn38xxp2;
struct cvmx_spxx_int_reg_s cn58xx;
struct cvmx_spxx_int_reg_s cn58xxp1;
};
union cvmx_spxx_int_sync {
uint64_t u64;
struct cvmx_spxx_int_sync_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
uint64_t calerr:1;
uint64_t syncerr:1;
uint64_t diperr:1;
uint64_t tpaovr:1;
uint64_t rsverr:1;
uint64_t drwnng:1;
uint64_t clserr:1;
uint64_t spiovr:1;
uint64_t reserved_2_3:2;
uint64_t abnorm:1;
uint64_t prtnxa:1;
#else
uint64_t prtnxa:1;
uint64_t abnorm:1;
uint64_t reserved_2_3:2;
uint64_t spiovr:1;
uint64_t clserr:1;
uint64_t drwnng:1;
uint64_t rsverr:1;
uint64_t tpaovr:1;
uint64_t diperr:1;
uint64_t syncerr:1;
uint64_t calerr:1;
uint64_t reserved_12_63:52;
#endif
} s;
struct cvmx_spxx_int_sync_s cn38xx;
struct cvmx_spxx_int_sync_s cn38xxp2;
struct cvmx_spxx_int_sync_s cn58xx;
struct cvmx_spxx_int_sync_s cn58xxp1;
};
union cvmx_spxx_tpa_acc {
uint64_t u64;
struct cvmx_spxx_tpa_acc_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t cnt:32;
#else
uint64_t cnt:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_spxx_tpa_acc_s cn38xx;
struct cvmx_spxx_tpa_acc_s cn38xxp2;
struct cvmx_spxx_tpa_acc_s cn58xx;
struct cvmx_spxx_tpa_acc_s cn58xxp1;
};
union cvmx_spxx_tpa_max {
uint64_t u64;
struct cvmx_spxx_tpa_max_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
uint64_t max:32;
#else
uint64_t max:32;
uint64_t reserved_32_63:32;
#endif
} s;
struct cvmx_spxx_tpa_max_s cn38xx;
struct cvmx_spxx_tpa_max_s cn38xxp2;
struct cvmx_spxx_tpa_max_s cn58xx;
struct cvmx_spxx_tpa_max_s cn58xxp1;
};
union cvmx_spxx_tpa_sel {
uint64_t u64;
struct cvmx_spxx_tpa_sel_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
uint64_t prtsel:4;
#else
uint64_t prtsel:4;
uint64_t reserved_4_63:60;
#endif
} s;
struct cvmx_spxx_tpa_sel_s cn38xx;
struct cvmx_spxx_tpa_sel_s cn38xxp2;
struct cvmx_spxx_tpa_sel_s cn58xx;
struct cvmx_spxx_tpa_sel_s cn58xxp1;
};
union cvmx_spxx_trn4_ctl {
uint64_t u64;
struct cvmx_spxx_trn4_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63:51;
uint64_t trntest:1;
uint64_t jitter:3;
uint64_t clr_boot:1;
uint64_t set_boot:1;
uint64_t maxdist:5;
uint64_t macro_en:1;
uint64_t mux_en:1;
#else
uint64_t mux_en:1;
uint64_t macro_en:1;
uint64_t maxdist:5;
uint64_t set_boot:1;
uint64_t clr_boot:1;
uint64_t jitter:3;
uint64_t trntest:1;
uint64_t reserved_13_63:51;
#endif
} s;
struct cvmx_spxx_trn4_ctl_s cn38xx;
struct cvmx_spxx_trn4_ctl_s cn38xxp2;
struct cvmx_spxx_trn4_ctl_s cn58xx;
struct cvmx_spxx_trn4_ctl_s cn58xxp1;
};
#endif