keystone-navigator-qmss.txt
10.8 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
* Texas Instruments Keystone Navigator Queue Management SubSystem driver
The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
the main hardware sub system which forms the backbone of the Keystone
multi-core Navigator. QMSS consist of queue managers, packed-data structure
processors(PDSP), linking RAM, descriptor pools and infrastructure
Packet DMA.
The Queue Manager is a hardware module that is responsible for accelerating
management of the packet queues. Packets are queued/de-queued by writing or
reading descriptor address to a particular memory mapped location. The PDSPs
perform QMSS related functions like accumulation, QoS, or event management.
Linking RAM registers are used to link the descriptors which are stored in
descriptor RAM. Descriptor RAM is configurable as internal or external memory.
The QMSS driver manages the PDSP setups, linking RAM regions,
queue pool management (allocation, push, pop and notify) and descriptor
pool management.
Required properties:
- compatible : Must be "ti,keystone-navigator-qmss";
: Must be "ti,keystone-navigator-qmss-l" for NSS Lite
- clocks : phandle to the reference clock for this device.
- clock-names : names of the clocks in the clocks property.
- queue-range : <start number> total range of queue numbers for the device.
- linkram0 : <address size> for internal link ram, where size is the total
link ram entries.
- linkram1 : <address size> for external link ram, where size is the total
external link ram entries. If the address is specified as "0"
driver will allocate memory.
- qmgrs : child node describing the individual queue managers on the
SoC. On keystone 1 devices there should be only one node.
On keystone 2 devices there can be more than 1 node.
-- managed-queues : the actual queues managed by each queue manager
instance, specified as <"base queue #" "# of queues">.
-- reg : Address and size of the register set for the device.
Register regions should be specified in the following
order
- Queue Peek region.
- Queue status RAM.
- Queue configuration region.
- Descriptor memory setup region.
- Queue Management/Queue Proxy region for queue Push.
- Queue Management/Queue Proxy region for queue Pop.
For NSS lite, following QMSS reg indexes are used in that order
- Queue Peek region.
- Queue configuration region.
- Queue Management/Queue Proxy region for queue Push/Pop.
- queue-pools : child node classifying the queue ranges into pools.
Queue ranges are grouped into 3 type of pools:
- qpend : pool of qpend(interruptible) queues
- general-purpose : pool of general queues, primarly used
as free descriptor queues or the
transmit DMA queues.
- accumulator : pool of queues on PDSP accumulator channel
Each range can have the following properties:
-- qrange : number of queues to use per queue range, specified as
<"base queue #" "# of queues">.
-- interrupts : Optional property to specify the interrupt mapping
for interruptible queues. The driver additionaly sets
the interrupt affinity hint based on the cpu mask.
-- qalloc-by-id : Optional property to specify that the queues in this
range can only be allocated by queue id.
-- accumulator : Accumulator channel specification. Any of the PDSPs in
QMSS can be loaded with the accumulator firmware. The
accumulator firmware’s job is to poll a select number of
queues looking for descriptors that have been pushed
into them. Descriptors are popped from the queue and
placed in a buffer provided by the host. When the list
becomes full or a programmed time period expires, the
accumulator triggers an interrupt to the host to read
the buffer for descriptor information. This firmware
comes in 16, 32, and 48 channel builds. Each of these
channels can be configured to monitor 32 contiguous
queues. Accumulator channel property is specified as:
<pdsp-id, channel, entries, pacing mode, latency>
pdsp-id : QMSS PDSP running accumulator firmware
on which the channel has to be
configured
channel : Accumulator channel number
entries : Size of the accumulator descriptor list
pacing mode : Interrupt pacing mode
0 : None, i.e interrupt on list full only
1 : Time delay since last interrupt
2 : Time delay since first new packet
3 : Time delay since last new packet
latency : time to delay the interrupt, specified
in microseconds.
-- multi-queue : Optional property to specify that the channel has to
monitor upto 32 queues starting at the base queue #.
- descriptor-regions : child node describing the memory regions for keystone
navigator packet DMA descriptors. The memory for
descriptors will be allocated by the driver.
-- id : region number in QMSS.
-- region-spec : specifies the number of descriptors in the
region, specified as
<"# of descriptors" "descriptor size">.
-- link-index : start index, i.e. index of the first
descriptor in the region.
Optional properties:
- dma-coherent : Present if DMA operations are coherent.
- pdsps : child node describing the PDSP configuration.
-- firmware_type : type of firmware to be loaded on the PDSP.
-- id : the qmss pdsp that will run the firmware.
-- syscon-intd : Handle to the syscon regmap of the QMSS interrupt
distributor register region.
-- reg : Address and size of the register set for the PDSP.
Register regions should be specified in the following
order
- PDSP internal RAM region.
- PDSP control/status region registers.
- PDSP command interface region.
- qos-inputs - quality of service configuration
-- qrange = <start number> :
number of queues staring at queue number,
start are reserved for QoS
-- pdsp-id = <x> :
the qmss pdsp that has the QoS firmware :
-- ticks-per-sec = <ticks> :
the ticks per sec
-- qos-cfg = <inputs_per_port int_num qos_ticks drop_ticks seed_0,1,2> :
number of input queues per QoS firmware physical port,
timer interrupt number,
qos scheduler timer tick rate,
drop scheduler timer tick rate,
seeds to random number generator for dropping/marking packets
-- sched-port-configs = <start count size> :
scheduler port start index,
number of scheduler ports,
size of address space for scheduler port
-- drop-out-profiles = <start count size> :
output profile start index,
number of output profiles,
size of address space for output profile
-- drop-cfg-profiles = <start count size> :
config profile start index,
number of config profiles,
size of address space for config profile
-- drop-queue-configs = <start count size> :
drop queue config start index,
number of drop queue configs,
size of queue config address space
-- drop-policies = <&droppolicies> :
phandle for drop policies
-- qos-tree = <&qostree> :
phandle for the qos tree configuration
-- statistic-profiles = <start count> :
statistics profile start index,
number of statistics profiles
Example:
pdsp_intd: intd@2a0c000 {
compatible = "syscon";
reg = <0x2a0c000 0x3c8>;
};
qmss: qmss@2a40000 {
compatible = "ti,keystone-qmss";
dma-coherent;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&chipclk13>;
clock-names = "qmss_clk";
ranges;
queue-range = <0 0x4000>;
linkram0 = <0x100000 0x8000>;
linkram1 = <0x0 0x10000>;
qmgrs {
#address-cells = <1>;
#size-cells = <1>;
ranges;
qmgr0 {
managed-queues = <0 0x2000>;
reg = <0x2a40000 0x20000>,
<0x2a06000 0x400>,
<0x2a02000 0x1000>,
<0x2a03000 0x1000>,
<0x23a80000 0x20000>,
<0x2a80000 0x20000>;
};
qmgr1 {
managed-queues = <0x2000 0x2000>;
reg = <0x2a60000 0x20000>,
<0x2a06400 0x400>,
<0x2a04000 0x1000>,
<0x2a05000 0x1000>,
<0x23aa0000 0x20000>,
<0x2aa0000 0x20000>;
};
};
queue-pools {
qpend {
qpend-0 {
qrange = <658 8>;
interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
0 43 0xf04 0 44 0xf04 0 45 0xf04
0 46 0xf04 0 47 0xf04>;
};
qpend-1 {
qrange = <8704 16>;
interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
0 51 0xf04 0 52 0xf04 0 53 0xf04
0 54 0xf04 0 55 0xf04 0 56 0xf04
0 57 0xf04 0 58 0xf04 0 59 0xf04
0 60 0xf04 0 61 0xf04 0 62 0xf04
0 63 0xf04>;
qalloc-by-id;
};
qpend-2 {
qrange = <8720 16>;
interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
0 59 0xf04 0 68 0xf04 0 69 0xf04
0 70 0xf04 0 71 0xf04 0 72 0xf04
0 73 0xf04 0 74 0xf04 0 75 0xf04
0 76 0xf04 0 77 0xf04 0 78 0xf04
0 79 0xf04>;
};
};
general-purpose {
gp-0 {
qrange = <4000 64>;
};
netcp-tx {
qrange = <640 9>;
qalloc-by-id;
};
};
qos {
qosinputs0: qos-inputs-0 {
qrange = <8000 192>;
pdsp-id = <3>;
ticks-per-sec = <10000>;
/* inputs_per_port
* drop cfg int_num
* drop cfg qos_ticks
* drop cfg drop_ticks
* drop cfg seed_0,1,2
*/
qos-cfg = <4 50 1 1 0xf00 0 0>;
/* 4 types of shadows
* each with <start-idx cnt size>
*/
sched-port-configs = <0 20 0x1c8>;
drop-out-profiles = <0 36 0xc>;
drop-cfg-profiles = <0 8 0x14>;
drop-queue-configs = <0 80 0x4>;
drop-policies = <&droppolicies>;
qos-tree = <&qostree0>;
statistics-profiles = <0 48>;
qalloc-by-id;
};
qosinputs1: qos-inputs-1 {
qrange = <6400 192>;
pdsp-id = <7>;
ticks-per-sec = <10000>;
qos-cfg = <4 50 1 1 0xf00 0 0>;
sched-port-configs = <0 20 0x1c8>;
drop-out-profiles = <0 36 0xc>;
drop-cfg-profiles = <0 8 0x14>;
drop-queue-configs = <0 80 0x4>;
drop-policies = <&droppolicies>;
qos-tree = <&qostree1>;
statistics-profiles = <0 48>;
qalloc-by-id;
};
};
accumulator {
acc-0 {
qrange = <128 32>;
accumulator = <0 36 16 2 50>;
interrupts = <0 215 0xf01>;
multi-queue;
qalloc-by-id;
};
acc-1 {
qrange = <160 32>;
accumulator = <0 37 16 2 50>;
interrupts = <0 216 0xf01>;
multi-queue;
};
acc-2 {
qrange = <192 32>;
accumulator = <0 38 16 2 50>;
interrupts = <0 217 0xf01>;
multi-queue;
};
acc-3 {
qrange = <224 32>;
accumulator = <0 39 16 2 50>;
interrupts = <0 218 0xf01>;
multi-queue;
};
};
};
descriptor-regions {
#address-cells = <1>;
#size-cells = <1>;
ranges;
region-12 {
id = <12>;
region-spec = <8192 128>; /* num_desc desc_size */
link-index = <0x4000>;
};
};
pdsps {
#address-cells = <1>;
#size-cells = <1>;
ranges;
pdsp0@0x2a10000 {
firmware_type = "acc";
syscon-intd = <&pdsp_intd>;
reg = <0x2a10000 0x1000>,
<0x2a0f000 0x100>,
<0x2a20000 0x4000>;
id = <0>;
};
};
}; /* qmss */