keystone-dsp-mem.txt
1.77 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
TI Keystone DSP Memory Mapping Device
=====================================
Binding status: Unstable - ABI compatibility may be broken in the future
The Keystone DSP Memory Mapping Device is a device node used to represent
the memory regions that can be mapped into userspace for providing direct
user-mode access to regions for the purposes of shared memory communication
with the DSP remote processor devices on the SoC. It can also be used for
supporting user-space based loading of the DSP remoteproc devices.
Required properties:
--------------------
- compatible : Should be "ti,keystone-dsp-mem"
- reg : An array of memory regions (DDR), each region represented by a
tuple of the region's start address and the size of the region.
SRAM usage (Optional):
----------------------
The on-chip Multicore Shared Memory (MSM) RAM can also be exposed to
userspace by defining specific child nodes under the corresponding parent
SRAM node. The generic SRAM binding is as per the binding document
Documentation/devicetree/bindings/misc/sram.txt. Following properties
should be used in each corresponding child node for the userspace mapping
usecase:
- compatible : Should be "ti,keystone-dsp-msm-ram"
- reg : Should contain a pair of values for the address and size
of the region, following the parent-child ranges convention.
Example:
--------
/* K2HK EVM */
soc {
mpm_mem: dspmem {
compatible = "ti,keystone-dsp-mem";
reg = <0xa0000000 0x20000000>; /* DDR Memory */
};
msm_ram: msmram@0c000000 {
compatible = "mmio-sram";
reg = <0x0c000000 0x600000>;
ranges = <0x0 0x0c000000 0x600000>;
#address-cells = <1>;
#size-cells = <1>;
sram-mpm@0 {
compatible = "ti,keystone-dsp-msm-ram";
reg = <0x0 0x80000>;
};
};
};