* Synopsys Designware PCIe interface

Required properties:
- compatible: should contain "snps,dw-pcie" to identify the core.
- reg: Should contain the configuration address space.
- reg-names: Must be "config" for the PCIe configuration space.
    (The old way of getting the configuration address space from "ranges"
    is deprecated and should be avoided.)
- #address-cells (only for host mode): set to <3>
- #size-cells (only for host mode): set to <2>
- device_type (only for host mode): set to "pci"
- ranges (only for host mode): ranges for the PCI memory and I/O regions
- num-ib-windows (only for EP mode): number of inbound address translation
	windows
- num-ob-windows (only for EP mode): number of outbound address translation
	windows
- #interrupt-cells (only for host mode): set to <1>
- interrupt-map-mask and interrupt-map (only for host mode): standard PCI
	properties to define the mapping of the PCIe interface to interrupt
	numbers.
- num-lanes: number of lanes to use

Optional properties:
- num-lanes: number of lanes to use (this property should be specified unless
  the link is brought already up in BIOS)
- reset-gpio (only for host mode): gpio pin number of power good signal
- bus-range (only for host mode): PCI bus numbers covered (it is recommended
  for new devicetrees to specify this property, to keep backwards compatibility
  a range of 0x00-0xff is assumed if not present)
- clocks: Must contain an entry for each entry in clock-names.
	See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
	- "pcie"
	- "pcie_bus"