* Keystone DDR3 Memory Controller EDAC device bindings

Keystone MC EDAC node is defined to describe the DDR3 memory controller
ECC error detection hardware. The hardware is capable of auto correcting
1 bit ECC errors. 2 bit ECC errors are uncorrectable and triggers an
interrupt and handled by the edac ecc error driver which currently enables
only interrupt for uncorrectable errors.

The following section describes the EDAC DT node binding.

Required properties:
- compatible		: Shall be "ti,keystone-ddr3-mc-edac"
- reg			: DDR3 MC base address
- interrupts		: ECC error interrupt
- interrupt-parent	: Interrupt controller node

Example:
	ddr3edac {
		compatible = "ti,keystone-ddr3-mc-edac";
		reg = <0x21010000 0x200>;
		interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
		interrupt-parent = <&gic>;
	};