에프에이리눅스 / 1611_0007_prime_oven

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Commit d14b40250a51452047a22dd83954218100532bb3

Authored by 장형기
1 parent e5a0c50f8d
Exists in master and in 2 other branches fhd, fhd-demo

device tree 수정 및 추가

Showing 2 changed files with 622 additions and 3 deletions   Show diff stats
kernel/linux-imx6_3.14.28/arch/arm/boot/dts/imx6qdl-prime-oven.dtsi
  Diff comments   View file @d14b402
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  1 +/*
  2 + * Copyright 2015 Boundary Devices, Inc.
  3 + * Copyright 2012 Freescale Semiconductor, Inc.
  4 + * Copyright 2011 Linaro Ltd.
  5 + *
  6 + * The code contained herein is licensed under the GNU General Public
  7 + * License. You may obtain a copy of the GNU General Public License
  8 + * Version 2 or later at the following locations:
  9 + *
  10 + * http://www.opensource.org/licenses/gpl-license.html
  11 + * http://www.gnu.org/copyleft/gpl.html
  12 + */
  13 +#include <dt-bindings/input/input.h>
  14 +
  15 +&iomuxc {
  16 + pinctrl-names = "default";
  17 + pinctrl-0 = <&pinctrl_hog>;
  18 +
  19 + iomuxc_imx6q_cmf1000: iomuxc-imx6q-cmf1000grp {
  20 + status = "okay";
  21 + };
  22 +};
  23 +
  24 +&iomuxc_imx6q_cmf1000 {
  25 + pinctrl_audmux: audmuxgrp {
  26 + fsl,pins = <
  27 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
  28 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
  29 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
  30 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
  31 + >;
  32 + };
  33 +
  34 + pinctrl_ecspi1: ecspi1grp {
  35 + fsl,pins = <
  36 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  37 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  38 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1
  39 +#define GP_ECSPI1_CS <&gpio3 19 GPIO_ACTIVE_LOW>
  40 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1
  41 + >;
  42 + };
  43 +
  44 + pinctrl_ecspi2: ecspi2grp {
  45 + fsl,pins = <
  46 + MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1
  47 + MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
  48 + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000b1
  49 +#define GP_ECSPI2_CS <&gpio5 12 GPIO_ACTIVE_LOW>
  50 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0b0b1
  51 + >;
  52 + };
  53 +
  54 + pinctrl_enet: enetgrp {
  55 + fsl,pins = <
  56 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  57 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  58 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  59 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  60 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  61 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  62 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  63 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  64 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  65 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  66 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  67 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  68 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  69 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  70 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  71 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  72 +#define GP_ENET_PHY_RESET <&gpio1 25 GPIO_ACTIVE_LOW>
  73 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x0f0b0 /* ethernet phy reset */
  74 +#define GPIRQ_ENET_PHY <&gpio1 26 IRQ_TYPE_LEVEL_LOW>
  75 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* ethernet phy interrupt */
  76 + >;
  77 + };
  78 +
  79 + pinctrl_gpio_leds: gpio-ledsgrp {
  80 + fsl,pins = <
  81 +#define GP_CPU_LED1 <&gpio1 2 GPIO_ACTIVE_HIGH>
  82 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
  83 +#define GP_CPU_LED2 <&gpio2 4 GPIO_ACTIVE_HIGH>
  84 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
  85 + >;
  86 + };
  87 +
  88 + pinctrl_hdmi_cec: hdmi_cecgrp {
  89 + fsl,pins = <
  90 + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
  91 + >;
  92 + };
  93 +
  94 + pinctrl_hog: hoggrp {
  95 + fsl,pins = <
  96 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* LCD Power Enable */
  97 + >;
  98 + };
  99 +
  100 + pinctrl_i2c1: i2c1grp {
  101 + fsl,pins = <
  102 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
  103 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
  104 + >;
  105 + };
  106 +
  107 + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp {
  108 + fsl,pins = <
  109 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */
  110 + >;
  111 + };
  112 +
  113 + pinctrl_i2c2: i2c2grp {
  114 + fsl,pins = <
  115 + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  116 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  117 + >;
  118 + };
  119 +
  120 + pinctrl_i2c2_max1180: i2c2-max1180grp {
  121 + fsl,pins = <
  122 +#define GPIRQ_MAX1180 <&gpio6 9 IRQ_TYPE_EDGE_FALLING>
  123 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 /* max1180 interrupt */
  124 + >;
  125 + };
  126 +
  127 + pinctrl_i2c3: i2c3grp {
  128 + fsl,pins = <
  129 + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
  130 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  131 + >;
  132 + };
  133 +
  134 + pinctrl_pwm1: pwm1grp {
  135 + fsl,pins = <
  136 + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
  137 + >;
  138 + };
  139 +
  140 + pinctrl_pcie: pciegrp {
  141 + fsl,pins = <
  142 +#define GP_PCIE_RESET <&gpio6 11 GPIO_ACTIVE_HIGH> /* GPIO_ACTIVE_HIGH 0, GPIO_ACTIVE_LOW 1 */
  143 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x000b0 /* PCIe Reset */
  144 +#define GP_PCIE_WAKE <&gpio6 14 GPIO_ACTIVE_HIGH> /* GPIO_ACTIVE_HIGH 0, GPIO_ACTIVE_LOW 1 */
  145 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 /* PCIe Wake */
  146 + >;
  147 + };
  148 +
  149 + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
  150 + fsl,pins = <
  151 +#define GP_REG_USBOTG <&gpio3 22 GPIO_ACTIVE_HIGH>
  152 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x030b0
  153 + >;
  154 + };
  155 +
  156 + pinctrl_reg_wlan_en: reg-wlan-engrp {
  157 + fsl,pins = <
  158 +#define GP_REG_WLAN_EN <&gpio6 15 GPIO_ACTIVE_HIGH>
  159 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x030b0
  160 + >;
  161 + };
  162 +
  163 + pinctrl_uart1: uart1grp {
  164 + fsl,pins = <
  165 + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  166 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  167 + >;
  168 + };
  169 +
  170 + pinctrl_uart2: uart2grp {
  171 + fsl,pins = <
  172 + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
  173 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
  174 + >;
  175 + };
  176 +
  177 + pinctrl_uart3: uart3grp {
  178 + fsl,pins = <
  179 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
  180 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
  181 + MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
  182 + MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1
  183 + >;
  184 + };
  185 +
  186 + pinctrl_uart4: uart4grp {
  187 + fsl,pins = <
  188 + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  189 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  190 + >;
  191 + };
  192 +
  193 + pinctrl_usbh1: usbh1grp {
  194 + fsl,pins = <
  195 +#define GP_USBH1_HUB_RESET <&gpio7 12 GPIO_ACTIVE_LOW>
  196 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0
  197 + >;
  198 + };
  199 +
  200 + pinctrl_usbotg: usbotggrp {
  201 + fsl,pins = <
  202 + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
  203 + >;
  204 + };
  205 +
  206 + pinctrl_usdhc3: usdhc3grp {
  207 + fsl,pins = <
  208 + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  209 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  210 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  211 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  212 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  213 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  214 +#define GP_USDHC3_CD <&gpio7 0 GPIO_ACTIVE_LOW>
  215 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
  216 +#define GP_USDHC3_WP <&gpio7 1 GPIO_ACTIVE_LOW>
  217 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
  218 + >;
  219 + };
  220 +
  221 + pinctrl_usdhc4: usdhc4grp {
  222 + fsl,pins = <
  223 + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
  224 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
  225 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
  226 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
  227 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
  228 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
  229 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
  230 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
  231 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
  232 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
  233 + >;
  234 + };
  235 +};
  236 +
  237 +/ {
  238 + aliases {
  239 + mmc0 = &usdhc3;
  240 + mmc1 = &usdhc4;
  241 + mxcfb0 = &mxcfb1;
  242 + mxcfb1 = &mxcfb2;
  243 + };
  244 +
  245 + clocks {
  246 + clk24m: clk24m {
  247 + compatible = "fixed-clock";
  248 + #clock-cells = <0>;
  249 + clock-frequency = <24000000>;
  250 + };
  251 + };
  252 +
  253 + memory {
  254 + reg = <0x10000000 0x40000000>;
  255 + };
  256 +
  257 + leds {
  258 + compatible = "gpio-leds";
  259 + pinctrl-names = "default";
  260 + pinctrl-0 = <&pinctrl_gpio_leds>;
  261 +
  262 + cpu-led1 {
  263 + label = "cpu-led1";
  264 + gpios = GP_CPU_LED1;
  265 + linux,default-trigger = "time";
  266 + retain-state-suspended;
  267 + };
  268 + cpu-led2 {
  269 + label = "cpu-led2";
  270 + gpios = GP_CPU_LED2;
  271 + linux,default-trigger = "none";
  272 + retain-state-suspended;
  273 + };
  274 + };
  275 +
  276 + regulators {
  277 + compatible = "simple-bus";
  278 + #address-cells = <1>;
  279 + #size-cells = <0>;
  280 +
  281 + reg_1p8v: regulator@0 {
  282 + compatible = "regulator-fixed";
  283 + reg = <0>;
  284 + regulator-name = "1P8V";
  285 + regulator-min-microvolt = <1800000>;
  286 + regulator-max-microvolt = <1800000>;
  287 + regulator-always-on;
  288 + };
  289 +
  290 + reg_2p5v: regulator@1 {
  291 + compatible = "regulator-fixed";
  292 + reg = <1>;
  293 + regulator-name = "2P5V";
  294 + regulator-min-microvolt = <2500000>;
  295 + regulator-max-microvolt = <2500000>;
  296 + regulator-always-on;
  297 + };
  298 +
  299 + reg_3p3v: regulator@2 {
  300 + compatible = "regulator-fixed";
  301 + reg = <2>;
  302 + regulator-name = "3P3V";
  303 + regulator-min-microvolt = <3300000>;
  304 + regulator-max-microvolt = <3300000>;
  305 + regulator-always-on;
  306 + };
  307 +
  308 + reg_usbotg_vbus: regulator@3 {
  309 + compatible = "regulator-fixed";
  310 + reg = <3>;
  311 + pinctrl-names = "default";
  312 + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
  313 + regulator-name = "usb_otg_vbus";
  314 + regulator-min-microvolt = <5000000>;
  315 + regulator-max-microvolt = <5000000>;
  316 + gpio = GP_REG_USBOTG;
  317 + enable-active-high;
  318 + };
  319 + };
  320 +
  321 + sound {
  322 + compatible = "fsl,imx6q-cmf-sgtl5000",
  323 + "fsl,imx-audio-sgtl5000";
  324 + model = "imx6q-cmf-sgtl5000";
  325 + cpu-dai = <&ssi1>;
  326 + audio-codec = <&sgtl5000>;
  327 + audio-routing =
  328 + "MIC_IN", "Mic Jack",
  329 + "Mic Jack", "Mic Bias",
  330 + "Headphone Jack", "HP_OUT";
  331 + mux-int-port = <1>;
  332 + mux-ext-port = <3>;
  333 + };
  334 +
  335 + sound-hdmi {
  336 + compatible = "fsl,imx6q-audio-hdmi",
  337 + "fsl,imx-audio-hdmi";
  338 + model = "imx-audio-hdmi";
  339 + hdmi-controller = <&hdmi_audio>;
  340 + };
  341 +
  342 + mxcfb1: fb@0 {
  343 + compatible = "fsl,mxc_sdc_fb";
  344 + disp_dev = "ldb";
  345 + interface_pix_fmt = "RGB24";
  346 + default_bpp = <32>;
  347 + int_clk = <0>;
  348 + late_init = <0>;
  349 + status = "disabled";
  350 + };
  351 +
  352 + mxcfb2: fb@1 {
  353 + compatible = "fsl,mxc_sdc_fb";
  354 + disp_dev = "hdmi";
  355 + interface_pix_fmt = "RGB24";
  356 + mode_str ="1920x1080M@60";
  357 + default_bpp = <24>;
  358 + int_clk = <0>;
  359 + late_init = <0>;
  360 + status = "disabled";
  361 + };
  362 +
  363 + backlight_lvds {
  364 + compatible = "pwm-backlight";
  365 + pwms = <&pwm1 0 5000000>;
  366 + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>;
  367 + default-brightness-level = <8>;
  368 + };
  369 +
  370 + v4l2_cap_0: v4l2_cap_0 {
  371 + compatible = "fsl,imx6q-v4l2-capture";
  372 + ipu_id = <0>;
  373 + csi_id = <0>;
  374 + mclk_source = <0>;
  375 + status = "okay";
  376 + };
  377 +
  378 + v4l2_cap_1: v4l2_cap_1 {
  379 + compatible = "fsl,imx6q-v4l2-capture";
  380 + ipu_id = <0>;
  381 + csi_id = <1>;
  382 + mclk_source = <0>;
  383 + status = "okay";
  384 + };
  385 +
  386 + v4l2_out {
  387 + compatible = "fsl,mxc_v4l2_output";
  388 + status = "okay";
  389 + };
  390 +};
  391 +
  392 +&audmux {
  393 + status = "okay";
  394 + pinctrl-names = "default";
  395 + pinctrl-0 = <&pinctrl_audmux>;
  396 +};
  397 +
  398 +&ecspi1 {
  399 + fsl,spi-num-chipselects = <1>;
  400 + cs-gpios = GP_ECSPI1_CS;
  401 + pinctrl-names = "default";
  402 + pinctrl-0 = <&pinctrl_ecspi1>;
  403 + status = "okay";
  404 +
  405 + spidev@0 {
  406 + compatible = "spidev";
  407 + spi-max-frequency = <20000000>;
  408 + reg = <0>;
  409 + status = "okay";
  410 + };
  411 +};
  412 +
  413 +&ecspi2 {
  414 + fsl,spi-num-chipselects = <2>;
  415 + cs-gpios = GP_ECSPI2_CS;
  416 + pinctrl-names = "default";
  417 + pinctrl-0 = <&pinctrl_ecspi2>;
  418 + status = "okay";
  419 +
  420 + spidev@0 {
  421 + compatible = "spidev";
  422 + spi-max-frequency = <20000000>;
  423 + reg = <0>;
  424 + status = "okay";
  425 + };
  426 +};
  427 +
  428 +&fec {
  429 + pinctrl-names = "default";
  430 + pinctrl-0 = <&pinctrl_enet>;
  431 + phy-mode = "rgmii";
  432 +#if 0
  433 + phy-reset-gpios = GP_ENET_PHY_RESET;
  434 +#endif
  435 + status = "okay";
  436 +
  437 + #address-cells = <0>;
  438 + #size-cells = <1>;
  439 + phy_int {
  440 + reg = <0x6>;
  441 + interrupts-extended = GPIRQ_ENET_PHY;
  442 + };
  443 +};
  444 +
  445 +&hdmi_audio {
  446 + status = "okay";
  447 +};
  448 +
  449 +&hdmi_cec {
  450 + pinctrl-names = "default";
  451 + pinctrl-0 = <&pinctrl_hdmi_cec>;
  452 + status = "okay";
  453 +};
  454 +
  455 +&hdmi_core {
  456 + ipu_id = <0>;
  457 + disp_id = <1>;
  458 + status = "okay";
  459 +};
  460 +
  461 +&hdmi_video {
  462 + fsl,phy_reg_vlev = <0x0294>;
  463 + fsl,phy_reg_cksymtx = <0x800d>;
  464 + status = "okay";
  465 +};
  466 +
  467 +&i2c1 {
  468 + clock-frequency = <100000>;
  469 + pinctrl-names = "default";
  470 + pinctrl-0 = <&pinctrl_i2c1>;
  471 + status = "okay";
  472 +
  473 + sgtl5000: sgtl5000@0a {
  474 + compatible = "fsl,sgtl5000";
  475 + pinctrl-names = "default";
  476 + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>;
  477 + reg = <0x0a>;
  478 + clocks = <&clks 201>;
  479 + VDDA-supply = <&reg_2p5v>;
  480 + VDDIO-supply = <&reg_3p3v>;
  481 + };
  482 +};
  483 +
  484 +&i2c2 {
  485 + clock-frequency = <100000>;
  486 + pinctrl-names = "default";
  487 + pinctrl-0 = <&pinctrl_i2c2>;
  488 + status = "okay";
  489 +
  490 + hdmi: edid@50 {
  491 + compatible = "fsl,imx6-hdmi-i2c";
  492 + reg = <0x50>;
  493 + };
  494 +
  495 + rtc: ds1339@68 {
  496 + compatible = "dallas,ds1339";
  497 + reg = <0x68>;
  498 + };
  499 +
  500 + max1180: max11801@48 {
  501 + compatible = "maxim,max11801";
  502 + reg = <0x48>;
  503 + pinctrl-names = "default";
  504 + pinctrl-0 = <&pinctrl_i2c2_max1180>;
  505 + interrupts-extended = GPIRQ_MAX1180;
  506 + work-mode = <0>;
  507 + };
  508 +};
  509 +
  510 +&i2c3 {
  511 + clock-frequency = <100000>;
  512 + pinctrl-names = "default";
  513 + pinctrl-0 = <&pinctrl_i2c3>;
  514 + status = "okay";
  515 +};
  516 +
  517 +&ldb {
  518 + status = "okay";
  519 +
  520 + lvds-channel@0 {
  521 + fsl,data-mapping = "spwg";
  522 + fsl,data-width = <24>;
  523 + status = "okay";
  524 + primary;
  525 +
  526 + display-timings {
  527 + native-mode = <&timing0>;
  528 + timing0: LDB-G156BGE {
  529 + clock-frequency = <76000000>;
  530 + hactive = <1366>;
  531 + vactive = <768>;
  532 + hback-porch = <130>;
  533 + hfront-porch = <60>;
  534 + vback-porch = <32>;
  535 + vfront-porch = <3>;
  536 + hsync-len = <4>;
  537 + vsync-len = <3>;
  538 + };
  539 + };
  540 + };
  541 +};
  542 +
  543 +&pcie {
  544 + pinctrl-names = "default";
  545 + pinctrl-0 = <&pinctrl_pcie>;
  546 + reset-gpio = GP_PCIE_RESET;
  547 + wake-up-gpio = GP_PCIE_WAKE;
  548 + status = "okay";
  549 +};
  550 +
  551 +&pwm1 {
  552 + pinctrl-names = "default";
  553 + pinctrl-0 = <&pinctrl_pwm1>;
  554 + status = "okay";
  555 +};
  556 +
  557 +&ssi1 {
  558 + fsl,mode = "i2s-slave";
  559 + status = "okay";
  560 +};
  561 +
  562 +&uart1 {
  563 + pinctrl-names = "default";
  564 + pinctrl-0 = <&pinctrl_uart1>;
  565 + status = "okay";
  566 +};
  567 +
  568 +&uart2 {
  569 + pinctrl-names = "default";
  570 + pinctrl-0 = <&pinctrl_uart2>;
  571 + status = "okay";
  572 +};
  573 +
  574 +&uart3 {
  575 + pinctrl-names = "default";
  576 + pinctrl-0 = <&pinctrl_uart3>;
  577 + fsl,uart-has-rtscts;
  578 + status = "okay";
  579 +};
  580 +
  581 +&uart4 {
  582 + pinctrl-names = "default";
  583 + pinctrl-0 = <&pinctrl_uart4>;
  584 + status = "okay";
  585 +};
  586 +
  587 +&usbh1 {
  588 + disable-over-current;
  589 + status = "okay";
  590 +};
  591 +
  592 +&usbotg {
  593 + vbus-supply = <&reg_usbotg_vbus>;
  594 + pinctrl-names = "default";
  595 + pinctrl-0 = <&pinctrl_usbotg>;
  596 + disable-over-current;
  597 + status = "okay";
  598 +};
  599 +
  600 +&usdhc3 {
  601 + pinctrl-names = "default";
  602 + pinctrl-0 = <&pinctrl_usdhc3>;
  603 + bus-width = <4>;
  604 + cd-gpios = GP_USDHC3_CD;
  605 + wp-gpios = GP_USDHC3_WP;
  606 + vmmc-supply = <&reg_3p3v>;
  607 + status = "okay";
  608 +};
  609 +
  610 +&usdhc4 {
  611 + pinctrl-names = "default";
  612 + pinctrl-0 = <&pinctrl_usdhc4>;
  613 + bus-width = <8>;
  614 + non-removable;
  615 + vmmc-supply = <&reg_3p3v>;
  616 + keep-power-in-suspend;
  617 + status = "okay";
  618 +};
  619 +
kernel/linux-imx6_3.14.28/arch/arm/boot/dts/imx6s-prime-oven.dts
  Diff comments   View file @d14b402
@@ -15,11 +15,11 @@ @@ -15,11 +15,11 @@
15 15
16 #include <dt-bindings/interrupt-controller/irq.h> 16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include "imx6dl.dtsi" 17 #include "imx6dl.dtsi"
18 -#include "imx6qdl-cmf.dtsi" 18 +#include "imx6qdl-prime-oven.dtsi"
19 19
20 / { 20 / {
21 - model = "Freescale i.MX6 Solo/DualLite Cellumed CMF1000 Device Board(PFUZE100)";  
22 - compatible = "fsl,imx6dl-cmf", "fsl,imx6dl"; 21 + model = "Freescale i.MX6 Solo/DualLite Prime Oven Device Board(PFUZE100)";
  22 + compatible = "fsl,imx6dl-prime-oven", "fsl,imx6dl";
23 }; 23 };
24 24
25 &mxcfb1 { 25 &mxcfb1 {