Commit 540d18e7310299e0c827cc5be8328b72c9883f88
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kernel: jig용 dtb추가
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kernel/linux-imx6_3.14.28/arch/arm/boot/dts/Makefile
kernel/linux-imx6_3.14.28/arch/arm/boot/dts/imx6qdl-prime-oven_jig.dtsi
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1 | +/* | |
2 | + * Copyright 2015 Boundary Devices, Inc. | |
3 | + * Copyright 2012 Freescale Semiconductor, Inc. | |
4 | + * Copyright 2011 Linaro Ltd. | |
5 | + * | |
6 | + * The code contained herein is licensed under the GNU General Public | |
7 | + * License. You may obtain a copy of the GNU General Public License | |
8 | + * Version 2 or later at the following locations: | |
9 | + * | |
10 | + * http://www.opensource.org/licenses/gpl-license.html | |
11 | + * http://www.gnu.org/copyleft/gpl.html | |
12 | + */ | |
13 | +#include <dt-bindings/input/input.h> | |
14 | + | |
15 | +&iomuxc { | |
16 | + pinctrl-names = "default"; | |
17 | + pinctrl-0 = <&pinctrl_hog>; | |
18 | + | |
19 | + iomuxc_imx6q_primeoven: iomuxc-imx6q-primeovengrp { | |
20 | + status = "okay"; | |
21 | + }; | |
22 | +}; | |
23 | + | |
24 | +&iomuxc_imx6q_primeoven { | |
25 | + pinctrl_audmux: audmuxgrp { | |
26 | + fsl,pins = < | |
27 | + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 | |
28 | + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 | |
29 | + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 | |
30 | + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 | |
31 | + >; | |
32 | + }; | |
33 | + | |
34 | + pinctrl_ecspi1: ecspi1grp { | |
35 | + fsl,pins = < | |
36 | + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 /* MISO */ | |
37 | + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 /* MOSI */ | |
38 | + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x000b1 /* SLCK */ | |
39 | + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b1 /* SS1 */ | |
40 | + >; | |
41 | + }; | |
42 | + | |
43 | + pinctrl_enet: enetgrp { | |
44 | + fsl,pins = < | |
45 | + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | |
46 | + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | |
47 | + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | |
48 | + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | |
49 | + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | |
50 | + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | |
51 | + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | |
52 | + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | |
53 | + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | |
54 | + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | |
55 | + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | |
56 | + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | |
57 | + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | |
58 | + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | |
59 | + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | |
60 | + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | |
61 | + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x0f0b0 /* ethernet phy reset */ | |
62 | + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* ethernet phy interrupt */ | |
63 | + >; | |
64 | + }; | |
65 | + | |
66 | + pinctrl_gpio_leds: gpio-ledsgrp { | |
67 | + fsl,pins = < | |
68 | + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* CPU-RUN */ | |
69 | + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CPU-ERROR */ | |
70 | + >; | |
71 | + }; | |
72 | + | |
73 | + pinctrl_hog: hoggrp { | |
74 | + fsl,pins = < | |
75 | + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 /* LCD Power Enable */ | |
76 | + | |
77 | + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x80000000 /* LED_1 */ | |
78 | + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 /* LED_2 */ | |
79 | + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x80000000 /* LED_3 */ | |
80 | + | |
81 | + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x80000000 /* IO_OUT */ | |
82 | + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* IO_IN */ | |
83 | + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* IO_IN1_EXT */ | |
84 | + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* IO_IN2_EXT */ | |
85 | + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* IO_OUT1_EXT */ | |
86 | + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* IO_OUT2_EXT */ | |
87 | + | |
88 | + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x80000000 /* ENCODER_R */ | |
89 | + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* ENCODER_L */ | |
90 | + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* ENCODER_BUTTON */ | |
91 | + | |
92 | + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* USB1_DRVVBUS */ | |
93 | + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* USB2_DRVVBUS */ | |
94 | + >; | |
95 | + }; | |
96 | + | |
97 | + pinctrl_pwm1: pwm1grp { | |
98 | + fsl,pins = < | |
99 | + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 /* LCD Backlight */ | |
100 | + >; | |
101 | + }; | |
102 | + | |
103 | + pinctrl_i2c1: i2c1grp { | |
104 | + fsl,pins = < | |
105 | + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | |
106 | + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | |
107 | + >; | |
108 | + }; | |
109 | + | |
110 | + pinctrl_i2c1_sgtl5000: i2c1-sgtl5000grp { | |
111 | + fsl,pins = < | |
112 | + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* sys_mclk */ | |
113 | + >; | |
114 | + }; | |
115 | + | |
116 | + pinctrl_i2c2: i2c2grp { | |
117 | + fsl,pins = < | |
118 | + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | |
119 | + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | |
120 | + >; | |
121 | + }; | |
122 | + | |
123 | + pinctrl_i2c2_tsc2007: i2c2-tsc2007grp { | |
124 | + fsl,pins = < | |
125 | + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 /* tsc2007 interrupt */ | |
126 | + >; | |
127 | + }; | |
128 | + | |
129 | + pinctrl_i2c3: i2c3grp { | |
130 | + fsl,pins = < | |
131 | + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 | |
132 | + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | |
133 | + >; | |
134 | + }; | |
135 | + | |
136 | + pinctrl_uart1: uart1grp { | |
137 | + fsl,pins = < | |
138 | + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 | |
139 | + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 | |
140 | + >; | |
141 | + }; | |
142 | + | |
143 | + pinctrl_uart2: uart2grp { | |
144 | + fsl,pins = < | |
145 | + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 | |
146 | + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 | |
147 | + >; | |
148 | + }; | |
149 | + | |
150 | + pinctrl_uart3: uart3grp { | |
151 | + fsl,pins = < | |
152 | + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 | |
153 | + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 | |
154 | + >; | |
155 | + }; | |
156 | + | |
157 | + pinctrl_uart4: uart4grp { | |
158 | + fsl,pins = < | |
159 | + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 | |
160 | + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 | |
161 | + >; | |
162 | + }; | |
163 | + | |
164 | + pinctrl_usbotg: usbotggrp { | |
165 | + fsl,pins = < | |
166 | + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 | |
167 | + >; | |
168 | + }; | |
169 | + | |
170 | + pinctrl_usdhc3: usdhc3grp { | |
171 | + fsl,pins = < | |
172 | + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | |
173 | + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | |
174 | + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | |
175 | + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | |
176 | + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | |
177 | + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | |
178 | + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 | |
179 | + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 | |
180 | + >; | |
181 | + }; | |
182 | + | |
183 | + pinctrl_usdhc4: usdhc4grp { | |
184 | + fsl,pins = < | |
185 | + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | |
186 | + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | |
187 | + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | |
188 | + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | |
189 | + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | |
190 | + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | |
191 | + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 | |
192 | + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 | |
193 | + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 | |
194 | + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 | |
195 | + >; | |
196 | + }; | |
197 | + | |
198 | + pinctrl_hdmi_cec: hdmi_cecgrp { | |
199 | + fsl,pins = < | |
200 | + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 | |
201 | + >; | |
202 | + }; | |
203 | +}; | |
204 | + | |
205 | +/ { | |
206 | + aliases { | |
207 | + mmc2 = &usdhc3; | |
208 | + mmc3 = &usdhc4; | |
209 | + mxcfb0 = &mxcfb1; | |
210 | + mxcfb1 = &mxcfb2; | |
211 | + }; | |
212 | + | |
213 | + clocks { | |
214 | + clk24m: clk24m { | |
215 | + compatible = "fixed-clock"; | |
216 | + #clock-cells = <0>; | |
217 | + clock-frequency = <24000000>; | |
218 | + }; | |
219 | + }; | |
220 | + | |
221 | + memory { | |
222 | + reg = <0x10000000 0x40000000>; /* 1GByte */ | |
223 | + }; | |
224 | + | |
225 | + leds { | |
226 | + compatible = "gpio-leds"; | |
227 | + pinctrl-names = "default"; | |
228 | + pinctrl-0 = <&pinctrl_gpio_leds>; | |
229 | + | |
230 | + cpu-run { | |
231 | + label = "cpu-run"; | |
232 | + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; | |
233 | + linux,default-trigger = "timer"; | |
234 | + retain-state-suspended; | |
235 | + }; | |
236 | + cpu-error { | |
237 | + label = "cpu-error"; | |
238 | + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; | |
239 | + linux,default-trigger = "none"; | |
240 | + retain-state-suspended; | |
241 | + }; | |
242 | + }; | |
243 | + | |
244 | + regulators { | |
245 | + compatible = "simple-bus"; | |
246 | + #address-cells = <1>; | |
247 | + #size-cells = <0>; | |
248 | + | |
249 | + reg_1p2v: regulator@0 { | |
250 | + compatible = "regulator-fixed"; | |
251 | + reg = <0>; | |
252 | + regulator-name = "1P2V"; | |
253 | + regulator-min-microvolt = <1200000>; | |
254 | + regulator-max-microvolt = <1200000>; | |
255 | + regulator-always-on; | |
256 | + }; | |
257 | + | |
258 | + reg_2p5v: regulator@1 { | |
259 | + compatible = "regulator-fixed"; | |
260 | + reg = <1>; | |
261 | + regulator-name = "2P5V"; | |
262 | + regulator-min-microvolt = <2500000>; | |
263 | + regulator-max-microvolt = <2500000>; | |
264 | + regulator-always-on; | |
265 | + }; | |
266 | + | |
267 | + reg_3p3v: regulator@2 { | |
268 | + compatible = "regulator-fixed"; | |
269 | + reg = <2>; | |
270 | + regulator-name = "3P3V"; | |
271 | + regulator-min-microvolt = <3300000>; | |
272 | + regulator-max-microvolt = <3300000>; | |
273 | + regulator-always-on; | |
274 | + }; | |
275 | + | |
276 | + reg_usbotg_vbus: regulator@3 { | |
277 | + compatible = "regulator-fixed"; | |
278 | + reg = <3>; | |
279 | + pinctrl-names = "default"; | |
280 | + regulator-name = "usb_otg_vbus"; | |
281 | + regulator-min-microvolt = <5000000>; | |
282 | + regulator-max-microvolt = <5000000>; | |
283 | + enable-active-high; | |
284 | + }; | |
285 | + }; | |
286 | + | |
287 | + sound { | |
288 | + compatible = "fsl,imx6q-cmf-sgtl5000", | |
289 | + "fsl,imx-audio-sgtl5000"; | |
290 | + model = "imx6q-cmf-sgtl5000"; | |
291 | + cpu-dai = <&ssi1>; | |
292 | + audio-codec = <&sgtl5000>; | |
293 | + audio-routing = | |
294 | + "MIC_IN", "Mic Jack", | |
295 | + "Mic Jack", "Mic Bias", | |
296 | + "Headphone Jack", "HP_OUT"; | |
297 | + mux-int-port = <1>; | |
298 | + mux-ext-port = <3>; | |
299 | + }; | |
300 | + | |
301 | + mxcfb1: fb@0 { | |
302 | + compatible = "fsl,mxc_sdc_fb"; | |
303 | + disp_dev = "hdmi"; | |
304 | + interface_pix_fmt = "RGB24"; | |
305 | + mode_str ="1920x1080M@60"; | |
306 | + default_bpp = <24>; | |
307 | + int_clk = <0>; | |
308 | + late_init = <0>; | |
309 | + status = "okay"; | |
310 | + }; | |
311 | + | |
312 | + mxcfb2: fb@1 { | |
313 | + compatible = "fsl,mxc_sdc_fb"; | |
314 | + disp_dev = "ldb"; | |
315 | + interface_pix_fmt = "RGB666"; | |
316 | + default_bpp = <16>; | |
317 | + int_clk = <0>; | |
318 | + late_init = <0>; | |
319 | + status = "okay"; | |
320 | + }; | |
321 | + | |
322 | + backlight_lvds { | |
323 | + compatible = "pwm-backlight"; | |
324 | + pwms = <&pwm1 0 2000000>; | |
325 | + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>; | |
326 | + default-brightness-level = <8>; | |
327 | + }; | |
328 | +}; | |
329 | + | |
330 | + | |
331 | +&audmux { | |
332 | + status = "okay"; | |
333 | + pinctrl-names = "default"; | |
334 | + pinctrl-0 = <&pinctrl_audmux>; | |
335 | +}; | |
336 | + | |
337 | +&ecspi1 { | |
338 | + fsl,spi-num-chipselects = <1>; | |
339 | + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; | |
340 | + pinctrl-names = "default"; | |
341 | + pinctrl-0 = <&pinctrl_ecspi1>; | |
342 | + status = "okay"; | |
343 | + | |
344 | + /* | |
345 | + spidev@0 { | |
346 | + compatible = "spidev"; | |
347 | + spi-max-frequency = <20000000>; | |
348 | + reg = <0>; | |
349 | + status = "okay"; | |
350 | + }; | |
351 | + */ | |
352 | + | |
353 | + MB85RS16N@0 { | |
354 | + compatible = "Fujitsu,MB85RS16N"; | |
355 | + reg = <0>; | |
356 | + spi-max-frequency = <5000000>; | |
357 | + }; | |
358 | +}; | |
359 | + | |
360 | +&fec { | |
361 | + pinctrl-names = "default"; | |
362 | + pinctrl-0 = <&pinctrl_enet>; | |
363 | + phy-mode = "rgmii"; | |
364 | +#if 0 | |
365 | + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; | |
366 | +#endif | |
367 | + status = "okay"; | |
368 | + | |
369 | + #address-cells = <0>; | |
370 | + #size-cells = <1>; | |
371 | + phy_int { | |
372 | + reg = <0x6>; | |
373 | + interrupts-extended = <&gpio1 25 GPIO_ACTIVE_LOW>; | |
374 | + }; | |
375 | +}; | |
376 | + | |
377 | +&hdmi_cec { | |
378 | + pinctrl-names = "default"; | |
379 | + pinctrl-0 = <&pinctrl_hdmi_cec>; | |
380 | + status = "okay"; | |
381 | +}; | |
382 | + | |
383 | +&hdmi_core { | |
384 | + ipu_id = <0>; | |
385 | + disp_id = <0>; | |
386 | + status = "okay"; | |
387 | +}; | |
388 | + | |
389 | +&hdmi_video { | |
390 | + fsl,phy_reg_vlev = <0x0294>; | |
391 | + fsl,phy_reg_cksymtx = <0x800d>; | |
392 | + status = "okay"; | |
393 | +}; | |
394 | + | |
395 | +&i2c1 { | |
396 | + clock-frequency = <100000>; | |
397 | + pinctrl-names = "default"; | |
398 | + pinctrl-0 = <&pinctrl_i2c1>; | |
399 | + status = "okay"; | |
400 | + | |
401 | + sgtl5000: sgtl5000@0a { | |
402 | + compatible = "fsl,sgtl5000"; | |
403 | + pinctrl-names = "default"; | |
404 | + pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; | |
405 | + reg = <0x0a>; | |
406 | + clocks = <&clks 201>; | |
407 | + VDDA-supply = <®_3p3v>; | |
408 | + VDDD-supply = <®_1p2v>; | |
409 | + VDDIO-supply = <®_3p3v>; | |
410 | + }; | |
411 | +}; | |
412 | + | |
413 | +&i2c2 { | |
414 | + clock-frequency = <100000>; | |
415 | + pinctrl-names = "default"; | |
416 | + pinctrl-0 = <&pinctrl_i2c2>; | |
417 | + status = "okay"; | |
418 | + | |
419 | + hdmi_i2c: edid@50 { | |
420 | + compatible = "fsl,imx6-hdmi-i2c"; | |
421 | + reg = <0x50>; | |
422 | + }; | |
423 | + | |
424 | + rtc: ds1339@68 { | |
425 | + compatible = "dallas,ds1339"; | |
426 | + reg = <0x68>; | |
427 | + }; | |
428 | + | |
429 | +}; | |
430 | + | |
431 | +&i2c3 { | |
432 | + clock-frequency = <100000>; | |
433 | + pinctrl-names = "default"; | |
434 | + pinctrl-0 = <&pinctrl_i2c3>; | |
435 | + status = "okay"; | |
436 | + | |
437 | + tsc2007: tsc2007@48 { | |
438 | + compatible = "ti,tsc2007"; | |
439 | + reg = <0x48>; | |
440 | + pinctrl-names = "default"; | |
441 | + pinctrl-0 = <&pinctrl_i2c2_tsc2007>; | |
442 | + interrupt-parent = <&gpio6>; | |
443 | + interrupts = <9 0>; | |
444 | + gpios = <&gpio6 9 0>; | |
445 | + ti,x-plate-ohms = <470>; | |
446 | + ti,poll-period = <10>; | |
447 | + }; | |
448 | +}; | |
449 | + | |
450 | +&ldb { | |
451 | + split-mode = <1>; | |
452 | + status = "okay"; | |
453 | + | |
454 | + lvds-channel@0 { | |
455 | + fsl,data-mapping = "spwg"; | |
456 | + fsl,data-width = <18>; | |
457 | + status = "okay"; | |
458 | + primary; | |
459 | + | |
460 | + display-timings { | |
461 | + native-mode = <&timing0>; | |
462 | + timing0: LDB-LP133WD2 { | |
463 | + clock-frequency = <92592000>; /* 48870000 96870000*/ | |
464 | + hactive = <1600>; | |
465 | + vactive = <900>; | |
466 | + hback-porch = <54>; | |
467 | + hfront-porch = <24>; | |
468 | + vback-porch = <7>; | |
469 | + vfront-porch = <2>; | |
470 | + hsync-len = <24>; | |
471 | + vsync-len = <3>; | |
472 | + }; | |
473 | + }; | |
474 | + }; | |
475 | +}; | |
476 | + | |
477 | +&pwm1 { | |
478 | + pinctrl-names = "default"; | |
479 | + pinctrl-0 = <&pinctrl_pwm1>; | |
480 | + status = "okay"; | |
481 | +}; | |
482 | + | |
483 | +&ssi1 { | |
484 | + fsl,mode = "i2s-slave"; | |
485 | + status = "okay"; | |
486 | +}; | |
487 | + | |
488 | +&uart1 { | |
489 | + pinctrl-names = "default"; | |
490 | + pinctrl-0 = <&pinctrl_uart1>; | |
491 | + status = "okay"; | |
492 | +}; | |
493 | + | |
494 | +&uart2 { | |
495 | + pinctrl-names = "default"; | |
496 | + pinctrl-0 = <&pinctrl_uart2>; | |
497 | + status = "okay"; | |
498 | +}; | |
499 | + | |
500 | +&uart3 { | |
501 | + pinctrl-names = "default"; | |
502 | + pinctrl-0 = <&pinctrl_uart3>; | |
503 | + status = "okay"; | |
504 | +}; | |
505 | + | |
506 | +&uart4 { | |
507 | + pinctrl-names = "default"; | |
508 | + pinctrl-0 = <&pinctrl_uart4>; | |
509 | + status = "okay"; | |
510 | +}; | |
511 | + | |
512 | +&usbh1 { | |
513 | + disable-over-current; | |
514 | + status = "okay"; | |
515 | +}; | |
516 | + | |
517 | +&usbotg { | |
518 | + vbus-supply = <®_usbotg_vbus>; | |
519 | + pinctrl-names = "default"; | |
520 | + pinctrl-0 = <&pinctrl_usbotg>; | |
521 | + disable-over-current; | |
522 | + status = "okay"; | |
523 | +}; | |
524 | + | |
525 | +&usdhc3 { | |
526 | + pinctrl-names = "default"; | |
527 | + pinctrl-0 = <&pinctrl_usdhc3>; | |
528 | + bus-width = <4>; | |
529 | + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; | |
530 | + wp-gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; | |
531 | + vmmc-supply = <®_3p3v>; | |
532 | + status = "okay"; | |
533 | +}; | |
534 | + | |
535 | +&usdhc4 { | |
536 | + pinctrl-names = "default"; | |
537 | + pinctrl-0 = <&pinctrl_usdhc4>; | |
538 | + bus-width = <8>; | |
539 | + non-removable; | |
540 | + vmmc-supply = <®_3p3v>; | |
541 | + keep-power-in-suspend; | |
542 | + status = "okay"; | |
543 | +}; | ... | ... |
kernel/linux-imx6_3.14.28/arch/arm/boot/dts/imx6s-prime-oven_jig.dts
... | ... | @@ -0,0 +1,152 @@ |
1 | +/* | |
2 | + * Copyright 2013 Boundary Devices | |
3 | + * Copyright 2012 Freescale Semiconductor, Inc. | |
4 | + * Copyright 2011 Linaro Ltd. | |
5 | + * | |
6 | + * The code contained herein is licensed under the GNU General Public | |
7 | + * License. You may obtain a copy of the GNU General Public License | |
8 | + * Version 2 or later at the following locations: | |
9 | + * | |
10 | + * http://www.opensource.org/licenses/gpl-license.html | |
11 | + * http://www.gnu.org/copyleft/gpl.html | |
12 | + */ | |
13 | + | |
14 | +/dts-v1/; | |
15 | + | |
16 | +#include <dt-bindings/interrupt-controller/irq.h> | |
17 | +#include "imx6dl.dtsi" | |
18 | +#include "imx6qdl-prime-oven_jig.dtsi" | |
19 | + | |
20 | +/ { | |
21 | + model = "Freescale i.MX6 Solo/DualLite Prime Oven Device Board(PFUZE100)"; | |
22 | + compatible = "fsl,imx6dl-prime-oven", "fsl,imx6dl"; | |
23 | + | |
24 | + prime_encoder@0 { | |
25 | + compatible = "prime-encoder"; | |
26 | + gpios = <&gpio6 11 1>, <&gpio6 10 1>, <&gpio6 14 1>; | |
27 | + /* add larche@falinux.com - private value */ | |
28 | + prime-encoder,button; | |
29 | + prime-encoder,left_code = <KEY_F1>; | |
30 | + prime-encoder,right_code = <KEY_F3>; | |
31 | + prime-encoder,center_code = <KEY_F2>; | |
32 | + }; | |
33 | +}; | |
34 | + | |
35 | +&mxcfb1 { | |
36 | + status = "okay"; | |
37 | +}; | |
38 | + | |
39 | +&mxcfb2 { | |
40 | + status = "okay"; | |
41 | +}; | |
42 | + | |
43 | +&ldb { | |
44 | + lvds-channel@0 { | |
45 | + crtc = "ipu1-di1"; | |
46 | + }; | |
47 | +}; | |
48 | + | |
49 | +&i2c2 { | |
50 | + pmic: pfuze100@08 { | |
51 | + compatible = "fsl,pfuze100"; | |
52 | + reg = <0x08>; | |
53 | + | |
54 | + regulators { | |
55 | + sw1a_reg: sw1ab { | |
56 | + regulator-min-microvolt = <300000>; | |
57 | + regulator-max-microvolt = <1875000>; | |
58 | + regulator-boot-on; | |
59 | + regulator-always-on; | |
60 | + regulator-ramp-delay = <6250>; | |
61 | + }; | |
62 | + | |
63 | + sw1c_reg: sw1c { | |
64 | + regulator-min-microvolt = <300000>; | |
65 | + regulator-max-microvolt = <1875000>; | |
66 | + regulator-boot-on; | |
67 | + regulator-always-on; | |
68 | + regulator-ramp-delay = <6250>; | |
69 | + }; | |
70 | + | |
71 | + sw2_reg: sw2 { | |
72 | + regulator-min-microvolt = <800000>; | |
73 | + regulator-max-microvolt = <3300000>; | |
74 | + regulator-boot-on; | |
75 | + regulator-always-on; | |
76 | + }; | |
77 | + | |
78 | + sw3a_reg: sw3a { | |
79 | + regulator-min-microvolt = <400000>; | |
80 | + regulator-max-microvolt = <1975000>; | |
81 | + regulator-boot-on; | |
82 | + regulator-always-on; | |
83 | + }; | |
84 | + | |
85 | + sw3b_reg: sw3b { | |
86 | + regulator-min-microvolt = <400000>; | |
87 | + regulator-max-microvolt = <1975000>; | |
88 | + regulator-boot-on; | |
89 | + regulator-always-on; | |
90 | + }; | |
91 | + | |
92 | + sw4_reg: sw4 { | |
93 | + regulator-min-microvolt = <800000>; | |
94 | + regulator-max-microvolt = <3300000>; | |
95 | + }; | |
96 | + | |
97 | + swbst_reg: swbst { | |
98 | + regulator-min-microvolt = <5000000>; | |
99 | + regulator-max-microvolt = <5150000>; | |
100 | + }; | |
101 | + | |
102 | + snvs_reg: vsnvs { | |
103 | + regulator-min-microvolt = <1000000>; | |
104 | + regulator-max-microvolt = <3000000>; | |
105 | + regulator-boot-on; | |
106 | + regulator-always-on; | |
107 | + }; | |
108 | + | |
109 | + vref_reg: vrefddr { | |
110 | + regulator-boot-on; | |
111 | + regulator-always-on; | |
112 | + }; | |
113 | + | |
114 | + vgen1_reg: vgen1 { | |
115 | + regulator-min-microvolt = <800000>; | |
116 | + regulator-max-microvolt = <1550000>; | |
117 | + }; | |
118 | + | |
119 | + vgen2_reg: vgen2 { | |
120 | + regulator-min-microvolt = <800000>; | |
121 | + regulator-max-microvolt = <1550000>; | |
122 | + }; | |
123 | + | |
124 | + vgen3_reg: vgen3 { | |
125 | + regulator-min-microvolt = <1800000>; | |
126 | + regulator-max-microvolt = <3300000>; | |
127 | + }; | |
128 | + | |
129 | + vgen4_reg: vgen4 { | |
130 | + regulator-min-microvolt = <1800000>; | |
131 | + regulator-max-microvolt = <3300000>; | |
132 | + regulator-always-on; | |
133 | + }; | |
134 | + | |
135 | + vgen5_reg: vgen5 { | |
136 | + regulator-min-microvolt = <1800000>; | |
137 | + regulator-max-microvolt = <3300000>; | |
138 | + regulator-always-on; | |
139 | + }; | |
140 | + | |
141 | + vgen6_reg: vgen6 { | |
142 | + regulator-min-microvolt = <1800000>; | |
143 | + regulator-max-microvolt = <3300000>; | |
144 | + regulator-always-on; | |
145 | + }; | |
146 | + }; | |
147 | + }; | |
148 | +}; | |
149 | + | |
150 | +&pxp { | |
151 | + status = "okay"; | |
152 | +}; | ... | ... |
kernel/linux-imx6_3.14.28/arch/arm/configs/imx6s_prime_oven_defconfig
... | ... | @@ -210,6 +210,7 @@ CONFIG_SND=y |
210 | 210 | CONFIG_SND_SOC=y |
211 | 211 | CONFIG_SND_IMX_SOC=y |
212 | 212 | CONFIG_SND_SOC_IMX_SGTL5000=y |
213 | +CONFIG_SND_SOC_IMX_HDMI=y | |
213 | 214 | CONFIG_HIDRAW=y |
214 | 215 | CONFIG_UHID=y |
215 | 216 | CONFIG_HID_MULTITOUCH=y |
... | ... | @@ -223,6 +224,8 @@ CONFIG_USB_WDM=y |
223 | 224 | CONFIG_USB_STORAGE=y |
224 | 225 | CONFIG_USB_CHIPIDEA=y |
225 | 226 | CONFIG_USB_CHIPIDEA_HOST=y |
227 | +CONFIG_USB_SERIAL=y | |
228 | +CONFIG_USB_SERIAL_FTDI_SIO=y | |
226 | 229 | CONFIG_NOP_USB_XCEIV=y |
227 | 230 | CONFIG_USB_MXS_PHY=y |
228 | 231 | CONFIG_MMC=y | ... | ... |