에프에이리눅스 / 1611_0007_prime_oven

tgpio_imx6q-iomux.h 342 KB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598 4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682 4683 4684 4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930 4931 4932 4933 4934 4935 4936 4937 4938 4939 4940 4941 4942 4943 4944 4945 4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971 4972 4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983 4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026 5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 5062 5063 5064 5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101 5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116 5117 5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139 5140 5141 5142 5143 5144 5145 5146 5147 5148 5149 5150 5151 5152 5153 5154 5155 5156 5157 5158 5159 5160 5161 5162 5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194 5195 5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216 5217 5218 5219 5220 5221 5222 5223 5224 5225 5226 5227 5228 5229 5230 5231 5232 5233 5234 5235 5236 5237 5238 5239 5240 5241 5242 5243 5244 5245 5246 5247 5248 5249 5250 5251 5252 5253 5254 5255 5256 5257 5258 5259 5260 5261 5262 5263 5264 5265 5266 5267 5268 5269 5270 5271 5272 5273 5274 5275 5276 5277 5278 5279 5280 5281 5282 5283 5284 5285 5286 5287 5288 5289 5290 5291 5292 5293 5294 5295 5296 5297 5298 5299 5300 5301 5302 5303 5304 5305 5306 5307 5308 5309 5310 5311 5312 5313 5314 5315 5316 5317 5318 5319 5320 5321 5322 5323 5324 5325 5326 5327 5328 5329 5330 5331 5332 5333 5334 5335 5336 5337 5338 5339 5340 5341 5342 5343 5344 5345 5346 5347 5348 5349 5350 5351 5352 5353 5354 5355 5356 5357 5358 5359 5360 5361 5362 5363 5364 5365 5366 5367 5368 5369 5370 5371 5372 5373 5374 5375 5376 5377 5378 5379 5380 5381 5382 5383 5384 5385 5386 5387 5388 5389 5390 5391 5392 5393 5394 5395 5396 5397 5398 5399 5400 5401 5402 5403 5404 5405 5406 5407 5408 5409 5410 5411 5412 5413 5414 5415 5416 5417 5418 5419 5420 5421 5422 5423 5424 5425 5426 5427 5428 5429 5430 5431 5432 5433 5434 5435 5436 5437 5438 5439 5440 5441 5442 5443 5444 5445 5446 5447 5448 5449 5450 5451 5452 5453 5454 5455 5456 5457 5458 5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469 5470 5471 5472 5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491 5492 5493 5494 5495 5496 5497 5498 5499 5500 5501 5502 5503 5504 5505 5506 5507 5508 5509 5510 5511 5512 5513 5514 5515 5516 5517 5518 5519 5520 5521 5522 5523 5524 5525 5526 5527 5528 5529 5530 5531 5532 5533 5534 5535 5536 5537 5538 5539 5540 5541 5542 5543 5544 5545 5546 5547 5548 5549 5550 5551 5552 5553 5554 5555 5556 5557 5558 5559 5560 5561 5562 5563 5564 5565 5566 5567 5568 5569 5570 5571 5572 5573 5574 5575 5576 5577 5578 5579 5580 5581 5582 5583 5584 5585 5586 5587 5588 5589 5590 5591 5592 5593 5594 5595 5596 5597 5598 5599 5600 5601 5602 5603 5604 5605 5606 5607 5608 5609 5610 5611 5612 5613 5614 5615 5616 5617 5618 5619 5620 5621 5622 5623 5624 5625 5626 5627 5628 5629 5630 5631 5632 5633 5634 5635 5636 5637 5638 5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652 5653 5654 5655 5656 5657 5658 5659 5660 5661 5662 5663 5664 5665 5666 5667 5668 5669 5670 5671 5672 5673 5674 5675 5676 5677 5678 5679 5680 5681 5682 5683 5684 5685 5686 5687 5688 5689 5690 5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701 5702 5703 5704 5705 5706 5707 5708 5709 5710 5711 5712 5713 5714 5715 5716 5717 5718 5719 5720 5721 5722 5723 5724 5725 5726 5727 5728 5729 5730 5731 5732 5733 5734 5735 5736 5737 5738 5739 5740 5741 5742 5743 5744 5745 5746 5747 5748 5749 5750 5751 5752 5753 5754 5755 5756 5757 5758 5759 5760 5761 5762 5763 5764 5765 5766 5767 5768 5769 5770 5771 5772 5773 5774 5775 5776 5777 5778 5779 5780 5781 5782 5783 5784 5785 5786 5787 5788 5789 5790 5791 5792 5793 5794 5795 5796 5797 5798 5799 5800 5801 5802 5803 5804 5805 5806 5807 5808 5809 5810 5811 5812 5813 5814 5815 5816 5817 5818 5819 5820 5821 5822 5823 5824 5825 5826 5827 5828 5829 5830 5831 5832 5833 5834 5835 5836 5837 5838 5839 5840 5841 5842 5843 5844 5845 5846 5847 5848 5849 5850 5851 5852 5853 5854 5855 5856 5857 5858 5859 5860 5861 5862 5863 5864 5865 5866 5867 5868 5869 5870 5871 5872 5873 5874 5875 5876 5877 5878 5879 5880 5881 5882 5883 5884 5885 5886 5887 5888 5889 5890 5891 5892 5893 5894 5895 5896 5897 5898 5899 5900 5901 5902 5903 5904 5905 5906 5907 5908 5909 5910 5911 5912 5913 5914 5915 5916 5917 5918 5919 5920 5921 5922 5923 5924 5925 5926 5927 5928 5929 5930 5931 5932 5933 5934 5935 5936 5937 5938 5939 5940 5941 5942 5943 5944 5945 5946 5947 5948 5949 5950 5951 5952 5953 5954 5955 5956 5957 5958 5959 5960 5961 5962 5963 5964 5965 5966 5967 5968 5969 5970 5971 5972 5973 5974 5975 5976 5977 5978 5979 5980 5981 5982 5983 5984 5985 5986 5987 5988 5989 5990 5991 5992 5993 5994 5995 5996 5997 5998 5999 6000 6001 6002 6003 6004 6005 6006 6007 6008 6009 6010 6011 6012 6013 6014 6015 6016 6017 6018 6019 6020 6021 6022 6023 6024 6025 6026 6027 6028 6029 6030 6031 6032 6033 6034 6035 6036 6037 6038 6039 6040 6041 6042 6043 6044 6045 6046 6047 6048 6049 6050 6051 6052 6053 6054 6055 6056 6057 6058 6059 6060 6061 6062 6063 6064 6065 6066 6067 6068 6069 6070 6071 6072 6073 6074 6075 6076 6077 6078 6079 6080 6081 6082 6083 6084 6085 6086 6087 6088 6089 6090 6091 6092 6093 6094 6095 6096 6097 6098 6099 6100 6101 6102 6103 6104 6105 6106 6107 6108 6109 6110 6111 6112 6113 6114 6115 6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128 6129 6130 6131 6132 6133 6134 6135 6136 6137 6138 6139 6140 6141 6142 6143 6144 6145 6146 6147 6148 6149 6150 6151 6152 6153 6154 6155 6156 6157 6158 6159 6160 6161 6162 6163 6164 6165 6166 6167 6168 6169 6170 6171 6172 6173 6174 6175 6176 6177 6178 6179 6180 6181 6182 6183 6184 6185 6186 6187 6188 6189 6190 6191 6192 6193 6194 6195 6196 6197 6198 6199 6200 6201 6202 6203 6204 6205 6206 6207 6208 6209 6210 6211 6212 6213 6214 6215 6216 6217 6218 6219 6220 6221 6222 6223 6224 6225 6226 6227 6228 6229 6230 6231 6232 6233 6234 6235 6236 6237 6238 6239 6240 6241 6242 6243 6244 6245 6246 6247 6248 6249 6250 6251 6252 6253 6254 6255 6256 6257 6258 6259 6260 6261 6262 6263 6264 6265 6266 6267 6268 6269 6270 6271 6272 6273 6274 6275 6276 6277 6278 6279 6280 6281 6282 6283 6284 6285 6286 6287 6288 6289 6290 6291 6292 6293 6294 6295 6296 6297 6298 6299 6300 6301 6302 6303 6304 6305 6306 6307 6308 6309 6310 6311 6312 6313 6314 6315 6316 6317 6318 6319 6320 6321 6322 6323 6324 6325 6326 6327 6328 6329 6330 6331 6332 6333 6334 6335 6336 6337 6338 6339 6340 6341 6342 6343 6344 6345 6346 6347 6348 6349 6350 6351 6352 6353 6354 6355 6356 6357 6358 6359 6360 6361 6362 6363 6364 6365 6366 6367 6368 6369 6370 6371 6372 6373 6374 6375 6376 6377 6378 6379 6380 6381 6382 6383 6384 6385 6386 6387 6388 6389 6390 6391 6392 6393 6394 6395 6396 6397 6398 6399 6400 6401 6402 6403 6404 6405 6406 6407 6408 6409 6410 6411 6412 6413 6414 6415 6416 6417 6418 6419 6420 6421 6422 6423 6424 6425 6426 6427 6428 6429 6430 6431 6432 6433 6434 6435 6436 6437 6438 6439 6440 6441 6442 6443 6444 6445 6446 6447 6448 6449 6450 6451 6452 6453 6454 6455 6456 6457 6458 6459 6460 6461 6462 6463 6464 6465 6466 6467 6468 6469 6470 6471 6472 6473 6474 6475 6476 6477 6478 6479 6480 6481 6482 6483 6484 6485 6486 6487 6488 6489 6490 6491 6492 6493 6494 6495 6496 6497 6498 6499 6500 6501 6502 6503 6504 6505 6506 6507 6508 6509 6510 6511 6512 6513 6514 6515 6516 6517 6518 6519 6520 6521 6522 6523 6524 6525 6526 6527 6528 6529 6530 6531 6532 6533 6534 6535 6536 6537 6538 6539 6540 6541 6542 6543 6544 6545 6546 6547 6548 6549 6550 6551 6552 6553 6554 6555 6556 6557 6558 6559 6560 6561 6562 6563 6564 6565 6566 6567 6568 6569 6570 6571 6572 6573 6574 6575 6576 6577 6578 6579 6580 6581 6582 6583 6584 6585 6586 6587 6588 6589 6590 6591 6592 6593 6594 6595 6596 6597 6598 6599 6600 6601 6602 6603 6604 6605 6606 6607 6608 6609 6610 6611 6612 6613 6614 6615 6616 6617 6618 6619 6620 6621 6622 6623 6624 6625 6626 6627 6628 6629 6630 6631 6632 6633 6634 6635 6636 6637 6638 6639 6640 6641 6642 6643 6644 6645 6646 6647 6648 6649 6650 6651 6652 6653 6654 6655 6656 6657 6658 6659 6660 6661 6662 6663 6664 6665 6666 6667 6668 6669 6670 6671 6672 6673 6674 6675 6676 6677 6678 6679 6680 6681 6682 6683 6684 6685 6686 6687 6688 6689 6690 6691 6692 6693 6694 6695 6696 6697 6698 6699 6700 6701 6702 6703 6704 6705 6706 6707 6708 6709 6710 6711 6712 6713 6714 6715 6716 6717 6718 6719 6720 6721 6722 6723 6724 6725 6726 6727 6728 6729 6730 6731 6732 6733 6734 6735 6736 6737 6738 6739 6740 6741 6742 6743 6744 6745 6746 6747 6748 6749 6750 6751 6752 6753 6754 6755 6756 6757 6758 6759 6760 6761 6762 6763 6764 6765 6766 6767 6768 6769 6770 6771 6772 6773 6774 6775 6776 6777 6778 6779 6780 6781 6782 6783 6784 6785 6786 6787 6788 6789 6790 6791 6792 6793 6794 6795 6796 6797 6798 6799 6800 6801 6802 6803 6804 6805 6806 6807 6808 6809 6810 6811 6812 6813 6814 6815 6816 6817 6818 6819 6820 6821 6822 6823 6824 6825 6826 6827 6828 6829 6830 6831 6832 6833 6834 6835 6836 6837 6838 6839 6840 6841 6842 6843 6844 6845 6846 6847 6848 6849 6850 6851 6852 6853 6854 6855 6856 6857 6858 6859 6860 6861 6862 6863 6864 6865 6866 6867 6868 6869 6870 6871 6872 6873 6874 6875 6876 6877 6878 6879 6880 6881 6882 6883 6884 6885 6886 6887 6888 6889 6890 6891 6892 6893 6894 6895 6896 6897 6898 6899 6900 6901 6902 6903 6904 6905 6906 6907 6908 6909 6910 6911 6912 6913 6914 6915 6916 6917 6918 6919 6920 6921 6922 6923 6924 6925 6926 6927 6928 6929 6930 6931 6932 6933 6934 6935 6936 6937 6938 6939 6940 6941 6942 6943 6944 6945 6946 6947 6948 6949 6950 6951 6952 6953 6954 6955 6956 6957 6958 6959 6960 6961 6962 6963 6964 6965 6966 6967 6968 6969 6970 6971 6972 6973 6974 6975 6976 6977 6978 6979 6980 6981 6982 6983 6984 6985 6986 6987 6988 6989 6990 6991 6992 6993 6994 6995 6996 6997 6998 6999 7000 7001 7002 7003 7004 7005 7006 7007 7008 7009 7010 7011 7012 7013 7014 7015 7016 7017 7018 7019 7020 7021 7022 7023 7024 7025 7026 7027 7028 7029 7030 7031 7032 7033 7034 7035 7036 7037 7038 7039 7040 7041 7042 7043 7044 7045 7046 7047 7048 7049 7050 7051 7052 7053 7054 7055 7056 7057 7058 7059 7060 7061 7062 7063 7064 7065 7066 7067 7068 7069 7070 7071 7072 7073 7074 7075 7076 7077 7078 7079 7080 7081 7082 7083 7084 7085 7086 7087 7088 7089 7090 7091 7092 7093 7094 7095 7096 7097 7098 7099 7100 7101 7102 7103 7104 7105 7106 7107 7108 7109 7110 7111 7112 7113 7114 7115 7116 7117 7118 7119 7120 7121 7122 7123 7124 7125 7126 7127 7128 7129 7130 7131 7132 7133 7134 7135 7136 7137 7138 7139 7140 7141 7142 7143 7144 7145 7146 7147 7148 7149 7150 7151 7152 7153 7154 7155 7156 7157 7158 7159 7160 7161 7162 7163 7164 7165 7166 7167 7168 7169 7170 7171 7172 7173 7174 7175 7176 7177 7178 7179 7180 7181 7182 7183 7184 7185 7186 7187 7188 7189 7190 7191 7192 7193 7194 7195 7196 7197 7198 7199 7200 7201 7202 7203 7204 7205 7206 7207 7208 7209 7210 7211 7212 7213 7214 7215 7216 7217 7218 7219 7220 7221 7222 7223 7224 7225 7226 7227 7228 7229 7230 7231 7232 7233 7234 7235 7236 7237 7238 7239 7240 7241 7242 7243 7244 7245 7246 7247 7248 7249 7250 7251 7252 7253 7254 7255 7256 7257 7258 7259 7260 7261 7262 7263 7264 7265 7266 7267 7268 7269 7270 7271 7272 7273 7274 7275 7276 7277 7278 7279 7280 7281 7282 7283 7284 7285 7286 7287 7288 7289 7290 7291 7292 7293 7294 7295 7296 7297 7298 7299 7300 7301 7302 7303 7304 7305 7306 7307 7308 7309 7310 7311 7312 7313 7314 7315 7316 7317 7318 7319 7320 7321 7322 7323 7324 7325 7326 7327 7328 7329 7330 7331 7332 7333 7334 7335 7336 7337 7338 7339 7340 7341 7342 7343 7344 7345 7346 7347 7348 7349 7350 7351 7352 7353 7354 7355 7356 7357 7358 7359 
/*
 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.

 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.

 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 *
 * Auto Generate file, please don't edit it
 *
 */

#ifndef __MACH_IOMUX_MX6Q_H__
#define __MACH_IOMUX_MX6Q_H__

#include <tgpio_imx6q.h>

/*
 * various IOMUX alternate output functions (1-7)
 */
typedef enum iomux_config {
	IOMUX_CONFIG_ALT0,
	IOMUX_CONFIG_ALT1,
	IOMUX_CONFIG_ALT2,
	IOMUX_CONFIG_ALT3,
	IOMUX_CONFIG_ALT4,
	IOMUX_CONFIG_ALT5,
	IOMUX_CONFIG_ALT6,
	IOMUX_CONFIG_ALT7,
	IOMUX_CONFIG_GPIO,      /* added to help user use GPIO mode */
} iomux_pin_cfg_t;

#define NON_MUX_I       0x3FF
#define NON_PAD_I       0x7FF
#define MX6Q_CCM_CLK0_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |	\
		PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |	\
		PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

#define MX6Q_HIGH_DRV	(PAD_CTL_DSE_120ohm)
#define MX6Q_UART_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |	\
		PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
		PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

#define MX6Q_USDHC_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |	\
		PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |	\
		PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

#define MX6Q_USDHC_PAD_CTRL_100MHZ	(PAD_CTL_PKE | PAD_CTL_PUE |	\
		PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED |	\
		PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

#define MX6Q_USDHC_PAD_CTRL_200MHZ	(PAD_CTL_PKE | PAD_CTL_PUE |	\
		PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH |	\
		PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

#define MX6Q_ENET_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |	\
		PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
		PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

#define MX6Q_DISP_PAD_CLT	MX6Q_HIGH_DRV
#define MX6Q_I2C_PAD_CTRL      (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
		PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_40ohm | \
		PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_SPEED_MED)

#define MX6Q_ESAI_PAD_CTRL	(PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
		PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)

#define MX6Q_GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define MX6Q_GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
#define MX6Q_GPMI_PAD_CTRL2 (MX6Q_GPMI_PAD_CTRL0 | MX6Q_GPMI_PAD_CTRL1)

#define MX6Q_SPDIF_OUT_PAD_CTRL (PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
#define MX6Q_USB_HSIC_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE |	\
				PAD_CTL_DSE_40ohm)

#define MX6Q_ECSPI_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
		PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

#define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1				\
		IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0				\
		IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0)
#define _MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2			\
		IOMUX_PAD(0x0360, 0x004C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS			\
		IOMUX_PAD(0x0360, 0x004C, 3, 0x07C8, 0, 0)
#define _MX6Q_PAD_SD2_DAT1__KPP_COL_7				\
		IOMUX_PAD(0x0360, 0x004C, 4, 0x08F0, 0, 0)
#define _MX6Q_PAD_SD2_DAT1__GPIO_1_14				\
		IOMUX_PAD(0x0360, 0x004C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT1__CCM_WAIT				\
		IOMUX_PAD(0x0360, 0x004C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0		\
		IOMUX_PAD(0x0360, 0x004C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD2_DAT2__USDHC2_DAT2				\
		IOMUX_PAD(0x0364, 0x0050, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT2__ECSPI5_SS1				\
		IOMUX_PAD(0x0364, 0x0050, 1, 0x0838, 0, 0)
#define _MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3			\
		IOMUX_PAD(0x0364, 0x0050, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD			\
		IOMUX_PAD(0x0364, 0x0050, 3, 0x07B8, 0, 0)
#define _MX6Q_PAD_SD2_DAT2__KPP_ROW_6				\
		IOMUX_PAD(0x0364, 0x0050, 4, 0x08F8, 0, 0)
#define _MX6Q_PAD_SD2_DAT2__GPIO_1_13				\
		IOMUX_PAD(0x0364, 0x0050, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT2__CCM_STOP				\
		IOMUX_PAD(0x0364, 0x0050, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1		\
		IOMUX_PAD(0x0364, 0x0050, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD2_DAT0__USDHC2_DAT0				\
		IOMUX_PAD(0x0368, 0x0054, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT0__ECSPI5_MISO				\
		IOMUX_PAD(0x0368, 0x0054, 1, 0x082C, 0, 0)
#define _MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD			\
		IOMUX_PAD(0x0368, 0x0054, 3, 0x07B4, 0, 0)
#define _MX6Q_PAD_SD2_DAT0__KPP_ROW_7				\
		IOMUX_PAD(0x0368, 0x0054, 4, 0x08FC, 0, 0)
#define _MX6Q_PAD_SD2_DAT0__GPIO_1_15				\
		IOMUX_PAD(0x0368, 0x0054, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT			\
		IOMUX_PAD(0x0368, 0x0054, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2		\
		IOMUX_PAD(0x0368, 0x0054, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA			\
		IOMUX_PAD(0x036C, 0x0058, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC			\
		IOMUX_PAD(0x036C, 0x0058, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK			\
		IOMUX_PAD(0x036C, 0x0058, 2, 0x0918, 0, 0)
#define _MX6Q_PAD_RGMII_TXC__GPIO_6_19				\
		IOMUX_PAD(0x036C, 0x0058, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0		\
		IOMUX_PAD(0x036C, 0x0058, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT		\
		IOMUX_PAD(0x036C, 0x0058, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY		\
		IOMUX_PAD(0x0370, 0x005C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0			\
		IOMUX_PAD(0x0370, 0x005C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TD0__GPIO_6_20				\
		IOMUX_PAD(0x0370, 0x005C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1		\
		IOMUX_PAD(0x0370, 0x005C, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG		\
		IOMUX_PAD(0x0374, 0x0060, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1			\
		IOMUX_PAD(0x0374, 0x0060, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TD1__GPIO_6_21				\
		IOMUX_PAD(0x0374, 0x0060, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2		\
		IOMUX_PAD(0x0374, 0x0060, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP			\
		IOMUX_PAD(0x0374, 0x0060, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA		\
		IOMUX_PAD(0x0378, 0x0064, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2			\
		IOMUX_PAD(0x0378, 0x0064, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TD2__GPIO_6_22				\
		IOMUX_PAD(0x0378, 0x0064, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3		\
		IOMUX_PAD(0x0378, 0x0064, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP			\
		IOMUX_PAD(0x0378, 0x0064, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE		\
		IOMUX_PAD(0x037C, 0x0068, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3			\
		IOMUX_PAD(0x037C, 0x0068, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TD3__GPIO_6_23				\
		IOMUX_PAD(0x037C, 0x0068, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4		\
		IOMUX_PAD(0x037C, 0x0068, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA			\
		IOMUX_PAD(0x0380, 0x006C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL		\
		IOMUX_PAD(0x0380, 0x006C, 1, 0x0858, 0, 0)
#define _MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24			\
		IOMUX_PAD(0x0380, 0x006C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5	\
		IOMUX_PAD(0x0380, 0x006C, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY		\
		IOMUX_PAD(0x0384, 0x0070, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0			\
		IOMUX_PAD(0x0384, 0x0070, 1, 0x0848, 0, 0)
#define _MX6Q_PAD_RGMII_RD0__GPIO_6_25				\
		IOMUX_PAD(0x0384, 0x0070, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6		\
		IOMUX_PAD(0x0384, 0x0070, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE		\
		IOMUX_PAD(0x0388, 0x0074, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL		\
		IOMUX_PAD(0x0388, 0x0074, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26			\
		IOMUX_PAD(0x0388, 0x0074, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7	\
		IOMUX_PAD(0x0388, 0x0074, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT	\
		IOMUX_PAD(0x0388, 0x0074, 7, 0x083C, 0, 0)

#define _MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG		\
		IOMUX_PAD(0x038C, 0x0078, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1			\
		IOMUX_PAD(0x038C, 0x0078, 1, 0x084C, 0, 0)
#define _MX6Q_PAD_RGMII_RD1__GPIO_6_27				\
		IOMUX_PAD(0x038C, 0x0078, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8		\
		IOMUX_PAD(0x038C, 0x0078, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_RD1__SJC_FAIL				\
		IOMUX_PAD(0x038C, 0x0078, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA		\
		IOMUX_PAD(0x0390, 0x007C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2			\
		IOMUX_PAD(0x0390, 0x007C, 1, 0x0850, 0, 0)
#define _MX6Q_PAD_RGMII_RD2__GPIO_6_28				\
		IOMUX_PAD(0x0390, 0x007C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9		\
		IOMUX_PAD(0x0390, 0x007C, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE		\
		IOMUX_PAD(0x0394, 0x0080, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3			\
		IOMUX_PAD(0x0394, 0x0080, 1, 0x0854, 0, 0)
#define _MX6Q_PAD_RGMII_RD3__GPIO_6_29				\
		IOMUX_PAD(0x0394, 0x0080, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10		\
		IOMUX_PAD(0x0394, 0x0080, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE			\
		IOMUX_PAD(0x0398, 0x0084, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC			\
		IOMUX_PAD(0x0398, 0x0084, 1, 0x0844, 0, 0)
#define _MX6Q_PAD_RGMII_RXC__GPIO_6_30				\
		IOMUX_PAD(0x0398, 0x0084, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11		\
		IOMUX_PAD(0x0398, 0x0084, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25			\
		IOMUX_PAD(0x039C, 0x0088, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A25__ECSPI4_SS1				\
		IOMUX_PAD(0x039C, 0x0088, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A25__ECSPI2_RDY				\
		IOMUX_PAD(0x039C, 0x0088, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12			\
		IOMUX_PAD(0x039C, 0x0088, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS			\
		IOMUX_PAD(0x039C, 0x0088, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A25__GPIO_5_2				\
		IOMUX_PAD(0x039C, 0x0088, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE			\
		IOMUX_PAD(0x039C, 0x0088, 6, 0x088C, 0, 0)
#define _MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0		\
		IOMUX_PAD(0x039C, 0x0088, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2			\
		IOMUX_PAD(0x03A0, 0x008C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB2__ECSPI1_SS0				\
		IOMUX_PAD(0x03A0, 0x008C, 1, 0x0800, 0, 0)
#define _MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK			\
		IOMUX_PAD(0x03A0, 0x008C, 2, 0x07EC, 0, 0)
#define _MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19			\
		IOMUX_PAD(0x03A0, 0x008C, 3, 0x08D4, 0, 0)
#define _MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL			\
		IOMUX_PAD(0x03A0, 0x008C, 4, 0x0890, 0, 0)
#define _MX6Q_PAD_EIM_EB2__GPIO_2_30				\
		IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB2__I2C2_SCL				\
		IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0)
#define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30			\
		IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16			\
		IOMUX_PAD(0x03A4, 0x0090, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D16__ECSPI1_SCLK				\
		IOMUX_PAD(0x03A4, 0x0090, 1, 0x07F4, 0, 0)
#define _MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5			\
		IOMUX_PAD(0x03A4, 0x0090, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18			\
		IOMUX_PAD(0x03A4, 0x0090, 3, 0x08D0, 0, 0)
#define _MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA			\
		IOMUX_PAD(0x03A4, 0x0090, 4, 0x0894, 0, 0)
#define _MX6Q_PAD_EIM_D16__GPIO_3_16				\
		IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D16__I2C2_SDA				\
		IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0)

#define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17			\
		IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D17__ECSPI1_MISO				\
		IOMUX_PAD(0x03A8, 0x0094, 1, 0x07F8, 0, 0)
#define _MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6			\
		IOMUX_PAD(0x03A8, 0x0094, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK			\
		IOMUX_PAD(0x03A8, 0x0094, 3, 0x08E0, 0, 0)
#define _MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT			\
		IOMUX_PAD(0x03A8, 0x0094, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D17__GPIO_3_17				\
		IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D17__I2C3_SCL				\
		IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0)
#define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1		\
		IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18			\
		IOMUX_PAD(0x03AC, 0x0098, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D18__ECSPI1_MOSI				\
		IOMUX_PAD(0x03AC, 0x0098, 1, 0x07FC, 0, 0)
#define _MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7			\
		IOMUX_PAD(0x03AC, 0x0098, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17			\
		IOMUX_PAD(0x03AC, 0x0098, 3, 0x08CC, 0, 0)
#define _MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS			\
		IOMUX_PAD(0x03AC, 0x0098, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D18__GPIO_3_18				\
		IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D18__I2C3_SDA				\
		IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0)
#define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2		\
		IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19			\
		IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D19__ECSPI1_SS1				\
		IOMUX_PAD(0x03B0, 0x009C, 1, 0x0804, 0, 0)
#define _MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8			\
		IOMUX_PAD(0x03B0, 0x009C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16			\
		IOMUX_PAD(0x03B0, 0x009C, 3, 0x08C8, 0, 0)
#define _MX6Q_PAD_EIM_D19__UART1_CTS				\
		IOMUX_PAD(0x03B0, 0x009C, 4, 0x091C, 0, 0)
#define _MX6Q_PAD_EIM_D19__GPIO_3_19				\
		IOMUX_PAD(0x03B0, 0x009C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D19__EPIT1_EPITO				\
		IOMUX_PAD(0x03B0, 0x009C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP			\
		IOMUX_PAD(0x03B0, 0x009C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20			\
		IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D20__ECSPI4_SS0				\
		IOMUX_PAD(0x03B4, 0x00A0, 1, 0x0824, 0, 0)
#define _MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16			\
		IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15			\
		IOMUX_PAD(0x03B4, 0x00A0, 3, 0x08C4, 0, 0)
#define _MX6Q_PAD_EIM_D20__UART1_CTS				\
		IOMUX_PAD(0x03B4, 0x00A0, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D20__UART1_RTS				\
		IOMUX_PAD(0x03B4, 0x00A0, 4, 0x091C, 1, 0)
#define _MX6Q_PAD_EIM_D20__GPIO_3_20				\
		IOMUX_PAD(0x03B4, 0x00A0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D20__EPIT2_EPITO				\
		IOMUX_PAD(0x03B4, 0x00A0, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21			\
		IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D21__ECSPI4_SCLK				\
		IOMUX_PAD(0x03B8, 0x00A4, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17			\
		IOMUX_PAD(0x03B8, 0x00A4, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11			\
		IOMUX_PAD(0x03B8, 0x00A4, 3, 0x08B4, 0, 0)
#define _MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC			\
		IOMUX_PAD(0x03B8, 0x00A4, 4, 0x0944, 0, 0)
#define _MX6Q_PAD_EIM_D21__GPIO_3_21			\
		IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D21__I2C1_SCL			\
		IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0)
#define _MX6Q_PAD_EIM_D21__SPDIF_IN1			\
		IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0)

#define _MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22			\
		IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D22__ECSPI4_MISO				\
		IOMUX_PAD(0x03BC, 0x00A8, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1			\
		IOMUX_PAD(0x03BC, 0x00A8, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10			\
		IOMUX_PAD(0x03BC, 0x00A8, 3, 0x08B0, 0, 0)
#define _MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR			\
		IOMUX_PAD(0x03BC, 0x00A8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D22__GPIO_3_22				\
		IOMUX_PAD(0x03BC, 0x00A8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D22__SPDIF_OUT1				\
		IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE		\
		IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23			\
		IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS			\
		IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D23__UART3_CTS				\
		IOMUX_PAD(0x03C0, 0x00AC, 2, 0x092C, 0, 0)
#define _MX6Q_PAD_EIM_D23__UART1_DCD				\
		IOMUX_PAD(0x03C0, 0x00AC, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN			\
		IOMUX_PAD(0x03C0, 0x00AC, 4, 0x08D8, 0, 0)
#define _MX6Q_PAD_EIM_D23__GPIO_3_23				\
		IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2			\
		IOMUX_PAD(0x03C0, 0x00AC, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14			\
		IOMUX_PAD(0x03C0, 0x00AC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3			\
		IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB3__ECSPI4_RDY			\
		IOMUX_PAD(0x03C4, 0x00B0, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB3__UART3_CTS			\
		IOMUX_PAD(0x03C4, 0x00B0, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB3__UART3_RTS			\
		IOMUX_PAD(0x03C4, 0x00B0, 2, 0x092C, 1, 0)
#define _MX6Q_PAD_EIM_EB3__UART1_RI			\
		IOMUX_PAD(0x03C4, 0x00B0, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC		\
		IOMUX_PAD(0x03C4, 0x00B0, 4, 0x08DC, 0, 0)
#define _MX6Q_PAD_EIM_EB3__GPIO_2_31			\
		IOMUX_PAD(0x03C4, 0x00B0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3				\
		IOMUX_PAD(0x03C4, 0x00B0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31				\
		IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24				\
		IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D24__ECSPI4_SS2			\
		IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D24__UART3_TXD			\
		IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D24__UART3_RXD			\
		IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0)
#define _MX6Q_PAD_EIM_D24__ECSPI1_SS2			\
		IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0)
#define _MX6Q_PAD_EIM_D24__ECSPI2_SS2			\
		IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D24__GPIO_3_24			\
		IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS			\
		IOMUX_PAD(0x03C8, 0x00B4, 6, 0x07D8, 0, 0)
#define _MX6Q_PAD_EIM_D24__UART1_DTR			\
		IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25		\
		IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D25__ECSPI4_SS3			\
		IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D25__UART3_TXD			\
		IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D25__UART3_RXD			\
		IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0)
#define _MX6Q_PAD_EIM_D25__ECSPI1_SS3			\
		IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0)
#define _MX6Q_PAD_EIM_D25__ECSPI2_SS3			\
		IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D25__GPIO_3_25			\
		IOMUX_PAD(0x03CC, 0x00B8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC		\
		IOMUX_PAD(0x03CC, 0x00B8, 6, 0x07D4, 0, 0)
#define _MX6Q_PAD_EIM_D25__UART1_DSR			\
		IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26				\
		IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11				\
		IOMUX_PAD(0x03D0, 0x00BC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1				\
		IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14				\
		IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0)
#define _MX6Q_PAD_EIM_D26__UART2_TXD			\
		IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D26__UART2_RXD			\
		IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0)
#define _MX6Q_PAD_EIM_D26__GPIO_3_26			\
		IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D26__IPU1_SISG_2			\
		IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22			\
		IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27				\
		IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13				\
		IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0				\
		IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13				\
		IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0)
#define _MX6Q_PAD_EIM_D27__UART2_TXD			\
		IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D27__UART2_RXD			\
		IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0)
#define _MX6Q_PAD_EIM_D27__GPIO_3_27			\
		IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D27__IPU1_SISG_3			\
		IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23			\
		IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28				\
		IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D28__I2C1_SDA			\
		IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0)
#define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI			\
		IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12				\
		IOMUX_PAD(0x03D8, 0x00C4, 3, 0x08B8, 0, 0)
#define _MX6Q_PAD_EIM_D28__UART2_CTS			\
		IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D28__UART2_RTS			\
		IOMUX_PAD(0x03D8, 0x00C4, 4, 0x0924, 0, 0)
#define _MX6Q_PAD_EIM_D28__GPIO_3_28			\
		IOMUX_PAD(0x03D8, 0x00C4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG				\
		IOMUX_PAD(0x03D8, 0x00C4, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13				\
		IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29				\
		IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15				\
		IOMUX_PAD(0x03DC, 0x00C8, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D29__ECSPI4_SS0			\
		IOMUX_PAD(0x03DC, 0x00C8, 2, 0x0824, 1, 0)
#define _MX6Q_PAD_EIM_D29__UART2_CTS			\
		IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D29__UART2_RTS			\
		IOMUX_PAD(0x03DC, 0x00C8, 4, 0x0924, 1, 0)
#define _MX6Q_PAD_EIM_D29__GPIO_3_29			\
		IOMUX_PAD(0x03DC, 0x00C8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC		\
		IOMUX_PAD(0x03DC, 0x00C8, 6, 0x08E4, 0, 0)
#define _MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14				\
		IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30				\
		IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21			\
		IOMUX_PAD(0x03E0, 0x00CC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11				\
		IOMUX_PAD(0x03E0, 0x00CC, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3				\
		IOMUX_PAD(0x03E0, 0x00CC, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D30__UART3_CTS			\
		IOMUX_PAD(0x03E0, 0x00CC, 4, 0x092C, 2, 0)
#define _MX6Q_PAD_EIM_D30__GPIO_3_30			\
		IOMUX_PAD(0x03E0, 0x00CC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC		\
		IOMUX_PAD(0x03E0, 0x00CC, 6, 0x0948, 0, 0)
#define _MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0		\
		IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31				\
		IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20			\
		IOMUX_PAD(0x03E4, 0x00D0, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12				\
		IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2				\
		IOMUX_PAD(0x03E4, 0x00D0, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D31__UART3_CTS			\
		IOMUX_PAD(0x03E4, 0x00D0, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D31__UART3_RTS			\
		IOMUX_PAD(0x03E4, 0x00D0, 4, 0x092C, 3, 0)
#define _MX6Q_PAD_EIM_D31__GPIO_3_31			\
		IOMUX_PAD(0x03E4, 0x00D0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR			\
		IOMUX_PAD(0x03E4, 0x00D0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1		\
		IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24				\
		IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19			\
		IOMUX_PAD(0x03E8, 0x00D4, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19				\
		IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4, 1, 0)
#define _MX6Q_PAD_EIM_A24__IPU2_SISG_2			\
		IOMUX_PAD(0x03E8, 0x00D4, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A24__IPU1_SISG_2			\
		IOMUX_PAD(0x03E8, 0x00D4, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A24__GPIO_5_4			\
		IOMUX_PAD(0x03E8, 0x00D4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2		\
		IOMUX_PAD(0x03E8, 0x00D4, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A24__SRC_BT_CFG_24				\
		IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23				\
		IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18			\
		IOMUX_PAD(0x03EC, 0x00D8, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18				\
		IOMUX_PAD(0x03EC, 0x00D8, 2, 0x08D0, 1, 0)
#define _MX6Q_PAD_EIM_A23__IPU2_SISG_3			\
		IOMUX_PAD(0x03EC, 0x00D8, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A23__IPU1_SISG_3			\
		IOMUX_PAD(0x03EC, 0x00D8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A23__GPIO_6_6			\
		IOMUX_PAD(0x03EC, 0x00D8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3		\
		IOMUX_PAD(0x03EC, 0x00D8, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A23__SRC_BT_CFG_23				\
		IOMUX_PAD(0x03EC, 0x00D8, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22				\
		IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17			\
		IOMUX_PAD(0x03F0, 0x00DC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17				\
		IOMUX_PAD(0x03F0, 0x00DC, 2, 0x08CC, 1, 0)
#define _MX6Q_PAD_EIM_A22__GPIO_2_16			\
		IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A22__TPSMP_HDATA_0				\
		IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A22__SRC_BT_CFG_22				\
		IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21				\
		IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16			\
		IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16				\
		IOMUX_PAD(0x03F4, 0x00E0, 2, 0x08C8, 1, 0)
#define _MX6Q_PAD_EIM_A21__RESERVED_RESERVED			\
		IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18		\
		IOMUX_PAD(0x03F4, 0x00E0, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A21__GPIO_2_17			\
		IOMUX_PAD(0x03F4, 0x00E0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A21__TPSMP_HDATA_1				\
		IOMUX_PAD(0x03F4, 0x00E0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A21__SRC_BT_CFG_21				\
		IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20				\
		IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15			\
		IOMUX_PAD(0x03F8, 0x00E4, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15				\
		IOMUX_PAD(0x03F8, 0x00E4, 2, 0x08C4, 1, 0)
#define _MX6Q_PAD_EIM_A20__RESERVED_RESERVED			\
		IOMUX_PAD(0x03F8, 0x00E4, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19		\
		IOMUX_PAD(0x03F8, 0x00E4, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A20__GPIO_2_18			\
		IOMUX_PAD(0x03F8, 0x00E4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A20__TPSMP_HDATA_2				\
		IOMUX_PAD(0x03F8, 0x00E4, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A20__SRC_BT_CFG_20				\
		IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19				\
		IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14			\
		IOMUX_PAD(0x03FC, 0x00E8, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14				\
		IOMUX_PAD(0x03FC, 0x00E8, 2, 0x08C0, 1, 0)
#define _MX6Q_PAD_EIM_A19__RESERVED_RESERVED			\
		IOMUX_PAD(0x03FC, 0x00E8, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20		\
		IOMUX_PAD(0x03FC, 0x00E8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A19__GPIO_2_19			\
		IOMUX_PAD(0x03FC, 0x00E8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A19__TPSMP_HDATA_3				\
		IOMUX_PAD(0x03FC, 0x00E8, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A19__SRC_BT_CFG_19				\
		IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18				\
		IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13			\
		IOMUX_PAD(0x0400, 0x00EC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13				\
		IOMUX_PAD(0x0400, 0x00EC, 2, 0x08BC, 1, 0)
#define _MX6Q_PAD_EIM_A18__RESERVED_RESERVED			\
		IOMUX_PAD(0x0400, 0x00EC, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21		\
		IOMUX_PAD(0x0400, 0x00EC, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A18__GPIO_2_20			\
		IOMUX_PAD(0x0400, 0x00EC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A18__TPSMP_HDATA_4				\
		IOMUX_PAD(0x0400, 0x00EC, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A18__SRC_BT_CFG_18				\
		IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17				\
		IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12			\
		IOMUX_PAD(0x0404, 0x00F0, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12				\
		IOMUX_PAD(0x0404, 0x00F0, 2, 0x08B8, 1, 0)
#define _MX6Q_PAD_EIM_A17__RESERVED_RESERVED			\
		IOMUX_PAD(0x0404, 0x00F0, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22		\
		IOMUX_PAD(0x0404, 0x00F0, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A17__GPIO_2_21			\
		IOMUX_PAD(0x0404, 0x00F0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A17__TPSMP_HDATA_5				\
		IOMUX_PAD(0x0404, 0x00F0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A17__SRC_BT_CFG_17				\
		IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16				\
		IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK			\
		IOMUX_PAD(0x0408, 0x00F4, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK			\
		IOMUX_PAD(0x0408, 0x00F4, 2, 0x08E0, 1, 0)
#define _MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23		\
		IOMUX_PAD(0x0408, 0x00F4, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A16__GPIO_2_22			\
		IOMUX_PAD(0x0408, 0x00F4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A16__TPSMP_HDATA_6				\
		IOMUX_PAD(0x0408, 0x00F4, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_A16__SRC_BT_CFG_16				\
		IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0				\
		IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5				\
		IOMUX_PAD(0x040C, 0x00F8, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_CS0__ECSPI2_SCLK			\
		IOMUX_PAD(0x040C, 0x00F8, 2, 0x0810, 0, 0)
#define _MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24		\
		IOMUX_PAD(0x040C, 0x00F8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_CS0__GPIO_2_23			\
		IOMUX_PAD(0x040C, 0x00F8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7				\
		IOMUX_PAD(0x040C, 0x00F8, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1				\
		IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6				\
		IOMUX_PAD(0x0410, 0x00FC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_CS1__ECSPI2_MOSI			\
		IOMUX_PAD(0x0410, 0x00FC, 2, 0x0818, 0, 0)
#define _MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25		\
		IOMUX_PAD(0x0410, 0x00FC, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_CS1__GPIO_2_24			\
		IOMUX_PAD(0x0410, 0x00FC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8				\
		IOMUX_PAD(0x0410, 0x00FC, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_OE__WEIM_WEIM_OE			\
		IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7			\
		IOMUX_PAD(0x0414, 0x0100, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_OE__ECSPI2_MISO			\
		IOMUX_PAD(0x0414, 0x0100, 2, 0x0814, 0, 0)
#define _MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26		\
		IOMUX_PAD(0x0414, 0x0100, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_OE__GPIO_2_25			\
		IOMUX_PAD(0x0414, 0x0100, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_OE__TPSMP_HDATA_9			\
		IOMUX_PAD(0x0414, 0x0100, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_RW__WEIM_WEIM_RW			\
		IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8			\
		IOMUX_PAD(0x0418, 0x0104, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_RW__ECSPI2_SS0			\
		IOMUX_PAD(0x0418, 0x0104, 2, 0x081C, 0, 0)
#define _MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27		\
		IOMUX_PAD(0x0418, 0x0104, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_RW__GPIO_2_26			\
		IOMUX_PAD(0x0418, 0x0104, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_RW__TPSMP_HDATA_10				\
		IOMUX_PAD(0x0418, 0x0104, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_RW__SRC_BT_CFG_29			\
		IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA				\
		IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17				\
		IOMUX_PAD(0x041C, 0x0108, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_LBA__ECSPI2_SS1			\
		IOMUX_PAD(0x041C, 0x0108, 2, 0x0820, 0, 0)
#define _MX6Q_PAD_EIM_LBA__GPIO_2_27			\
		IOMUX_PAD(0x041C, 0x0108, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11				\
		IOMUX_PAD(0x041C, 0x0108, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26				\
		IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0				\
		IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11			\
		IOMUX_PAD(0x0420, 0x010C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11				\
		IOMUX_PAD(0x0420, 0x010C, 2, 0x08B4, 1, 0)
#define _MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0		\
		IOMUX_PAD(0x0420, 0x010C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY			\
		IOMUX_PAD(0x0420, 0x010C, 4, 0x07F0, 0, 0)
#define _MX6Q_PAD_EIM_EB0__GPIO_2_28			\
		IOMUX_PAD(0x0420, 0x010C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12				\
		IOMUX_PAD(0x0420, 0x010C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27				\
		IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1				\
		IOMUX_PAD(0x0424, 0x0110, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10			\
		IOMUX_PAD(0x0424, 0x0110, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10				\
		IOMUX_PAD(0x0424, 0x0110, 2, 0x08B0, 1, 0)
#define _MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1		\
		IOMUX_PAD(0x0424, 0x0110, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB1__GPIO_2_29			\
		IOMUX_PAD(0x0424, 0x0110, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13				\
		IOMUX_PAD(0x0424, 0x0110, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28				\
		IOMUX_PAD(0x0424, 0x0110, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0			\
		IOMUX_PAD(0x0428, 0x0114, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9			\
		IOMUX_PAD(0x0428, 0x0114, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9				\
		IOMUX_PAD(0x0428, 0x0114, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2		\
		IOMUX_PAD(0x0428, 0x0114, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA0__GPIO_3_0			\
		IOMUX_PAD(0x0428, 0x0114, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14				\
		IOMUX_PAD(0x0428, 0x0114, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0			\
		IOMUX_PAD(0x0428, 0x0114, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1			\
		IOMUX_PAD(0x042C, 0x0118, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8			\
		IOMUX_PAD(0x042C, 0x0118, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8				\
		IOMUX_PAD(0x042C, 0x0118, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3		\
		IOMUX_PAD(0x042C, 0x0118, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE		\
		IOMUX_PAD(0x042C, 0x0118, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA1__GPIO_3_1			\
		IOMUX_PAD(0x042C, 0x0118, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15				\
		IOMUX_PAD(0x042C, 0x0118, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1			\
		IOMUX_PAD(0x042C, 0x0118, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2			\
		IOMUX_PAD(0x0430, 0x011C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7			\
		IOMUX_PAD(0x0430, 0x011C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7				\
		IOMUX_PAD(0x0430, 0x011C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4		\
		IOMUX_PAD(0x0430, 0x011C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE		\
		IOMUX_PAD(0x0430, 0x011C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA2__GPIO_3_2			\
		IOMUX_PAD(0x0430, 0x011C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16				\
		IOMUX_PAD(0x0430, 0x011C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2			\
		IOMUX_PAD(0x0430, 0x011C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3			\
		IOMUX_PAD(0x0434, 0x0120, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6			\
		IOMUX_PAD(0x0434, 0x0120, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6				\
		IOMUX_PAD(0x0434, 0x0120, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5		\
		IOMUX_PAD(0x0434, 0x0120, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ		\
		IOMUX_PAD(0x0434, 0x0120, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA3__GPIO_3_3			\
		IOMUX_PAD(0x0434, 0x0120, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17				\
		IOMUX_PAD(0x0434, 0x0120, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3			\
		IOMUX_PAD(0x0434, 0x0120, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4			\
		IOMUX_PAD(0x0438, 0x0124, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5			\
		IOMUX_PAD(0x0438, 0x0124, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5				\
		IOMUX_PAD(0x0438, 0x0124, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6		\
		IOMUX_PAD(0x0438, 0x0124, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN		\
		IOMUX_PAD(0x0438, 0x0124, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA4__GPIO_3_4			\
		IOMUX_PAD(0x0438, 0x0124, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18				\
		IOMUX_PAD(0x0438, 0x0124, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4			\
		IOMUX_PAD(0x0438, 0x0124, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5			\
		IOMUX_PAD(0x043C, 0x0128, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4			\
		IOMUX_PAD(0x043C, 0x0128, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4				\
		IOMUX_PAD(0x043C, 0x0128, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7		\
		IOMUX_PAD(0x043C, 0x0128, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP		\
		IOMUX_PAD(0x043C, 0x0128, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA5__GPIO_3_5			\
		IOMUX_PAD(0x043C, 0x0128, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19				\
		IOMUX_PAD(0x043C, 0x0128, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5			\
		IOMUX_PAD(0x043C, 0x0128, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6			\
		IOMUX_PAD(0x0440, 0x012C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3			\
		IOMUX_PAD(0x0440, 0x012C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3				\
		IOMUX_PAD(0x0440, 0x012C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8		\
		IOMUX_PAD(0x0440, 0x012C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN		\
		IOMUX_PAD(0x0440, 0x012C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA6__GPIO_3_6			\
		IOMUX_PAD(0x0440, 0x012C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20				\
		IOMUX_PAD(0x0440, 0x012C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6			\
		IOMUX_PAD(0x0440, 0x012C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7			\
		IOMUX_PAD(0x0444, 0x0130, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2			\
		IOMUX_PAD(0x0444, 0x0130, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2				\
		IOMUX_PAD(0x0444, 0x0130, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9		\
		IOMUX_PAD(0x0444, 0x0130, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA7__GPIO_3_7			\
		IOMUX_PAD(0x0444, 0x0130, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21				\
		IOMUX_PAD(0x0444, 0x0130, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7			\
		IOMUX_PAD(0x0444, 0x0130, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8			\
		IOMUX_PAD(0x0448, 0x0134, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1			\
		IOMUX_PAD(0x0448, 0x0134, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1				\
		IOMUX_PAD(0x0448, 0x0134, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10		\
		IOMUX_PAD(0x0448, 0x0134, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA8__GPIO_3_8			\
		IOMUX_PAD(0x0448, 0x0134, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22				\
		IOMUX_PAD(0x0448, 0x0134, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8			\
		IOMUX_PAD(0x0448, 0x0134, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9			\
		IOMUX_PAD(0x044C, 0x0138, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0			\
		IOMUX_PAD(0x044C, 0x0138, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0				\
		IOMUX_PAD(0x044C, 0x0138, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11		\
		IOMUX_PAD(0x044C, 0x0138, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA9__GPIO_3_9			\
		IOMUX_PAD(0x044C, 0x0138, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23				\
		IOMUX_PAD(0x044C, 0x0138, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9			\
		IOMUX_PAD(0x044C, 0x0138, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10		\
		IOMUX_PAD(0x0450, 0x013C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15		\
		IOMUX_PAD(0x0450, 0x013C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN		\
		IOMUX_PAD(0x0450, 0x013C, 2, 0x08D8, 1, 0)
#define _MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12		\
		IOMUX_PAD(0x0450, 0x013C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA10__GPIO_3_10			\
		IOMUX_PAD(0x0450, 0x013C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24		\
		IOMUX_PAD(0x0450, 0x013C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10				\
		IOMUX_PAD(0x0450, 0x013C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11		\
		IOMUX_PAD(0x0454, 0x0140, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2				\
		IOMUX_PAD(0x0454, 0x0140, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC			\
		IOMUX_PAD(0x0454, 0x0140, 2, 0x08DC, 1, 0)
#define _MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13		\
		IOMUX_PAD(0x0454, 0x0140, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6		\
		IOMUX_PAD(0x0454, 0x0140, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA11__GPIO_3_11			\
		IOMUX_PAD(0x0454, 0x0140, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25		\
		IOMUX_PAD(0x0454, 0x0140, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11				\
		IOMUX_PAD(0x0454, 0x0140, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12		\
		IOMUX_PAD(0x0458, 0x0144, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3				\
		IOMUX_PAD(0x0458, 0x0144, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC			\
		IOMUX_PAD(0x0458, 0x0144, 2, 0x08E4, 1, 0)
#define _MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14		\
		IOMUX_PAD(0x0458, 0x0144, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3		\
		IOMUX_PAD(0x0458, 0x0144, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA12__GPIO_3_12			\
		IOMUX_PAD(0x0458, 0x0144, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26		\
		IOMUX_PAD(0x0458, 0x0144, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12				\
		IOMUX_PAD(0x0458, 0x0144, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13		\
		IOMUX_PAD(0x045C, 0x0148, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS		\
		IOMUX_PAD(0x045C, 0x0148, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK			\
		IOMUX_PAD(0x045C, 0x0148, 2, 0x07EC, 1, 0)
#define _MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15		\
		IOMUX_PAD(0x045C, 0x0148, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4		\
		IOMUX_PAD(0x045C, 0x0148, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA13__GPIO_3_13				\
		IOMUX_PAD(0x045C, 0x0148, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27			\
		IOMUX_PAD(0x045C, 0x0148, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13			\
		IOMUX_PAD(0x045C, 0x0148, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14			\
		IOMUX_PAD(0x0460, 0x014C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS			\
		IOMUX_PAD(0x0460, 0x014C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK			\
		IOMUX_PAD(0x0460, 0x014C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16		\
		IOMUX_PAD(0x0460, 0x014C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5		\
		IOMUX_PAD(0x0460, 0x014C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA14__GPIO_3_14				\
		IOMUX_PAD(0x0460, 0x014C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28			\
		IOMUX_PAD(0x0460, 0x014C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14			\
		IOMUX_PAD(0x0460, 0x014C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15			\
		IOMUX_PAD(0x0464, 0x0150, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1			\
		IOMUX_PAD(0x0464, 0x0150, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4			\
		IOMUX_PAD(0x0464, 0x0150, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17		\
		IOMUX_PAD(0x0464, 0x0150, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA15__GPIO_3_15				\
		IOMUX_PAD(0x0464, 0x0150, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29			\
		IOMUX_PAD(0x0464, 0x0150, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15			\
		IOMUX_PAD(0x0464, 0x0150, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT			\
		IOMUX_PAD(0x0468, 0x0154, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B			\
		IOMUX_PAD(0x0468, 0x0154, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_WAIT__GPIO_5_0				\
		IOMUX_PAD(0x0468, 0x0154, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30			\
		IOMUX_PAD(0x0468, 0x0154, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25			\
		IOMUX_PAD(0x0468, 0x0154, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK			\
		IOMUX_PAD(0x046C, 0x0158, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16			\
		IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_BCLK__GPIO_6_31				\
		IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31			\
		IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK		\
		IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK		\
		IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28	\
		IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0		\
		IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16			\
		IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0		\
		IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15			\
		IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15			\
		IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC			\
		IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29		\
		IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1		\
		IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN15__GPIO_4_17				\
		IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1			\
		IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2			\
		IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2			\
		IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD			\
		IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30		\
		IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2		\
		IOMUX_PAD(0x0478, 0x0164, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN2__GPIO_4_18				\
		IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2			\
		IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9		\
		IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3			\
		IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3			\
		IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS			\
		IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31		\
		IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3		\
		IOMUX_PAD(0x047C, 0x0168, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN3__GPIO_4_19			\
		IOMUX_PAD(0x047C, 0x0168, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3			\
		IOMUX_PAD(0x047C, 0x0168, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10		\
		IOMUX_PAD(0x047C, 0x0168, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4			\
		IOMUX_PAD(0x0480, 0x016C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4			\
		IOMUX_PAD(0x0480, 0x016C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD			\
		IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN4__USDHC1_WP				\
		IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0)
#define _MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD			\
		IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN4__GPIO_4_20				\
		IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4			\
		IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11		\
		IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0			\
		IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0			\
		IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK			\
		IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0		\
		IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN		\
		IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT0__GPIO_4_21				\
		IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5			\
		IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1			\
		IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1			\
		IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI			\
		IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1		\
		IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL	\
		IOMUX_PAD(0x0488, 0x0174, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT1__GPIO_4_22				\
		IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6			\
		IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12		\
		IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2			\
		IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2			\
		IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO			\
		IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2		\
		IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE			\
		IOMUX_PAD(0x048C, 0x0178, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT2__GPIO_4_23				\
		IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7			\
		IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13		\
		IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3			\
		IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3			\
		IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0			\
		IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3		\
		IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR		\
		IOMUX_PAD(0x0490, 0x017C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT3__GPIO_4_24				\
		IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8			\
		IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14		\
		IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4			\
		IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4			\
		IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1			\
		IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4		\
		IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB		\
		IOMUX_PAD(0x0494, 0x0180, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT4__GPIO_4_25				\
		IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9			\
		IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15		\
		IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5			\
		IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5			\
		IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2			\
		IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS			\
		IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS		\
		IOMUX_PAD(0x0498, 0x0184, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT5__GPIO_4_26				\
		IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10		\
		IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16		\
		IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6			\
		IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6			\
		IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3			\
		IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC			\
		IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE		\
		IOMUX_PAD(0x049C, 0x0188, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT6__GPIO_4_27				\
		IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11		\
		IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17		\
		IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7			\
		IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7			\
		IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY			\
		IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5		\
		IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0	\
		IOMUX_PAD(0x04A0, 0x018C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT7__GPIO_4_28				\
		IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12		\
		IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18		\
		IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8			\
		IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8			\
		IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT8__PWM1_PWMO				\
		IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B			\
		IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1	\
		IOMUX_PAD(0x04A4, 0x0190, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT8__GPIO_4_29				\
		IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13		\
		IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19		\
		IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9		\
		IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9		\
		IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT9__PWM2_PWMO			\
		IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B		\
		IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2		\
		IOMUX_PAD(0x04A8, 0x0194, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT9__GPIO_4_30			\
		IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14		\
		IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20		\
		IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10		\
		IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10		\
		IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6		\
		IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3		\
		IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT10__GPIO_4_31				\
		IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15		\
		IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21		\
		IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11		\
		IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11		\
		IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7		\
		IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4		\
		IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT11__GPIO_5_5			\
		IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16		\
		IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22		\
		IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12		\
		IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12		\
		IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED		\
		IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5		\
		IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT12__GPIO_5_6			\
		IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17		\
		IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23		\
		IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13		\
		IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13		\
		IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS		\
		IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0)
#define _MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0		\
		IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT13__GPIO_5_7			\
		IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18		\
		IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24		\
		IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14		\
		IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14		\
		IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC		\
		IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0)
#define _MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1		\
		IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT14__GPIO_5_8			\
		IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19		\
		IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15		\
		IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15		\
		IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1				\
		IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0)
#define _MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1				\
		IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0)
#define _MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2		\
		IOMUX_PAD(0x04C0, 0x01AC, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT15__GPIO_5_9			\
		IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20		\
		IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25		\
		IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16		\
		IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16		\
		IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI		\
		IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0)
#define _MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC		\
		IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0)
#define _MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0		\
		IOMUX_PAD(0x04C4, 0x01B0, 4, 0x090C, 0, 0)
#define _MX6Q_PAD_DISP0_DAT16__GPIO_5_10				\
		IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21		\
		IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26		\
		IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17		\
		IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17		\
		IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO		\
		IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0)
#define _MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD		\
		IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0)
#define _MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1		\
		IOMUX_PAD(0x04C8, 0x01B4, 4, 0x0910, 0, 0)
#define _MX6Q_PAD_DISP0_DAT17__GPIO_5_11				\
		IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22		\
		IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27		\
		IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18		\
		IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18		\
		IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0				\
		IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0)
#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS		\
		IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0)
#define _MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS		\
		IOMUX_PAD(0x04CC, 0x01B8, 4, 0x07C0, 0, 0)
#define _MX6Q_PAD_DISP0_DAT18__GPIO_5_12				\
		IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23		\
		IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2		\
		IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19		\
		IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19		\
		IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK		\
		IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0)
#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD		\
		IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0)
#define _MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC		\
		IOMUX_PAD(0x04D0, 0x01BC, 4, 0x07BC, 0, 0)
#define _MX6Q_PAD_DISP0_DAT19__GPIO_5_13				\
		IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24		\
		IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3		\
		IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20		\
		IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20		\
		IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK		\
		IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0)
#define _MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC		\
		IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0)
#define _MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7		\
		IOMUX_PAD(0x04D4, 0x01C0, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT20__GPIO_5_14				\
		IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25		\
		IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28		\
		IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21		\
		IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21		\
		IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI		\
		IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0)
#define _MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD		\
		IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0)
#define _MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0		\
		IOMUX_PAD(0x04D8, 0x01C4, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT21__GPIO_5_15				\
		IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26		\
		IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29		\
		IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22		\
		IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22		\
		IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO		\
		IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0)
#define _MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS		\
		IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0)
#define _MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1		\
		IOMUX_PAD(0x04DC, 0x01C8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT22__GPIO_5_16				\
		IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27		\
		IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30		\
		IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23		\
		IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23		\
		IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0				\
		IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0)
#define _MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD		\
		IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0)
#define _MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2		\
		IOMUX_PAD(0x04E0, 0x01CC, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT23__GPIO_5_17				\
		IOMUX_PAD(0x04E0, 0x01CC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28		\
		IOMUX_PAD(0x04E0, 0x01CC, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31		\
		IOMUX_PAD(0x04E0, 0x01CC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED		\
		IOMUX_PAD(0x04E4, 0x01D0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_MDIO__ENET_MDIO			\
		IOMUX_PAD(0x04E4, 0x01D0, 1, 0x0840, 0, 0)
#define _MX6Q_PAD_ENET_MDIO__ESAI1_SCKR			\
		IOMUX_PAD(0x04E4, 0x01D0, 2, 0x086C, 0, 0)
#define _MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3		\
		IOMUX_PAD(0x04E4, 0x01D0, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT		\
		IOMUX_PAD(0x04E4, 0x01D0, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_MDIO__GPIO_1_22			\
		IOMUX_PAD(0x04E4, 0x01D0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK				\
		IOMUX_PAD(0x04E4, 0x01D0, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED		\
		IOMUX_PAD(0x04E8, 0x01D4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK			\
		IOMUX_PAD(0x04E8, 0x01D4, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR				\
		IOMUX_PAD(0x04E8, 0x01D4, 2, 0x085C, 0, 0)
#define _MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4		\
		IOMUX_PAD(0x04E8, 0x01D4, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_REF_CLK__GPIO_1_23				\
		IOMUX_PAD(0x04E8, 0x01D4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK			\
		IOMUX_PAD(0x04E8, 0x01D4, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH		\
		IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_ENET_RX_ER__ENET_RX_ER				\
		IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR				\
		IOMUX_PAD(0x04EC, 0x01D8, 2, 0x0864, 0, 0)
#define _MX6Q_PAD_ENET_RX_ER__SPDIF_IN1			\
		IOMUX_PAD(0x04EC, 0x01D8, 3, 0x0914, 1, 0)
#define _MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT		\
		IOMUX_PAD(0x04EC, 0x01D8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_RX_ER__GPIO_1_24			\
		IOMUX_PAD(0x04EC, 0x01D8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_RX_ER__PHY_TDI			\
		IOMUX_PAD(0x04EC, 0x01D8, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD		\
		IOMUX_PAD(0x04EC, 0x01D8, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED		\
		IOMUX_PAD(0x04F0, 0x01DC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN				\
		IOMUX_PAD(0x04F0, 0x01DC, 1, 0x0858, 1, 0)
#define _MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT				\
		IOMUX_PAD(0x04F0, 0x01DC, 2, 0x0870, 0, 0)
#define _MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK		\
		IOMUX_PAD(0x04F0, 0x01DC, 3, 0x0918, 1, 0)
#define _MX6Q_PAD_ENET_CRS_DV__GPIO_1_25				\
		IOMUX_PAD(0x04F0, 0x01DC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_CRS_DV__PHY_TDO			\
		IOMUX_PAD(0x04F0, 0x01DC, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD		\
		IOMUX_PAD(0x04F0, 0x01DC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_ENET_RXD1__MLB_MLBSIG			\
		IOMUX_PAD(0x04F4, 0x01E0, 0, 0x0908, 0, 0)
#define _MX6Q_PAD_ENET_RXD1__ENET_RDATA_1				\
		IOMUX_PAD(0x04F4, 0x01E0, 1, 0x084C, 1, 0)
#define _MX6Q_PAD_ENET_RXD1__ESAI1_FST			\
		IOMUX_PAD(0x04F4, 0x01E0, 2, 0x0860, 0, 0)
#define _MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT		\
		IOMUX_PAD(0x04F4, 0x01E0, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_RXD1__GPIO_1_26			\
		IOMUX_PAD(0x04F4, 0x01E0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_RXD1__PHY_TCK			\
		IOMUX_PAD(0x04F4, 0x01E0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET		\
		IOMUX_PAD(0x04F4, 0x01E0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT			\
		IOMUX_PAD(0x04F8, 0x01E4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_RXD0__ENET_RDATA_0				\
		IOMUX_PAD(0x04F8, 0x01E4, 1, 0x0848, 1, 0)
#define _MX6Q_PAD_ENET_RXD0__ESAI1_HCKT			\
		IOMUX_PAD(0x04F8, 0x01E4, 2, 0x0868, 0, 0)
#define _MX6Q_PAD_ENET_RXD0__SPDIF_OUT1			\
		IOMUX_PAD(0x04F8, 0x01E4, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_RXD0__GPIO_1_27			\
		IOMUX_PAD(0x04F8, 0x01E4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_RXD0__PHY_TMS			\
		IOMUX_PAD(0x04F8, 0x01E4, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV		\
		IOMUX_PAD(0x04F8, 0x01E4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED		\
		IOMUX_PAD(0x04FC, 0x01E8, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_TX_EN__ENET_TX_EN				\
		IOMUX_PAD(0x04FC, 0x01E8, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2			\
		IOMUX_PAD(0x04FC, 0x01E8, 2, 0x0880, 0, 0)
#define _MX6Q_PAD_ENET_TX_EN__GPIO_1_28			\
		IOMUX_PAD(0x04FC, 0x01E8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI		\
		IOMUX_PAD(0x04FC, 0x01E8, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH		\
		IOMUX_PAD(0x04FC, 0x01E8, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_ENET_TXD1__MLB_MLBCLK			\
		IOMUX_PAD(0x0500, 0x01EC, 0, 0x0900, 0, 0)
#define _MX6Q_PAD_ENET_TXD1__ENET_TDATA_1				\
		IOMUX_PAD(0x0500, 0x01EC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3		\
		IOMUX_PAD(0x0500, 0x01EC, 2, 0x087C, 0, 0)
#define _MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN		\
		IOMUX_PAD(0x0500, 0x01EC, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_TXD1__GPIO_1_29			\
		IOMUX_PAD(0x0500, 0x01EC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO				\
		IOMUX_PAD(0x0500, 0x01EC, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD		\
		IOMUX_PAD(0x0500, 0x01EC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED		\
		IOMUX_PAD(0x0504, 0x01F0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_TXD0__ENET_TDATA_0				\
		IOMUX_PAD(0x0504, 0x01F0, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1		\
		IOMUX_PAD(0x0504, 0x01F0, 2, 0x0884, 0, 0)
#define _MX6Q_PAD_ENET_TXD0__GPIO_1_30			\
		IOMUX_PAD(0x0504, 0x01F0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK				\
		IOMUX_PAD(0x0504, 0x01F0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD		\
		IOMUX_PAD(0x0504, 0x01F0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_ENET_MDC__MLB_MLBDAT			\
		IOMUX_PAD(0x0508, 0x01F4, 0, 0x0904, 0, 0)
#define _MX6Q_PAD_ENET_MDC__ENET_MDC			\
		IOMUX_PAD(0x0508, 0x01F4, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0				\
		IOMUX_PAD(0x0508, 0x01F4, 2, 0x0888, 0, 0)
#define _MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN		\
		IOMUX_PAD(0x0508, 0x01F4, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_MDC__GPIO_1_31			\
		IOMUX_PAD(0x0508, 0x01F4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_MDC__SATA_PHY_TMS				\
		IOMUX_PAD(0x0508, 0x01F4, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET		\
		IOMUX_PAD(0x0508, 0x01F4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5		\
		IOMUX_PAD(0x050C, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5			\
		IOMUX_PAD(0x0510, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4			\
		IOMUX_PAD(0x0514, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4		\
		IOMUX_PAD(0x0518, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3		\
		IOMUX_PAD(0x051C, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3			\
		IOMUX_PAD(0x0520, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2		\
		IOMUX_PAD(0x0524, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2			\
		IOMUX_PAD(0x0528, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0				\
		IOMUX_PAD(0x052C, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1				\
		IOMUX_PAD(0x0530, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2				\
		IOMUX_PAD(0x0534, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3				\
		IOMUX_PAD(0x0538, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4				\
		IOMUX_PAD(0x053C, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5				\
		IOMUX_PAD(0x0540, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6				\
		IOMUX_PAD(0x0544, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7				\
		IOMUX_PAD(0x0548, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8				\
		IOMUX_PAD(0x054C, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9				\
		IOMUX_PAD(0x0550, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10		\
		IOMUX_PAD(0x0554, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11		\
		IOMUX_PAD(0x0558, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12		\
		IOMUX_PAD(0x055C, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13		\
		IOMUX_PAD(0x0560, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14		\
		IOMUX_PAD(0x0564, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15		\
		IOMUX_PAD(0x0568, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS				\
		IOMUX_PAD(0x056C, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0		\
		IOMUX_PAD(0x0570, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1		\
		IOMUX_PAD(0x0574, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS				\
		IOMUX_PAD(0x0578, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET		\
		IOMUX_PAD(0x057C, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0		\
		IOMUX_PAD(0x0580, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1		\
		IOMUX_PAD(0x0584, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0		\
		IOMUX_PAD(0x0588, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2		\
		IOMUX_PAD(0x058C, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0		\
		IOMUX_PAD(0x0590, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1		\
		IOMUX_PAD(0x0594, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1		\
		IOMUX_PAD(0x0598, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0		\
		IOMUX_PAD(0x059C, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1		\
		IOMUX_PAD(0x05A0, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE			\
		IOMUX_PAD(0x05A4, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0				\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1				\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2				\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3				\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4				\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5				\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0		\
		IOMUX_PAD(0x05A8, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6				\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7				\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0			\
		IOMUX_PAD(0x05AC, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8				\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9				\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1		\
		IOMUX_PAD(0x05B0, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1			\
		IOMUX_PAD(0x05B4, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6		\
		IOMUX_PAD(0x05B8, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6			\
		IOMUX_PAD(0x05BC, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7		\
		IOMUX_PAD(0x05C0, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7			\
		IOMUX_PAD(0x05C4, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_KEY_COL0__ECSPI1_SCLK			\
		IOMUX_PAD(0x05C8, 0x01F8, 0, 0x07F4, 2, 0)
#define _MX6Q_PAD_KEY_COL0__ENET_RDATA_3				\
		IOMUX_PAD(0x05C8, 0x01F8, 1, 0x0854, 1, 0)
#define _MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC			\
		IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0)
#define _MX6Q_PAD_KEY_COL0__KPP_COL_0			\
		IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL0__UART4_TXD			\
		IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL0__UART4_RXD			\
		IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0)
#define _MX6Q_PAD_KEY_COL0__GPIO_4_6			\
		IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT		\
		IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST		\
		IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI			\
		IOMUX_PAD(0x05CC, 0x01FC, 0, 0x07FC, 2, 0)
#define _MX6Q_PAD_KEY_ROW0__ENET_TDATA_3				\
		IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD			\
		IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0)
#define _MX6Q_PAD_KEY_ROW0__KPP_ROW_0			\
		IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW0__UART4_TXD			\
		IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW0__UART4_RXD			\
		IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0)
#define _MX6Q_PAD_KEY_ROW0__GPIO_4_7			\
		IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT		\
		IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0		\
		IOMUX_PAD(0x05CC, 0x01FC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_KEY_COL1__ECSPI1_MISO			\
		IOMUX_PAD(0x05D0, 0x0200, 0, 0x07F8, 2, 0)
#define _MX6Q_PAD_KEY_COL1__ENET_MDIO			\
		IOMUX_PAD(0x05D0, 0x0200, 1, 0x0840, 1, 0)
#define _MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS			\
		IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0)
#define _MX6Q_PAD_KEY_COL1__KPP_COL_1			\
		IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL1__UART5_TXD			\
		IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL1__UART5_RXD			\
		IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0)
#define _MX6Q_PAD_KEY_COL1__GPIO_4_8			\
		IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL1__USDHC1_VSELECT		\
		IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1		\
		IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_KEY_ROW1__ECSPI1_SS0			\
		IOMUX_PAD(0x05D4, 0x0204, 0, 0x0800, 2, 0)
#define _MX6Q_PAD_KEY_ROW1__ENET_COL			\
		IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD			\
		IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0)
#define _MX6Q_PAD_KEY_ROW1__KPP_ROW_1			\
		IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW1__UART5_TXD			\
		IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW1__UART5_RXD			\
		IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0)
#define _MX6Q_PAD_KEY_ROW1__GPIO_4_9			\
		IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT		\
		IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2		\
		IOMUX_PAD(0x05D4, 0x0204, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_KEY_COL2__ECSPI1_SS1			\
		IOMUX_PAD(0x05D8, 0x0208, 0, 0x0804, 2, 0)
#define _MX6Q_PAD_KEY_COL2__ENET_RDATA_2				\
		IOMUX_PAD(0x05D8, 0x0208, 1, 0x0850, 1, 0)
#define _MX6Q_PAD_KEY_COL2__CAN1_TXCAN			\
		IOMUX_PAD(0x05D8, 0x0208, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL2__KPP_COL_2			\
		IOMUX_PAD(0x05D8, 0x0208, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL2__ENET_MDC			\
		IOMUX_PAD(0x05D8, 0x0208, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL2__GPIO_4_10			\
		IOMUX_PAD(0x05D8, 0x0208, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP		\
		IOMUX_PAD(0x05D8, 0x0208, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3		\
		IOMUX_PAD(0x05D8, 0x0208, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_KEY_ROW2__ECSPI1_SS2			\
		IOMUX_PAD(0x05DC, 0x020C, 0, 0x0808, 1, 0)
#define _MX6Q_PAD_KEY_ROW2__ENET_TDATA_2				\
		IOMUX_PAD(0x05DC, 0x020C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW2__CAN1_RXCAN			\
		IOMUX_PAD(0x05DC, 0x020C, 2, 0x07E4, 0, 0)
#define _MX6Q_PAD_KEY_ROW2__KPP_ROW_2			\
		IOMUX_PAD(0x05DC, 0x020C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT		\
		IOMUX_PAD(0x05DC, 0x020C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW2__GPIO_4_11			\
		IOMUX_PAD(0x05DC, 0x020C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE			\
		IOMUX_PAD(0x05DC, 0x020C, 6, 0x088C, 1, 0)
#define _MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4		\
		IOMUX_PAD(0x05DC, 0x020C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_KEY_COL3__ECSPI1_SS3			\
		IOMUX_PAD(0x05E0, 0x0210, 0, 0x080C, 1, 0)
#define _MX6Q_PAD_KEY_COL3__ENET_CRS			\
		IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL			\
		IOMUX_PAD(0x05E0, 0x0210, 2, 0x0890, 1, 0)
#define _MX6Q_PAD_KEY_COL3__KPP_COL_3			\
		IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL3__I2C2_SCL			\
		IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0)
#define _MX6Q_PAD_KEY_COL3__GPIO_4_12			\
		IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL3__SPDIF_IN1			\
		IOMUX_PAD(0x05E0, 0x0210, 6, 0x0914, 2, 0)
#define _MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5		\
		IOMUX_PAD(0x05E0, 0x0210, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT		\
		IOMUX_PAD(0x05E4, 0x0214, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK		\
		IOMUX_PAD(0x05E4, 0x0214, 1, 0x07B0, 0, 0)
#define _MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA			\
		IOMUX_PAD(0x05E4, 0x0214, 2, 0x0894, 1, 0)
#define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3			\
		IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW3__I2C2_SDA			\
		IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0)
#define _MX6Q_PAD_KEY_ROW3__GPIO_4_13			\
		IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT		\
		IOMUX_PAD(0x05E4, 0x0214, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6		\
		IOMUX_PAD(0x05E4, 0x0214, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_KEY_COL4__CAN2_TXCAN			\
		IOMUX_PAD(0x05E8, 0x0218, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL4__IPU1_SISG_4			\
		IOMUX_PAD(0x05E8, 0x0218, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC			\
		IOMUX_PAD(0x05E8, 0x0218, 2, 0x0944, 1, 0)
#define _MX6Q_PAD_KEY_COL4__KPP_COL_4			\
		IOMUX_PAD(0x05E8, 0x0218, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL4__UART5_CTS			\
		IOMUX_PAD(0x05E8, 0x0218, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL4__UART5_RTS			\
		IOMUX_PAD(0x05E8, 0x0218, 4, 0x093C, 0, 0)
#define _MX6Q_PAD_KEY_COL4__GPIO_4_14			\
		IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49		\
		IOMUX_PAD(0x05E8, 0x0218, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7		\
		IOMUX_PAD(0x05E8, 0x0218, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_KEY_ROW4__CAN2_RXCAN			\
		IOMUX_PAD(0x05EC, 0x021C, 0, 0x07E8, 0, 0)
#define _MX6Q_PAD_KEY_ROW4__IPU1_SISG_5			\
		IOMUX_PAD(0x05EC, 0x021C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR		\
		IOMUX_PAD(0x05EC, 0x021C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW4__KPP_ROW_4			\
		IOMUX_PAD(0x05EC, 0x021C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW4__UART5_CTS			\
		IOMUX_PAD(0x05EC, 0x021C, 4, 0x093C, 1, 0)
#define _MX6Q_PAD_KEY_ROW4__GPIO_4_15			\
		IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50		\
		IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8		\
		IOMUX_PAD(0x05EC, 0x021C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_GPIO_0__CCM_CLKO			\
		IOMUX_PAD(0x05F0, 0x0220, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_0__KPP_COL_5			\
		IOMUX_PAD(0x05F0, 0x0220, 2, 0x08E8, 0, 0)
#define _MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK			\
		IOMUX_PAD(0x05F0, 0x0220, 3, 0x07B0, 1, 0)
#define _MX6Q_PAD_GPIO_0__EPIT1_EPITO			\
		IOMUX_PAD(0x05F0, 0x0220, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_0__GPIO_1_0			\
		IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR		\
		IOMUX_PAD(0x05F0, 0x0220, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5		\
		IOMUX_PAD(0x05F0, 0x0220, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_GPIO_1__ESAI1_SCKR			\
		IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0)
#define _MX6Q_PAD_GPIO_1__WDOG2_WDOG_B			\
		IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_1__KPP_ROW_5			\
		IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0)
#define MX6Q_PAD_GPIO_1__USBOTG_ID                      \
		IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, MX6Q_USDHC_PAD_CTRL)
#define _MX6Q_PAD_GPIO_1__PWM2_PWMO			\
		IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_1__GPIO_1_1			\
		IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_1__USDHC1_CD			\
		IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_1__SRC_TESTER_ACK				\
		IOMUX_PAD(0x05F4, 0x0224, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_GPIO_9__ESAI1_FSR			\
		IOMUX_PAD(0x05F8, 0x0228, 0, 0x085C, 1, 0)
#define _MX6Q_PAD_GPIO_9__WDOG1_WDOG_B			\
		IOMUX_PAD(0x05F8, 0x0228, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_9__KPP_COL_6			\
		IOMUX_PAD(0x05F8, 0x0228, 2, 0x08EC, 0, 0)
#define _MX6Q_PAD_GPIO_9__CCM_REF_EN_B			\
		IOMUX_PAD(0x05F8, 0x0228, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_9__PWM1_PWMO			\
		IOMUX_PAD(0x05F8, 0x0228, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_9__GPIO_1_9			\
		IOMUX_PAD(0x05F8, 0x0228, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_9__USDHC1_WP			\
		IOMUX_PAD(0x05F8, 0x0228, 6, 0x094C, 1, 0)
#define _MX6Q_PAD_GPIO_9__SRC_EARLY_RST			\
		IOMUX_PAD(0x05F8, 0x0228, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_GPIO_3__ESAI1_HCKR			\
		IOMUX_PAD(0x05FC, 0x022C, 0, 0x0864, 1, 0)
#define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0		\
		IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_3__I2C3_SCL			\
		IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0)
#define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT		\
		IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_3__CCM_CLKO2			\
		IOMUX_PAD(0x05FC, 0x022C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_3__GPIO_1_3			\
		IOMUX_PAD(0x05FC, 0x022C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC				\
		IOMUX_PAD(0x05FC, 0x022C, 6, 0x0948, 1, 0)
#define _MX6Q_PAD_GPIO_3__MLB_MLBCLK			\
		IOMUX_PAD(0x05FC, 0x022C, 7, 0x0900, 1, 0)

#define _MX6Q_PAD_GPIO_6__ESAI1_SCKT			\
		IOMUX_PAD(0x0600, 0x0230, 0, 0x0870, 1, 0)
#define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1		\
		IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_6__I2C3_SDA			\
		IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0)
#define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0			\
		IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB				\
		IOMUX_PAD(0x0600, 0x0230, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_6__GPIO_1_6			\
		IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_6__USDHC2_LCTL			\
		IOMUX_PAD(0x0600, 0x0230, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_6__MLB_MLBSIG			\
		IOMUX_PAD(0x0600, 0x0230, 7, 0x0908, 1, 0)

#define _MX6Q_PAD_GPIO_2__ESAI1_FST			\
		IOMUX_PAD(0x0604, 0x0234, 0, 0x0860, 1, 0)
#define _MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2		\
		IOMUX_PAD(0x0604, 0x0234, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_2__KPP_ROW_6			\
		IOMUX_PAD(0x0604, 0x0234, 2, 0x08F8, 1, 0)
#define _MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1			\
		IOMUX_PAD(0x0604, 0x0234, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0		\
		IOMUX_PAD(0x0604, 0x0234, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_2__GPIO_1_2			\
		IOMUX_PAD(0x0604, 0x0234, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_2__USDHC2_WP			\
		IOMUX_PAD(0x0604, 0x0234, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_2__MLB_MLBDAT			\
		IOMUX_PAD(0x0604, 0x0234, 7, 0x0904, 1, 0)

#define _MX6Q_PAD_GPIO_4__ESAI1_HCKT			\
		IOMUX_PAD(0x0608, 0x0238, 0, 0x0868, 1, 0)
#define _MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3		\
		IOMUX_PAD(0x0608, 0x0238, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_4__KPP_COL_7			\
		IOMUX_PAD(0x0608, 0x0238, 2, 0x08F0, 1, 0)
#define _MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2			\
		IOMUX_PAD(0x0608, 0x0238, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1		\
		IOMUX_PAD(0x0608, 0x0238, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_4__GPIO_1_4			\
		IOMUX_PAD(0x0608, 0x0238, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_4__USDHC2_CD			\
		IOMUX_PAD(0x0608, 0x0238, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED		\
		IOMUX_PAD(0x0608, 0x0238, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3			\
		IOMUX_PAD(0x060C, 0x023C, 0, 0x087C, 1, 0)
#define _MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4		\
		IOMUX_PAD(0x060C, 0x023C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_5__KPP_ROW_7			\
		IOMUX_PAD(0x060C, 0x023C, 2, 0x08FC, 1, 0)
#define _MX6Q_PAD_GPIO_5__CCM_CLKO			\
		IOMUX_PAD(0x060C, 0x023C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2		\
		IOMUX_PAD(0x060C, 0x023C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_5__GPIO_1_5			\
		IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_5__I2C3_SCL			\
		IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0)
#define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI				\
		IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1			\
		IOMUX_PAD(0x0610, 0x0240, 0, 0x0884, 1, 0)
#define _MX6Q_PAD_GPIO_7__ECSPI5_RDY			\
		IOMUX_PAD(0x0610, 0x0240, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_7__EPIT1_EPITO			\
		IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_7__CAN1_TXCAN			\
		IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_7__UART2_TXD			\
		IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_7__UART2_RXD			\
		IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0)
#define _MX6Q_PAD_GPIO_7__GPIO_1_7			\
		IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_7__SPDIF_PLOCK			\
		IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE		\
		IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0			\
		IOMUX_PAD(0x0614, 0x0244, 0, 0x0888, 1, 0)
#define _MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT		\
		IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_8__EPIT2_EPITO			\
		IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_8__CAN1_RXCAN			\
		IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0)
#define _MX6Q_PAD_GPIO_8__UART2_TXD			\
		IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_8__UART2_RXD			\
		IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0)
#define _MX6Q_PAD_GPIO_8__GPIO_1_8			\
		IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_8__SPDIF_SRCLK			\
		IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP		\
		IOMUX_PAD(0x0614, 0x0244, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2				\
		IOMUX_PAD(0x0618, 0x0248, 0, 0x0880, 1, 0)
#define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN		\
		IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT		\
		IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0)
#define _MX6Q_PAD_GPIO_16__USDHC1_LCTL			\
		IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_16__SPDIF_IN1			\
		IOMUX_PAD(0x0618, 0x0248, 4, 0x0914, 3, 0)
#define _MX6Q_PAD_GPIO_16__GPIO_7_11			\
		IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_16__I2C3_SDA			\
		IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0)
#define _MX6Q_PAD_GPIO_16__SJC_DE_B			\
		IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_GPIO_17__ESAI1_TX0			\
		IOMUX_PAD(0x061C, 0x024C, 0, 0x0874, 0, 0)
#define _MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN		\
		IOMUX_PAD(0x061C, 0x024C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_17__CCM_PMIC_RDY			\
		IOMUX_PAD(0x061C, 0x024C, 2, 0x07F0, 1, 0)
#define _MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0		\
		IOMUX_PAD(0x061C, 0x024C, 3, 0x090C, 1, 0)
#define _MX6Q_PAD_GPIO_17__SPDIF_OUT1			\
		IOMUX_PAD(0x061C, 0x024C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_17__GPIO_7_12			\
		IOMUX_PAD(0x061C, 0x024C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_17__SJC_JTAG_ACT			\
		IOMUX_PAD(0x061C, 0x024C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_GPIO_18__ESAI1_TX1			\
		IOMUX_PAD(0x0620, 0x0250, 0, 0x0878, 0, 0)
#define _MX6Q_PAD_GPIO_18__ENET_RX_CLK			\
		IOMUX_PAD(0x0620, 0x0250, 1, 0x0844, 1, 0)
#define _MX6Q_PAD_GPIO_18__USDHC3_VSELECT				\
		IOMUX_PAD(0x0620, 0x0250, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1		\
		IOMUX_PAD(0x0620, 0x0250, 3, 0x0910, 1, 0)
#define _MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK			\
		IOMUX_PAD(0x0620, 0x0250, 4, 0x07B0, 2, 0)
#define _MX6Q_PAD_GPIO_18__GPIO_7_13			\
		IOMUX_PAD(0x0620, 0x0250, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL		\
		IOMUX_PAD(0x0620, 0x0250, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST				\
		IOMUX_PAD(0x0620, 0x0250, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_GPIO_19__KPP_COL_5			\
		IOMUX_PAD(0x0624, 0x0254, 0, 0x08E8, 1, 0)
#define _MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT		\
		IOMUX_PAD(0x0624, 0x0254, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_19__SPDIF_OUT1			\
		IOMUX_PAD(0x0624, 0x0254, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_19__CCM_CLKO			\
		IOMUX_PAD(0x0624, 0x0254, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_19__ECSPI1_RDY			\
		IOMUX_PAD(0x0624, 0x0254, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_19__GPIO_4_5			\
		IOMUX_PAD(0x0624, 0x0254, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_19__ENET_TX_ER			\
		IOMUX_PAD(0x0624, 0x0254, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_19__SRC_INT_BOOT			\
		IOMUX_PAD(0x0624, 0x0254, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK		\
		IOMUX_PAD(0x0628, 0x0258, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12		\
		IOMUX_PAD(0x0628, 0x0258, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0		\
		IOMUX_PAD(0x0628, 0x0258, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18				\
		IOMUX_PAD(0x0628, 0x0258, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29		\
		IOMUX_PAD(0x0628, 0x0258, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO		\
		IOMUX_PAD(0x0628, 0x0258, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC			\
		IOMUX_PAD(0x062C, 0x025C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13		\
		IOMUX_PAD(0x062C, 0x025C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_MCLK__CCM_CLKO			\
		IOMUX_PAD(0x062C, 0x025C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1			\
		IOMUX_PAD(0x062C, 0x025C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_MCLK__GPIO_5_19			\
		IOMUX_PAD(0x062C, 0x025C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30		\
		IOMUX_PAD(0x062C, 0x025C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL		\
		IOMUX_PAD(0x062C, 0x025C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN		\
		IOMUX_PAD(0x0630, 0x0260, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0		\
		IOMUX_PAD(0x0630, 0x0260, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14		\
		IOMUX_PAD(0x0630, 0x0260, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2		\
		IOMUX_PAD(0x0630, 0x0260, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20				\
		IOMUX_PAD(0x0630, 0x0260, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31		\
		IOMUX_PAD(0x0630, 0x0260, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK		\
		IOMUX_PAD(0x0630, 0x0260, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC		\
		IOMUX_PAD(0x0634, 0x0264, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1			\
		IOMUX_PAD(0x0634, 0x0264, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15		\
		IOMUX_PAD(0x0634, 0x0264, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3		\
		IOMUX_PAD(0x0634, 0x0264, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_VSYNC__GPIO_5_21			\
		IOMUX_PAD(0x0634, 0x0264, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32		\
		IOMUX_PAD(0x0634, 0x0264, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0		\
		IOMUX_PAD(0x0634, 0x0264, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4		\
		IOMUX_PAD(0x0638, 0x0268, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2		\
		IOMUX_PAD(0x0638, 0x0268, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK				\
		IOMUX_PAD(0x0638, 0x0268, 2, 0x07F4, 3, 0)
#define _MX6Q_PAD_CSI0_DAT4__KPP_COL_5			\
		IOMUX_PAD(0x0638, 0x0268, 3, 0x08E8, 2, 0)
#define _MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC			\
		IOMUX_PAD(0x0638, 0x0268, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT4__GPIO_5_22			\
		IOMUX_PAD(0x0638, 0x0268, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43		\
		IOMUX_PAD(0x0638, 0x0268, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1			\
		IOMUX_PAD(0x0638, 0x0268, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5		\
		IOMUX_PAD(0x063C, 0x026C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3		\
		IOMUX_PAD(0x063C, 0x026C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI				\
		IOMUX_PAD(0x063C, 0x026C, 2, 0x07FC, 3, 0)
#define _MX6Q_PAD_CSI0_DAT5__KPP_ROW_5			\
		IOMUX_PAD(0x063C, 0x026C, 3, 0x08F4, 1, 0)
#define _MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD			\
		IOMUX_PAD(0x063C, 0x026C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT5__GPIO_5_23			\
		IOMUX_PAD(0x063C, 0x026C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44		\
		IOMUX_PAD(0x063C, 0x026C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2			\
		IOMUX_PAD(0x063C, 0x026C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6		\
		IOMUX_PAD(0x0640, 0x0270, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4		\
		IOMUX_PAD(0x0640, 0x0270, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO				\
		IOMUX_PAD(0x0640, 0x0270, 2, 0x07F8, 3, 0)
#define _MX6Q_PAD_CSI0_DAT6__KPP_COL_6			\
		IOMUX_PAD(0x0640, 0x0270, 3, 0x08EC, 1, 0)
#define _MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS		\
		IOMUX_PAD(0x0640, 0x0270, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT6__GPIO_5_24			\
		IOMUX_PAD(0x0640, 0x0270, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45		\
		IOMUX_PAD(0x0640, 0x0270, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3			\
		IOMUX_PAD(0x0640, 0x0270, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7		\
		IOMUX_PAD(0x0644, 0x0274, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5		\
		IOMUX_PAD(0x0644, 0x0274, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0			\
		IOMUX_PAD(0x0644, 0x0274, 2, 0x0800, 3, 0)
#define _MX6Q_PAD_CSI0_DAT7__KPP_ROW_6			\
		IOMUX_PAD(0x0644, 0x0274, 3, 0x08F8, 2, 0)
#define _MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD			\
		IOMUX_PAD(0x0644, 0x0274, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT7__GPIO_5_25			\
		IOMUX_PAD(0x0644, 0x0274, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46		\
		IOMUX_PAD(0x0644, 0x0274, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4			\
		IOMUX_PAD(0x0644, 0x0274, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8		\
		IOMUX_PAD(0x0648, 0x0278, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6		\
		IOMUX_PAD(0x0648, 0x0278, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK				\
		IOMUX_PAD(0x0648, 0x0278, 2, 0x0810, 2, 0)
#define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7			\
		IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0)
#define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA			\
		IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0)
#define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26			\
		IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47		\
		IOMUX_PAD(0x0648, 0x0278, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5			\
		IOMUX_PAD(0x0648, 0x0278, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9		\
		IOMUX_PAD(0x064C, 0x027C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7		\
		IOMUX_PAD(0x064C, 0x027C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI				\
		IOMUX_PAD(0x064C, 0x027C, 2, 0x0818, 2, 0)
#define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7			\
		IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0)
#define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL			\
		IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0)
#define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27			\
		IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48		\
		IOMUX_PAD(0x064C, 0x027C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6			\
		IOMUX_PAD(0x064C, 0x027C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10			\
		IOMUX_PAD(0x0650, 0x0280, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC		\
		IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO				\
		IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0)
#define _MX6Q_PAD_CSI0_DAT10__UART1_TXD			\
		IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT10__UART1_RXD			\
		IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0)
#define _MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4		\
		IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT10__GPIO_5_28			\
		IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33		\
		IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7		\
		IOMUX_PAD(0x0650, 0x0280, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11			\
		IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS		\
		IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0				\
		IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0)
#define _MX6Q_PAD_CSI0_DAT11__UART1_TXD			\
		IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT11__UART1_RXD			\
		IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0)
#define _MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5		\
		IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT11__GPIO_5_29			\
		IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34		\
		IOMUX_PAD(0x0654, 0x0284, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8		\
		IOMUX_PAD(0x0654, 0x0284, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12			\
		IOMUX_PAD(0x0658, 0x0288, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8			\
		IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16		\
		IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT12__UART4_TXD			\
		IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT12__UART4_RXD			\
		IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0)
#define _MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6		\
		IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT12__GPIO_5_30			\
		IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35		\
		IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9		\
		IOMUX_PAD(0x0658, 0x0288, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13			\
		IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9			\
		IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17		\
		IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT13__UART4_TXD			\
		IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT13__UART4_RXD			\
		IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0)
#define _MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7		\
		IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT13__GPIO_5_31			\
		IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36		\
		IOMUX_PAD(0x065C, 0x028C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10		\
		IOMUX_PAD(0x065C, 0x028C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14			\
		IOMUX_PAD(0x0660, 0x0290, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10			\
		IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18		\
		IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT14__UART5_TXD			\
		IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT14__UART5_RXD			\
		IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0)
#define _MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8		\
		IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT14__GPIO_6_0			\
		IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37		\
		IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11		\
		IOMUX_PAD(0x0660, 0x0290, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15			\
		IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11			\
		IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19		\
		IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT15__UART5_TXD			\
		IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT15__UART5_RXD			\
		IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0)
#define _MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9		\
		IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT15__GPIO_6_1			\
		IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38		\
		IOMUX_PAD(0x0664, 0x0294, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12		\
		IOMUX_PAD(0x0664, 0x0294, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16			\
		IOMUX_PAD(0x0668, 0x0298, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12			\
		IOMUX_PAD(0x0668, 0x0298, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20		\
		IOMUX_PAD(0x0668, 0x0298, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT16__UART4_CTS			\
		IOMUX_PAD(0x0668, 0x0298, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT16__UART4_RTS			\
		IOMUX_PAD(0x0668, 0x0298, 3, 0x0934, 0, 0)
#define _MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10		\
		IOMUX_PAD(0x0668, 0x0298, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT16__GPIO_6_2			\
		IOMUX_PAD(0x0668, 0x0298, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39		\
		IOMUX_PAD(0x0668, 0x0298, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13		\
		IOMUX_PAD(0x0668, 0x0298, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17			\
		IOMUX_PAD(0x066C, 0x029C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13			\
		IOMUX_PAD(0x066C, 0x029C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21		\
		IOMUX_PAD(0x066C, 0x029C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT17__UART4_CTS			\
		IOMUX_PAD(0x066C, 0x029C, 3, 0x0934, 1, 0)
#define _MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11		\
		IOMUX_PAD(0x066C, 0x029C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT17__GPIO_6_3			\
		IOMUX_PAD(0x066C, 0x029C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40		\
		IOMUX_PAD(0x066C, 0x029C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14		\
		IOMUX_PAD(0x066C, 0x029C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18			\
		IOMUX_PAD(0x0670, 0x02A0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14			\
		IOMUX_PAD(0x0670, 0x02A0, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22		\
		IOMUX_PAD(0x0670, 0x02A0, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT18__UART5_CTS			\
		IOMUX_PAD(0x0670, 0x02A0, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT18__UART5_RTS			\
		IOMUX_PAD(0x0670, 0x02A0, 3, 0x093C, 2, 0)
#define _MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12		\
		IOMUX_PAD(0x0670, 0x02A0, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT18__GPIO_6_4			\
		IOMUX_PAD(0x0670, 0x02A0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41		\
		IOMUX_PAD(0x0670, 0x02A0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15		\
		IOMUX_PAD(0x0670, 0x02A0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19			\
		IOMUX_PAD(0x0674, 0x02A4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15			\
		IOMUX_PAD(0x0674, 0x02A4, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23		\
		IOMUX_PAD(0x0674, 0x02A4, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT19__UART5_CTS			\
		IOMUX_PAD(0x0674, 0x02A4, 3, 0x093C, 3, 0)
#define _MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13		\
		IOMUX_PAD(0x0674, 0x02A4, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT19__GPIO_6_5			\
		IOMUX_PAD(0x0674, 0x02A4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42		\
		IOMUX_PAD(0x0674, 0x02A4, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9		\
		IOMUX_PAD(0x0674, 0x02A4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_JTAG_TMS__SJC_TMS			\
		IOMUX_PAD(0x0678, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_JTAG_MOD__SJC_MOD			\
		IOMUX_PAD(0x067C, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB			\
		IOMUX_PAD(0x0680, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_JTAG_TDI__SJC_TDI			\
		IOMUX_PAD(0x0684, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_JTAG_TCK__SJC_TCK			\
		IOMUX_PAD(0x0688, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_JTAG_TDO__SJC_TDO			\
		IOMUX_PAD(0x068C, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3			\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2			\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK			\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1			\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0			\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3			\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK			\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2			\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1			\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0			\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_POR_B__SRC_POR_B			\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_RESET_IN_B__SRC_RESET_B				\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_TEST_MODE__TCU_TEST_MODE		\
		IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0)

#define _MX6Q_PAD_SD3_DAT7__USDHC3_DAT7			\
		IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT7__UART1_TXD			\
		IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT7__UART1_RXD			\
		IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0)
#define _MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24		\
		IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0		\
		IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0		\
		IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT7__GPIO_6_17			\
		IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12		\
		IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV		\
		IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD3_DAT6__USDHC3_DAT6			\
		IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT6__UART1_TXD			\
		IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT6__UART1_RXD			\
		IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0)
#define _MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25		\
		IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1		\
		IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1		\
		IOMUX_PAD(0x0694, 0x02AC, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT6__GPIO_6_18			\
		IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13		\
		IOMUX_PAD(0x0694, 0x02AC, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10		\
		IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD3_DAT5__USDHC3_DAT5			\
		IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT5__UART2_TXD			\
		IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT5__UART2_RXD			\
		IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0)
#define _MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26		\
		IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2		\
		IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2		\
		IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT5__GPIO_7_0			\
		IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14		\
		IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11		\
		IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD3_DAT4__USDHC3_DAT4			\
		IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT4__UART2_TXD			\
		IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT4__UART2_RXD			\
		IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0)
#define _MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27		\
		IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3		\
		IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3		\
		IOMUX_PAD(0x069C, 0x02B4, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT4__GPIO_7_1			\
		IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15		\
		IOMUX_PAD(0x069C, 0x02B4, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12		\
		IOMUX_PAD(0x069C, 0x02B4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD3_CMD__USDHC3_CMD			\
		IOMUX_PAD(0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_CMD__UART2_CTS			\
		IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0924, 2, 0)
#define _MX6Q_PAD_SD3_CMD__CAN1_TXCAN			\
		IOMUX_PAD(0x06A0, 0x02B8, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4		\
		IOMUX_PAD(0x06A0, 0x02B8, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4		\
		IOMUX_PAD(0x06A0, 0x02B8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_CMD__GPIO_7_2			\
		IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16		\
		IOMUX_PAD(0x06A0, 0x02B8, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13		\
		IOMUX_PAD(0x06A0, 0x02B8, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD3_CLK__USDHC3_CLK			\
		IOMUX_PAD(0x06A4, 0x02BC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_CLK__UART2_CTS			\
		IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_CLK__UART2_RTS			\
		IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0924, 3, 0)
#define _MX6Q_PAD_SD3_CLK__CAN1_RXCAN			\
		IOMUX_PAD(0x06A4, 0x02BC, 2, 0x07E4, 2, 0)
#define _MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5		\
		IOMUX_PAD(0x06A4, 0x02BC, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5		\
		IOMUX_PAD(0x06A4, 0x02BC, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_CLK__GPIO_7_3			\
		IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17		\
		IOMUX_PAD(0x06A4, 0x02BC, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14		\
		IOMUX_PAD(0x06A4, 0x02BC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD3_DAT0__USDHC3_DAT0			\
		IOMUX_PAD(0x06A8, 0x02C0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT0__UART1_CTS			\
		IOMUX_PAD(0x06A8, 0x02C0, 1, 0x091C, 2, 0)
#define _MX6Q_PAD_SD3_DAT0__CAN2_TXCAN			\
		IOMUX_PAD(0x06A8, 0x02C0, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6		\
		IOMUX_PAD(0x06A8, 0x02C0, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6		\
		IOMUX_PAD(0x06A8, 0x02C0, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT0__GPIO_7_4			\
		IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18		\
		IOMUX_PAD(0x06A8, 0x02C0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15		\
		IOMUX_PAD(0x06A8, 0x02C0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD3_DAT1__USDHC3_DAT1			\
		IOMUX_PAD(0x06AC, 0x02C4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT1__UART1_CTS			\
		IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT1__UART1_RTS			\
		IOMUX_PAD(0x06AC, 0x02C4, 1, 0x091C, 3, 0)
#define _MX6Q_PAD_SD3_DAT1__CAN2_RXCAN			\
		IOMUX_PAD(0x06AC, 0x02C4, 2, 0x07E8, 1, 0)
#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7		\
		IOMUX_PAD(0x06AC, 0x02C4, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7		\
		IOMUX_PAD(0x06AC, 0x02C4, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT1__GPIO_7_5			\
		IOMUX_PAD(0x06AC, 0x02C4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19		\
		IOMUX_PAD(0x06AC, 0x02C4, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0		\
		IOMUX_PAD(0x06AC, 0x02C4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD3_DAT2__USDHC3_DAT2			\
		IOMUX_PAD(0x06B0, 0x02C8, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28		\
		IOMUX_PAD(0x06B0, 0x02C8, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8		\
		IOMUX_PAD(0x06B0, 0x02C8, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8		\
		IOMUX_PAD(0x06B0, 0x02C8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT2__GPIO_7_6			\
		IOMUX_PAD(0x06B0, 0x02C8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20		\
		IOMUX_PAD(0x06B0, 0x02C8, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1		\
		IOMUX_PAD(0x06B0, 0x02C8, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD3_DAT3__USDHC3_DAT3			\
		IOMUX_PAD(0x06B4, 0x02CC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT3__UART3_CTS			\
		IOMUX_PAD(0x06B4, 0x02CC, 1, 0x092C, 4, 0)
#define _MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29		\
		IOMUX_PAD(0x06B4, 0x02CC, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9		\
		IOMUX_PAD(0x06B4, 0x02CC, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9		\
		IOMUX_PAD(0x06B4, 0x02CC, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT3__GPIO_7_7			\
		IOMUX_PAD(0x06B4, 0x02CC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21		\
		IOMUX_PAD(0x06B4, 0x02CC, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2		\
		IOMUX_PAD(0x06B4, 0x02CC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD3_RST__USDHC3_RST			\
		IOMUX_PAD(0x06B8, 0x02D0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_RST__UART3_CTS			\
		IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_RST__UART3_RTS			\
		IOMUX_PAD(0x06B8, 0x02D0, 1, 0x092C, 5, 0)
#define _MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30		\
		IOMUX_PAD(0x06B8, 0x02D0, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10		\
		IOMUX_PAD(0x06B8, 0x02D0, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10		\
		IOMUX_PAD(0x06B8, 0x02D0, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_RST__GPIO_7_8			\
		IOMUX_PAD(0x06B8, 0x02D0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22		\
		IOMUX_PAD(0x06B8, 0x02D0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3		\
		IOMUX_PAD(0x06B8, 0x02D0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_CLE__RAWNAND_CLE				\
		IOMUX_PAD(0x06BC, 0x02D4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CLE__IPU2_SISG_4				\
		IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31		\
		IOMUX_PAD(0x06BC, 0x02D4, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11		\
		IOMUX_PAD(0x06BC, 0x02D4, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11		\
		IOMUX_PAD(0x06BC, 0x02D4, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CLE__GPIO_6_7			\
		IOMUX_PAD(0x06BC, 0x02D4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23		\
		IOMUX_PAD(0x06BC, 0x02D4, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0			\
		IOMUX_PAD(0x06BC, 0x02D4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_ALE__RAWNAND_ALE				\
		IOMUX_PAD(0x06C0, 0x02D8, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_ALE__USDHC4_RST			\
		IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0		\
		IOMUX_PAD(0x06C0, 0x02D8, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12		\
		IOMUX_PAD(0x06C0, 0x02D8, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12		\
		IOMUX_PAD(0x06C0, 0x02D8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_ALE__GPIO_6_8			\
		IOMUX_PAD(0x06C0, 0x02D8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24		\
		IOMUX_PAD(0x06C0, 0x02D8, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1			\
		IOMUX_PAD(0x06C0, 0x02D8, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN			\
		IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5				\
		IOMUX_PAD(0x06C4, 0x02DC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1		\
		IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13		\
		IOMUX_PAD(0x06C4, 0x02DC, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13		\
		IOMUX_PAD(0x06C4, 0x02DC, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_WP_B__GPIO_6_9			\
		IOMUX_PAD(0x06C4, 0x02DC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32		\
		IOMUX_PAD(0x06C4, 0x02DC, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0		\
		IOMUX_PAD(0x06C4, 0x02DC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_RB0__RAWNAND_READY0			\
		IOMUX_PAD(0x06C8, 0x02E0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1		\
		IOMUX_PAD(0x06C8, 0x02E0, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2		\
		IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14		\
		IOMUX_PAD(0x06C8, 0x02E0, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14		\
		IOMUX_PAD(0x06C8, 0x02E0, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_RB0__GPIO_6_10			\
		IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33		\
		IOMUX_PAD(0x06C8, 0x02E0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1		\
		IOMUX_PAD(0x06C8, 0x02E0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N				\
		IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15		\
		IOMUX_PAD(0x06CC, 0x02E4, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15		\
		IOMUX_PAD(0x06CC, 0x02E4, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS0__GPIO_6_11			\
		IOMUX_PAD(0x06CC, 0x02E4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2		\
		IOMUX_PAD(0x06CC, 0x02E4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N				\
		IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT			\
		IOMUX_PAD(0x06D0, 0x02E8, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT			\
		IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3		\
		IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS1__GPIO_6_14			\
		IOMUX_PAD(0x06D0, 0x02E8, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT		\
		IOMUX_PAD(0x06D0, 0x02E8, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N				\
		IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS2__IPU1_SISG_0				\
		IOMUX_PAD(0x06D4, 0x02EC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS2__ESAI1_TX0			\
		IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0874, 1, 0)
#define _MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE		\
		IOMUX_PAD(0x06D4, 0x02EC, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS2__CCM_CLKO2			\
		IOMUX_PAD(0x06D4, 0x02EC, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS2__GPIO_6_15			\
		IOMUX_PAD(0x06D4, 0x02EC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS2__IPU2_SISG_0				\
		IOMUX_PAD(0x06D4, 0x02EC, 6, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N				\
		IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS3__IPU1_SISG_1				\
		IOMUX_PAD(0x06D8, 0x02F0, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS3__ESAI1_TX1			\
		IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0878, 1, 0)
#define _MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26			\
		IOMUX_PAD(0x06D8, 0x02F0, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4		\
		IOMUX_PAD(0x06D8, 0x02F0, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS3__GPIO_6_16			\
		IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS3__IPU2_SISG_1				\
		IOMUX_PAD(0x06D8, 0x02F0, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_CS3__TPSMP_CLK			\
		IOMUX_PAD(0x06D8, 0x02F0, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD4_CMD__USDHC4_CMD			\
		IOMUX_PAD(0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_CMD__RAWNAND_RDN			\
		IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_CMD__UART3_TXD			\
		IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_CMD__UART3_RXD			\
		IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0)
#define _MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5		\
		IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_CMD__GPIO_7_9			\
		IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR		\
		IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD4_CLK__USDHC4_CLK			\
		IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_CLK__RAWNAND_WRN			\
		IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_CLK__UART3_TXD			\
		IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_CLK__UART3_RXD			\
		IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0)
#define _MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6		\
		IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_CLK__GPIO_7_10			\
		IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_D0__RAWNAND_D0			\
		IOMUX_PAD(0x06E4, 0x02FC, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D0__USDHC1_DAT4			\
		IOMUX_PAD(0x06E4, 0x02FC, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0		\
		IOMUX_PAD(0x06E4, 0x02FC, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16		\
		IOMUX_PAD(0x06E4, 0x02FC, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16		\
		IOMUX_PAD(0x06E4, 0x02FC, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D0__GPIO_2_0			\
		IOMUX_PAD(0x06E4, 0x02FC, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0		\
		IOMUX_PAD(0x06E4, 0x02FC, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0		\
		IOMUX_PAD(0x06E4, 0x02FC, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_D1__RAWNAND_D1			\
		IOMUX_PAD(0x06E8, 0x0300, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D1__USDHC1_DAT5			\
		IOMUX_PAD(0x06E8, 0x0300, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1		\
		IOMUX_PAD(0x06E8, 0x0300, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17		\
		IOMUX_PAD(0x06E8, 0x0300, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17		\
		IOMUX_PAD(0x06E8, 0x0300, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D1__GPIO_2_1			\
		IOMUX_PAD(0x06E8, 0x0300, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1		\
		IOMUX_PAD(0x06E8, 0x0300, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1		\
		IOMUX_PAD(0x06E8, 0x0300, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_D2__RAWNAND_D2			\
		IOMUX_PAD(0x06EC, 0x0304, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D2__USDHC1_DAT6			\
		IOMUX_PAD(0x06EC, 0x0304, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2		\
		IOMUX_PAD(0x06EC, 0x0304, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18		\
		IOMUX_PAD(0x06EC, 0x0304, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18		\
		IOMUX_PAD(0x06EC, 0x0304, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D2__GPIO_2_2			\
		IOMUX_PAD(0x06EC, 0x0304, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2		\
		IOMUX_PAD(0x06EC, 0x0304, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2		\
		IOMUX_PAD(0x06EC, 0x0304, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_D3__RAWNAND_D3			\
		IOMUX_PAD(0x06F0, 0x0308, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D3__USDHC1_DAT7			\
		IOMUX_PAD(0x06F0, 0x0308, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3		\
		IOMUX_PAD(0x06F0, 0x0308, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19		\
		IOMUX_PAD(0x06F0, 0x0308, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19		\
		IOMUX_PAD(0x06F0, 0x0308, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D3__GPIO_2_3			\
		IOMUX_PAD(0x06F0, 0x0308, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3		\
		IOMUX_PAD(0x06F0, 0x0308, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3		\
		IOMUX_PAD(0x06F0, 0x0308, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_D4__RAWNAND_D4			\
		IOMUX_PAD(0x06F4, 0x030C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D4__USDHC2_DAT4			\
		IOMUX_PAD(0x06F4, 0x030C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4		\
		IOMUX_PAD(0x06F4, 0x030C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20		\
		IOMUX_PAD(0x06F4, 0x030C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20		\
		IOMUX_PAD(0x06F4, 0x030C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D4__GPIO_2_4			\
		IOMUX_PAD(0x06F4, 0x030C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4		\
		IOMUX_PAD(0x06F4, 0x030C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4		\
		IOMUX_PAD(0x06F4, 0x030C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_D5__RAWNAND_D5			\
		IOMUX_PAD(0x06F8, 0x0310, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D5__USDHC2_DAT5			\
		IOMUX_PAD(0x06F8, 0x0310, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5		\
		IOMUX_PAD(0x06F8, 0x0310, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21		\
		IOMUX_PAD(0x06F8, 0x0310, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21		\
		IOMUX_PAD(0x06F8, 0x0310, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D5__GPIO_2_5			\
		IOMUX_PAD(0x06F8, 0x0310, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5		\
		IOMUX_PAD(0x06F8, 0x0310, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5		\
		IOMUX_PAD(0x06F8, 0x0310, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_D6__RAWNAND_D6			\
		IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D6__USDHC2_DAT6			\
		IOMUX_PAD(0x06FC, 0x0314, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6		\
		IOMUX_PAD(0x06FC, 0x0314, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22		\
		IOMUX_PAD(0x06FC, 0x0314, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22		\
		IOMUX_PAD(0x06FC, 0x0314, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D6__GPIO_2_6			\
		IOMUX_PAD(0x06FC, 0x0314, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6		\
		IOMUX_PAD(0x06FC, 0x0314, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6		\
		IOMUX_PAD(0x06FC, 0x0314, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_NANDF_D7__RAWNAND_D7			\
		IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D7__USDHC2_DAT7			\
		IOMUX_PAD(0x0700, 0x0318, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7		\
		IOMUX_PAD(0x0700, 0x0318, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23		\
		IOMUX_PAD(0x0700, 0x0318, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23		\
		IOMUX_PAD(0x0700, 0x0318, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D7__GPIO_2_7			\
		IOMUX_PAD(0x0700, 0x0318, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7		\
		IOMUX_PAD(0x0700, 0x0318, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7		\
		IOMUX_PAD(0x0700, 0x0318, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD4_DAT0__RAWNAND_D8			\
		IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT0__USDHC4_DAT0			\
		IOMUX_PAD(0x0704, 0x031C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT0__RAWNAND_DQS			\
		IOMUX_PAD(0x0704, 0x031C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24		\
		IOMUX_PAD(0x0704, 0x031C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24		\
		IOMUX_PAD(0x0704, 0x031C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT0__GPIO_2_8			\
		IOMUX_PAD(0x0704, 0x031C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8		\
		IOMUX_PAD(0x0704, 0x031C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8		\
		IOMUX_PAD(0x0704, 0x031C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD4_DAT1__RAWNAND_D9			\
		IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT1__USDHC4_DAT1			\
		IOMUX_PAD(0x0708, 0x0320, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT1__PWM3_PWMO			\
		IOMUX_PAD(0x0708, 0x0320, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25		\
		IOMUX_PAD(0x0708, 0x0320, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25		\
		IOMUX_PAD(0x0708, 0x0320, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT1__GPIO_2_9			\
		IOMUX_PAD(0x0708, 0x0320, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9		\
		IOMUX_PAD(0x0708, 0x0320, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9		\
		IOMUX_PAD(0x0708, 0x0320, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD4_DAT2__RAWNAND_D10			\
		IOMUX_PAD(0x070C, 0x0324, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT2__USDHC4_DAT2			\
		IOMUX_PAD(0x070C, 0x0324, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT2__PWM4_PWMO			\
		IOMUX_PAD(0x070C, 0x0324, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26		\
		IOMUX_PAD(0x070C, 0x0324, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26		\
		IOMUX_PAD(0x070C, 0x0324, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT2__GPIO_2_10			\
		IOMUX_PAD(0x070C, 0x0324, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10		\
		IOMUX_PAD(0x070C, 0x0324, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10		\
		IOMUX_PAD(0x070C, 0x0324, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD4_DAT3__RAWNAND_D11			\
		IOMUX_PAD(0x0710, 0x0328, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT3__USDHC4_DAT3			\
		IOMUX_PAD(0x0710, 0x0328, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27		\
		IOMUX_PAD(0x0710, 0x0328, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27		\
		IOMUX_PAD(0x0710, 0x0328, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT3__GPIO_2_11			\
		IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11		\
		IOMUX_PAD(0x0710, 0x0328, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11		\
		IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD4_DAT4__RAWNAND_D12			\
		IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT4__USDHC4_DAT4			\
		IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT4__UART2_TXD			\
		IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT4__UART2_RXD			\
		IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0)
#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28		\
		IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28		\
		IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT4__GPIO_2_12			\
		IOMUX_PAD(0x0714, 0x032C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12		\
		IOMUX_PAD(0x0714, 0x032C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12		\
		IOMUX_PAD(0x0714, 0x032C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD4_DAT5__RAWNAND_D13			\
		IOMUX_PAD(0x0718, 0x0330, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT5__USDHC4_DAT5			\
		IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT5__UART2_CTS			\
		IOMUX_PAD(0x0718, 0x0330, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT5__UART2_RTS			\
		IOMUX_PAD(0x0718, 0x0330, 2, 0x0924, 4, 0)
#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29		\
		IOMUX_PAD(0x0718, 0x0330, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29		\
		IOMUX_PAD(0x0718, 0x0330, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT5__GPIO_2_13			\
		IOMUX_PAD(0x0718, 0x0330, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13		\
		IOMUX_PAD(0x0718, 0x0330, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13		\
		IOMUX_PAD(0x0718, 0x0330, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD4_DAT6__RAWNAND_D14			\
		IOMUX_PAD(0x071C, 0x0334, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT6__USDHC4_DAT6			\
		IOMUX_PAD(0x071C, 0x0334, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT6__UART2_CTS			\
		IOMUX_PAD(0x071C, 0x0334, 2, 0x0924, 5, 0)
#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30		\
		IOMUX_PAD(0x071C, 0x0334, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30		\
		IOMUX_PAD(0x071C, 0x0334, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT6__GPIO_2_14			\
		IOMUX_PAD(0x071C, 0x0334, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14		\
		IOMUX_PAD(0x071C, 0x0334, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14		\
		IOMUX_PAD(0x071C, 0x0334, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD4_DAT7__RAWNAND_D15			\
		IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT7__USDHC4_DAT7			\
		IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT7__UART2_TXD			\
		IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT7__UART2_RXD			\
		IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0)
#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31		\
		IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31		\
		IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT7__GPIO_2_15			\
		IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15		\
		IOMUX_PAD(0x0720, 0x0338, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15		\
		IOMUX_PAD(0x0720, 0x0338, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD1_DAT1__USDHC1_DAT1			\
		IOMUX_PAD(0x0724, 0x033C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT1__ECSPI5_SS0			\
		IOMUX_PAD(0x0724, 0x033C, 1, 0x0834, 1, 0)
#define _MX6Q_PAD_SD1_DAT1__PWM3_PWMO			\
		IOMUX_PAD(0x0724, 0x033C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT1__GPT_CAPIN2			\
		IOMUX_PAD(0x0724, 0x033C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7		\
		IOMUX_PAD(0x0724, 0x033C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT1__GPIO_1_17			\
		IOMUX_PAD(0x0724, 0x033C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0		\
		IOMUX_PAD(0x0724, 0x033C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8		\
		IOMUX_PAD(0x0724, 0x033C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD1_DAT0__USDHC1_DAT0			\
		IOMUX_PAD(0x0728, 0x0340, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT0__ECSPI5_MISO			\
		IOMUX_PAD(0x0728, 0x0340, 1, 0x082C, 1, 0)
#define _MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS		\
		IOMUX_PAD(0x0728, 0x0340, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT0__GPT_CAPIN1			\
		IOMUX_PAD(0x0728, 0x0340, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8		\
		IOMUX_PAD(0x0728, 0x0340, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT0__GPIO_1_16			\
		IOMUX_PAD(0x0728, 0x0340, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1		\
		IOMUX_PAD(0x0728, 0x0340, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7		\
		IOMUX_PAD(0x0728, 0x0340, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD1_DAT3__USDHC1_DAT3			\
		IOMUX_PAD(0x072C, 0x0344, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT3__ECSPI5_SS2			\
		IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3			\
		IOMUX_PAD(0x072C, 0x0344, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT3__PWM1_PWMO			\
		IOMUX_PAD(0x072C, 0x0344, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B				\
		IOMUX_PAD(0x072C, 0x0344, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT3__GPIO_1_21			\
		IOMUX_PAD(0x072C, 0x0344, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB		\
		IOMUX_PAD(0x072C, 0x0344, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6		\
		IOMUX_PAD(0x072C, 0x0344, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD1_CMD__USDHC1_CMD			\
		IOMUX_PAD(0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_CMD__ECSPI5_MOSI			\
		IOMUX_PAD(0x0730, 0x0348, 1, 0x0830, 0, 0)
#define _MX6Q_PAD_SD1_CMD__PWM4_PWMO			\
		IOMUX_PAD(0x0730, 0x0348, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_CMD__GPT_CMPOUT1			\
		IOMUX_PAD(0x0730, 0x0348, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_CMD__GPIO_1_18			\
		IOMUX_PAD(0x0730, 0x0348, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5		\
		IOMUX_PAD(0x0730, 0x0348, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD1_DAT2__USDHC1_DAT2			\
		IOMUX_PAD(0x0734, 0x034C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT2__ECSPI5_SS1			\
		IOMUX_PAD(0x0734, 0x034C, 1, 0x0838, 1, 0)
#define _MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2			\
		IOMUX_PAD(0x0734, 0x034C, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT2__PWM2_PWMO			\
		IOMUX_PAD(0x0734, 0x034C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B				\
		IOMUX_PAD(0x0734, 0x034C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT2__GPIO_1_19			\
		IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB		\
		IOMUX_PAD(0x0734, 0x034C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4		\
		IOMUX_PAD(0x0734, 0x034C, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD1_CLK__USDHC1_CLK			\
		IOMUX_PAD(0x0738, 0x0350, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_CLK__ECSPI5_SCLK			\
		IOMUX_PAD(0x0738, 0x0350, 1, 0x0828, 0, 0)
#define _MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT				\
		IOMUX_PAD(0x0738, 0x0350, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_CLK__GPT_CLKIN			\
		IOMUX_PAD(0x0738, 0x0350, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_CLK__GPIO_1_20			\
		IOMUX_PAD(0x0738, 0x0350, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_CLK__PHY_DTB_0			\
		IOMUX_PAD(0x0738, 0x0350, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0				\
		IOMUX_PAD(0x0738, 0x0350, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD2_CLK__USDHC2_CLK			\
		IOMUX_PAD(0x073C, 0x0354, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_CLK__ECSPI5_SCLK			\
		IOMUX_PAD(0x073C, 0x0354, 1, 0x0828, 1, 0)
#define _MX6Q_PAD_SD2_CLK__KPP_COL_5			\
		IOMUX_PAD(0x073C, 0x0354, 2, 0x08E8, 3, 0)
#define _MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS			\
		IOMUX_PAD(0x073C, 0x0354, 3, 0x07C0, 1, 0)
#define _MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9		\
		IOMUX_PAD(0x073C, 0x0354, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_CLK__GPIO_1_10			\
		IOMUX_PAD(0x073C, 0x0354, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_CLK__PHY_DTB_1			\
		IOMUX_PAD(0x073C, 0x0354, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1				\
		IOMUX_PAD(0x073C, 0x0354, 7, 0x0000, 0, 0)

#define _MX6Q_PAD_SD2_CMD__USDHC2_CMD			\
		IOMUX_PAD(0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_CMD__ECSPI5_MOSI			\
		IOMUX_PAD(0x0740, 0x0358, 1, 0x0830, 1, 0)
#define _MX6Q_PAD_SD2_CMD__KPP_ROW_5			\
		IOMUX_PAD(0x0740, 0x0358, 2, 0x08F4, 2, 0)
#define _MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC		\
		IOMUX_PAD(0x0740, 0x0358, 3, 0x07BC, 1, 0)
#define _MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10		\
		IOMUX_PAD(0x0740, 0x0358, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_CMD__GPIO_1_11			\
		IOMUX_PAD(0x0740, 0x0358, 5, 0x0000, 0, 0)

#define _MX6Q_PAD_SD2_DAT3__USDHC2_DAT3			\
		IOMUX_PAD(0x0744, 0x035C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT3__ECSPI5_SS3			\
		IOMUX_PAD(0x0744, 0x035C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT3__KPP_COL_6			\
		IOMUX_PAD(0x0744, 0x035C, 2, 0x08EC, 2, 0)
#define _MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC			\
		IOMUX_PAD(0x0744, 0x035C, 3, 0x07C4, 1, 0)
#define _MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11		\
		IOMUX_PAD(0x0744, 0x035C, 4, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT3__GPIO_1_12			\
		IOMUX_PAD(0x0744, 0x035C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT3__SJC_DONE			\
		IOMUX_PAD(0x0744, 0x035C, 6, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3		\
		IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0)

// @@START

#define  MX6Q_PAD_SD2_DAT1__USDHC2_DAT1		\
		(_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT1__ECSPI5_SS0		\
		(_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2		\
		(_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS		\
		(_MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT1__KPP_COL_7		\
		(_MX6Q_PAD_SD2_DAT1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT1__GPIO_1_14		\
		(_MX6Q_PAD_SD2_DAT1__GPIO_1_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT1__CCM_WAIT		\
		(_MX6Q_PAD_SD2_DAT1__CCM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0		\
		(_MX6Q_PAD_SD2_DAT1__ANATOP_ANATOP_TESTO_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD2_DAT2__USDHC2_DAT2		\
		(_MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT2__ECSPI5_SS1		\
		(_MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3		\
		(_MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD		\
		(_MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT2__KPP_ROW_6		\
		(_MX6Q_PAD_SD2_DAT2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT2__GPIO_1_13		\
		(_MX6Q_PAD_SD2_DAT2__GPIO_1_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT2__CCM_STOP		\
		(_MX6Q_PAD_SD2_DAT2__CCM_STOP | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1		\
		(_MX6Q_PAD_SD2_DAT2__ANATOP_ANATOP_TESTO_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD2_DAT0__USDHC2_DAT0		\
		(_MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT0__ECSPI5_MISO		\
		(_MX6Q_PAD_SD2_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD		\
		(_MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT0__KPP_ROW_7		\
		(_MX6Q_PAD_SD2_DAT0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT0__GPIO_1_15		\
		(_MX6Q_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT		\
		(_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2		\
		(_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 | MUX_PAD_CTRL(NO_PAD_CTRL))


#define  MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA		\
		(_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC		\
		(_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK		\
		(_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TXC__GPIO_6_19		\
		(_MX6Q_PAD_RGMII_TXC__GPIO_6_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0		\
		(_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT		\
		(_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))


#define  MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY		\
		(_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0		\
		(_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TD0__GPIO_6_20		\
		(_MX6Q_PAD_RGMII_TD0__GPIO_6_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1		\
		(_MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_TEST_IN_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG		\
		(_MX6Q_PAD_RGMII_TD1__MIPI_HSI_CTRL_RX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1		\
		(_MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TD1__GPIO_6_21		\
		(_MX6Q_PAD_RGMII_TD1__GPIO_6_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2		\
		(_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP		\
		(_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))


#define  MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA		\
		(_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2		\
		(_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TD2__GPIO_6_22		\
		(_MX6Q_PAD_RGMII_TD2__GPIO_6_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3		\
		(_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP		\
		(_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))


#define  MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE		\
		(_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3		\
		(_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TD3__GPIO_6_23		\
		(_MX6Q_PAD_RGMII_TD3__GPIO_6_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4		\
		(_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 | MUX_PAD_CTRL(NO_PAD_CTRL))


#define  MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA		\
		(_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL		\
		(_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24		\
		(_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5		\
		(_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 | MUX_PAD_CTRL(NO_PAD_CTRL))


#define  MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY		\
		(_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0		\
		(_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RD0__GPIO_6_25		\
		(_MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6		\
		(_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 | MUX_PAD_CTRL(NO_PAD_CTRL))


#define  MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE		\
		(_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START		\
		(_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | \
		 MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP)\
		 )
#define  MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL		\
		(_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26		\
		(_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7		\
		(_MX6Q_PAD_RGMII_TX_CTL__MIPI_CORE_DPHY_TEST_IN_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT		\
		(_MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG		\
		(_MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FLAG | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1		\
		(_MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RD1__GPIO_6_27		\
		(_MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8		\
		(_MX6Q_PAD_RGMII_RD1__MIPI_CORE_DPHY_TEST_IN_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RD1__SJC_FAIL		\
		(_MX6Q_PAD_RGMII_RD1__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA		\
		(_MX6Q_PAD_RGMII_RD2__MIPI_HSI_CTRL_TX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2		\
		(_MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RD2__GPIO_6_28		\
		(_MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9		\
		(_MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_TEST_IN_9 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE		\
		(_MX6Q_PAD_RGMII_RD3__MIPI_HSI_CTRL_TX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3		\
		(_MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RD3__GPIO_6_29		\
		(_MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10		\
		(_MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_TEST_IN_10 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE		\
		(_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE_START		\
		(_MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE | MUX_PAD_CTRL(MX6Q_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP))
#define  MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC		\
		(_MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RXC__GPIO_6_30		\
		(_MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11		\
		(_MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_TEST_IN_11 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25		\
		(_MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A25__ECSPI4_SS1		\
		(_MX6Q_PAD_EIM_A25__ECSPI4_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A25__ECSPI2_RDY		\
		(_MX6Q_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12		\
		(_MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS		\
		(_MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A25__GPIO_5_2		\
		(_MX6Q_PAD_EIM_A25__GPIO_5_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE		\
		(_MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0		\
		(_MX6Q_PAD_EIM_A25__PL301_MX6QPER1_HBURST_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2		\
		(_MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB2__ECSPI1_SS0		\
		(_MX6Q_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK		\
		(_MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19		\
		(_MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL		\
		(_MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB2__GPIO_2_30		\
		(_MX6Q_PAD_EIM_EB2__GPIO_2_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB2__I2C2_SCL		\
		(_MX6Q_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30		\
		(_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16		\
		(_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D16__ECSPI1_SCLK		\
		(_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
#define  MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5		\
		(_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18		\
		(_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA		\
		(_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D16__GPIO_3_16		\
		(_MX6Q_PAD_EIM_D16__GPIO_3_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D16__I2C2_SDA		\
		(_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17		\
		(_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D17__ECSPI1_MISO		\
		(_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
#define  MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6		\
		(_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK		\
		(_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT		\
		(_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D17__GPIO_3_17		\
		(_MX6Q_PAD_EIM_D17__GPIO_3_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D17__I2C3_SCL		\
		(_MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1		\
		(_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18		\
		(_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D18__ECSPI1_MOSI		\
		(_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
#define  MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7		\
		(_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17		\
		(_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS		\
		(_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D18__GPIO_3_18		\
		(_MX6Q_PAD_EIM_D18__GPIO_3_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D18__I2C3_SDA		\
		(_MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2		\
		(_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19		\
		(_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D19__ECSPI1_SS1		\
		(_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
#define  MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8		\
		(_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16		\
		(_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D19__UART1_CTS		\
		(_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D19__GPIO_3_19		\
		(_MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
#define  MX6Q_PAD_EIM_D19__EPIT1_EPITO		\
		(_MX6Q_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP		\
		(_MX6Q_PAD_EIM_D19__PL301_MX6QPER1_HRESP | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20		\
		(_MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D20__ECSPI4_SS0		\
		(_MX6Q_PAD_EIM_D20__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16		\
		(_MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15		\
		(_MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D20__UART1_CTS		\
		(_MX6Q_PAD_EIM_D20__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D20__UART1_RTS		\
		(_MX6Q_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D20__GPIO_3_20		\
		(_MX6Q_PAD_EIM_D20__GPIO_3_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D20__EPIT2_EPITO		\
		(_MX6Q_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21		\
		(_MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D21__ECSPI4_SCLK		\
		(_MX6Q_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17		\
		(_MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11		\
		(_MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC		\
		(_MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D21__GPIO_3_21		\
		(_MX6Q_PAD_EIM_D21__GPIO_3_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D21__I2C1_SCL		\
		(_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
#define  MX6Q_PAD_EIM_D21__SPDIF_IN1		\
		(_MX6Q_PAD_EIM_D21__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22		\
		(_MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D22__ECSPI4_MISO		\
		(_MX6Q_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1		\
		(_MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10		\
		(_MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR		\
		(_MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D22__GPIO_3_22		\
		(_MX6Q_PAD_EIM_D22__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D22__SPDIF_OUT1		\
		(_MX6Q_PAD_EIM_D22__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE		\
		(_MX6Q_PAD_EIM_D22__PL301_MX6QPER1_HWRITE | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23		\
		(_MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS		\
		(_MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D23__UART3_CTS		\
		(_MX6Q_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D23__UART1_DCD		\
		(_MX6Q_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN		\
		(_MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D23__GPIO_3_23		\
		(_MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2		\
		(_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14		\
		(_MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3		\
		(_MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB3__ECSPI4_RDY		\
		(_MX6Q_PAD_EIM_EB3__ECSPI4_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB3__UART3_CTS		\
		(_MX6Q_PAD_EIM_EB3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB3__UART3_RTS		\
		(_MX6Q_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB3__UART1_RI		\
		(_MX6Q_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC		\
		(_MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB3__GPIO_2_31		\
		(_MX6Q_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3		\
		(_MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31		\
		(_MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24		\
		(_MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D24__ECSPI4_SS2		\
		(_MX6Q_PAD_EIM_D24__ECSPI4_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D24__UART3_TXD		\
		(_MX6Q_PAD_EIM_D24__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D24__UART3_RXD		\
		(_MX6Q_PAD_EIM_D24__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D24__ECSPI1_SS2		\
		(_MX6Q_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D24__ECSPI2_SS2		\
		(_MX6Q_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D24__GPIO_3_24		\
		(_MX6Q_PAD_EIM_D24__GPIO_3_24 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
#define  MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS		\
		(_MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D24__UART1_DTR		\
		(_MX6Q_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))

#define  MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25		\
		(_MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D25__ECSPI4_SS3		\
		(_MX6Q_PAD_EIM_D25__ECSPI4_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D25__UART3_TXD		\
		(_MX6Q_PAD_EIM_D25__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D25__UART3_RXD		\
		(_MX6Q_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D25__ECSPI1_SS3		\
		(_MX6Q_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D25__ECSPI2_SS3		\
		(_MX6Q_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D25__GPIO_3_25		\
		(_MX6Q_PAD_EIM_D25__GPIO_3_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC		\
		(_MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D25__UART1_DSR		\
		(_MX6Q_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))

#define  MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26		\
		(_MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11		\
		(_MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1		\
		(_MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14		\
		(_MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D26__UART2_TXD		\
		(_MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D26__UART2_RXD		\
		(_MX6Q_PAD_EIM_D26__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D26__GPIO_3_26		\
		(_MX6Q_PAD_EIM_D26__GPIO_3_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D26__IPU1_SISG_2		\
		(_MX6Q_PAD_EIM_D26__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22		\
		(_MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27		\
		(_MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13		\
		(_MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0		\
		(_MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13		\
		(_MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D27__UART2_TXD		\
		(_MX6Q_PAD_EIM_D27__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D27__UART2_RXD		\
		(_MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D27__GPIO_3_27		\
		(_MX6Q_PAD_EIM_D27__GPIO_3_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D27__IPU1_SISG_3		\
		(_MX6Q_PAD_EIM_D27__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23		\
		(_MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28		\
		(_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D28__I2C1_SDA		\
		(_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
#define  MX6Q_PAD_EIM_D28__ECSPI4_MOSI		\
		(_MX6Q_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12		\
		(_MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D28__UART2_CTS		\
		(_MX6Q_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D28__UART2_RTS		\
		(_MX6Q_PAD_EIM_D28__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D28__GPIO_3_28		\
		(_MX6Q_PAD_EIM_D28__GPIO_3_28 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
#define  MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG		\
		(_MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13		\
		(_MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29		\
		(_MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15		\
		(_MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D29__ECSPI4_SS0		\
		(_MX6Q_PAD_EIM_D29__ECSPI4_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D29__UART2_CTS		\
		(_MX6Q_PAD_EIM_D29__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D29__UART2_RTS		\
		(_MX6Q_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D29__GPIO_3_29		\
		(_MX6Q_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC		\
		(_MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14		\
		(_MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30		\
		(_MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21		\
		(_MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11		\
		(_MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3		\
		(_MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D30__UART3_CTS		\
		(_MX6Q_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D30__GPIO_3_30		\
		(_MX6Q_PAD_EIM_D30__GPIO_3_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC		\
		(_MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0		\
		(_MX6Q_PAD_EIM_D30__PL301_MX6QPER1_HPROT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31		\
		(_MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20		\
		(_MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12		\
		(_MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2		\
		(_MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D31__UART3_CTS		\
		(_MX6Q_PAD_EIM_D31__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D31__UART3_RTS		\
		(_MX6Q_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_EIM_D31__GPIO_3_31		\
		(_MX6Q_PAD_EIM_D31__GPIO_3_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR		\
		(_MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1		\
		(_MX6Q_PAD_EIM_D31__PL301_MX6QPER1_HPROT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24		\
		(_MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19		\
		(_MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19		\
		(_MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A24__IPU2_SISG_2		\
		(_MX6Q_PAD_EIM_A24__IPU2_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A24__IPU1_SISG_2		\
		(_MX6Q_PAD_EIM_A24__IPU1_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A24__GPIO_5_4		\
		(_MX6Q_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2		\
		(_MX6Q_PAD_EIM_A24__PL301_MX6QPER1_HPROT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A24__SRC_BT_CFG_24		\
		(_MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23		\
		(_MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18		\
		(_MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18		\
		(_MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A23__IPU2_SISG_3		\
		(_MX6Q_PAD_EIM_A23__IPU2_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A23__IPU1_SISG_3		\
		(_MX6Q_PAD_EIM_A23__IPU1_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A23__GPIO_6_6		\
		(_MX6Q_PAD_EIM_A23__GPIO_6_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3		\
		(_MX6Q_PAD_EIM_A23__PL301_MX6QPER1_HPROT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A23__SRC_BT_CFG_23		\
		(_MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22		\
		(_MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17		\
		(_MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17		\
		(_MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A22__GPIO_2_16		\
		(_MX6Q_PAD_EIM_A22__GPIO_2_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A22__TPSMP_HDATA_0		\
		(_MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A22__SRC_BT_CFG_22		\
		(_MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21		\
		(_MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16		\
		(_MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16		\
		(_MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A21__RESERVED_RESERVED		\
		(_MX6Q_PAD_EIM_A21__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18		\
		(_MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_TEST_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A21__GPIO_2_17		\
		(_MX6Q_PAD_EIM_A21__GPIO_2_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A21__TPSMP_HDATA_1		\
		(_MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A21__SRC_BT_CFG_21		\
		(_MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20		\
		(_MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15		\
		(_MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15		\
		(_MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A20__RESERVED_RESERVED		\
		(_MX6Q_PAD_EIM_A20__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19		\
		(_MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_TEST_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A20__GPIO_2_18		\
		(_MX6Q_PAD_EIM_A20__GPIO_2_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A20__TPSMP_HDATA_2		\
		(_MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A20__SRC_BT_CFG_20		\
		(_MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19		\
		(_MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14		\
		(_MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14		\
		(_MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A19__RESERVED_RESERVED		\
		(_MX6Q_PAD_EIM_A19__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20		\
		(_MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_TEST_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A19__GPIO_2_19		\
		(_MX6Q_PAD_EIM_A19__GPIO_2_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A19__TPSMP_HDATA_3		\
		(_MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A19__SRC_BT_CFG_19		\
		(_MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18		\
		(_MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13		\
		(_MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13		\
		(_MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A18__RESERVED_RESERVED		\
		(_MX6Q_PAD_EIM_A18__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21		\
		(_MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_TEST_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A18__GPIO_2_20		\
		(_MX6Q_PAD_EIM_A18__GPIO_2_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A18__TPSMP_HDATA_4		\
		(_MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A18__SRC_BT_CFG_18		\
		(_MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17		\
		(_MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12		\
		(_MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12		\
		(_MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A17__RESERVED_RESERVED		\
		(_MX6Q_PAD_EIM_A17__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22		\
		(_MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_TEST_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A17__GPIO_2_21		\
		(_MX6Q_PAD_EIM_A17__GPIO_2_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A17__TPSMP_HDATA_5		\
		(_MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A17__SRC_BT_CFG_17		\
		(_MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16		\
		(_MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK		\
		(_MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK		\
		(_MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23		\
		(_MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_TEST_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A16__GPIO_2_22		\
		(_MX6Q_PAD_EIM_A16__GPIO_2_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A16__TPSMP_HDATA_6		\
		(_MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_A16__SRC_BT_CFG_16		\
		(_MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0		\
		(_MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5		\
		(_MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_CS0__ECSPI2_SCLK		\
		(_MX6Q_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24		\
		(_MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_TEST_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_CS0__GPIO_2_23		\
		(_MX6Q_PAD_EIM_CS0__GPIO_2_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7		\
		(_MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1		\
		(_MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6		\
		(_MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_CS1__ECSPI2_MOSI		\
		(_MX6Q_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25		\
		(_MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_TEST_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_CS1__GPIO_2_24		\
		(_MX6Q_PAD_EIM_CS1__GPIO_2_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8		\
		(_MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_OE__WEIM_WEIM_OE		\
		(_MX6Q_PAD_EIM_OE__WEIM_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7		\
		(_MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_OE__ECSPI2_MISO		\
		(_MX6Q_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26		\
		(_MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_TEST_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_OE__GPIO_2_25		\
		(_MX6Q_PAD_EIM_OE__GPIO_2_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_OE__TPSMP_HDATA_9		\
		(_MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_RW__WEIM_WEIM_RW		\
		(_MX6Q_PAD_EIM_RW__WEIM_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8		\
		(_MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_RW__ECSPI2_SS0		\
		(_MX6Q_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27		\
		(_MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_TEST_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_RW__GPIO_2_26		\
		(_MX6Q_PAD_EIM_RW__GPIO_2_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_RW__TPSMP_HDATA_10		\
		(_MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_RW__SRC_BT_CFG_29		\
		(_MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA		\
		(_MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17		\
		(_MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_LBA__ECSPI2_SS1		\
		(_MX6Q_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_LBA__GPIO_2_27		\
		(_MX6Q_PAD_EIM_LBA__GPIO_2_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11		\
		(_MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26		\
		(_MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0		\
		(_MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11		\
		(_MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11		\
		(_MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0		\
		(_MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_TEST_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY		\
		(_MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB0__GPIO_2_28		\
		(_MX6Q_PAD_EIM_EB0__GPIO_2_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12		\
		(_MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27		\
		(_MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1		\
		(_MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10		\
		(_MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10		\
		(_MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1		\
		(_MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY_TEST_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB1__GPIO_2_29		\
		(_MX6Q_PAD_EIM_EB1__GPIO_2_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13		\
		(_MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28		\
		(_MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0		\
		(_MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9		\
		(_MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9		\
		(_MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2		\
		(_MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY_TEST_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA0__GPIO_3_0		\
		(_MX6Q_PAD_EIM_DA0__GPIO_3_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14		\
		(_MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0		\
		(_MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1		\
		(_MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8		\
		(_MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8		\
		(_MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3		\
		(_MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_TEST_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE		\
		(_MX6Q_PAD_EIM_DA1__ANATOP_USBPHY1_TSTI_TX_LS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA1__GPIO_3_1		\
		(_MX6Q_PAD_EIM_DA1__GPIO_3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15		\
		(_MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1		\
		(_MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2		\
		(_MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7		\
		(_MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7		\
		(_MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4		\
		(_MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_TEST_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE		\
		(_MX6Q_PAD_EIM_DA2__ANATOP_USBPHY1_TSTI_TX_HS_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA2__GPIO_3_2		\
		(_MX6Q_PAD_EIM_DA2__GPIO_3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16		\
		(_MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2		\
		(_MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3		\
		(_MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6		\
		(_MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6		\
		(_MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5		\
		(_MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_TEST_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ		\
		(_MX6Q_PAD_EIM_DA3__ANATOP_USBPHY1_TSTI_TX_HIZ | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA3__GPIO_3_3		\
		(_MX6Q_PAD_EIM_DA3__GPIO_3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17		\
		(_MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3		\
		(_MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4		\
		(_MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5		\
		(_MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5		\
		(_MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6		\
		(_MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_TEST_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN		\
		(_MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TSTI_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA4__GPIO_3_4		\
		(_MX6Q_PAD_EIM_DA4__GPIO_3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18		\
		(_MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4		\
		(_MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5		\
		(_MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4		\
		(_MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4		\
		(_MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7		\
		(_MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_TEST_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP		\
		(_MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TSTI_TX_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA5__GPIO_3_5		\
		(_MX6Q_PAD_EIM_DA5__GPIO_3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19		\
		(_MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5		\
		(_MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6		\
		(_MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3		\
		(_MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3		\
		(_MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8		\
		(_MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_TEST_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN		\
		(_MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TSTI_TX_DN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA6__GPIO_3_6		\
		(_MX6Q_PAD_EIM_DA6__GPIO_3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20		\
		(_MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6		\
		(_MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7		\
		(_MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2		\
		(_MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2		\
		(_MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9		\
		(_MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_TEST_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA7__GPIO_3_7		\
		(_MX6Q_PAD_EIM_DA7__GPIO_3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21		\
		(_MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7		\
		(_MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8		\
		(_MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1		\
		(_MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1		\
		(_MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10		\
		(_MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_TEST_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA8__GPIO_3_8		\
		(_MX6Q_PAD_EIM_DA8__GPIO_3_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22		\
		(_MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8		\
		(_MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9		\
		(_MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0		\
		(_MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0		\
		(_MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11		\
		(_MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_TEST_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA9__GPIO_3_9		\
		(_MX6Q_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23		\
		(_MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9		\
		(_MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10		\
		(_MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15		\
		(_MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN		\
		(_MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12		\
		(_MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_TEST_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA10__GPIO_3_10		\
		(_MX6Q_PAD_EIM_DA10__GPIO_3_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24		\
		(_MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10		\
		(_MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11		\
		(_MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2		\
		(_MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC		\
		(_MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13		\
		(_MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_TEST_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6		\
		(_MX6Q_PAD_EIM_DA11__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA11__GPIO_3_11		\
		(_MX6Q_PAD_EIM_DA11__GPIO_3_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25		\
		(_MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11		\
		(_MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12		\
		(_MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3		\
		(_MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC		\
		(_MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14		\
		(_MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_TEST_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3		\
		(_MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA12__GPIO_3_12		\
		(_MX6Q_PAD_EIM_DA12__GPIO_3_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26		\
		(_MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12		\
		(_MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13		\
		(_MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS		\
		(_MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK		\
		(_MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15		\
		(_MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_TEST_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4		\
		(_MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA13__GPIO_3_13		\
		(_MX6Q_PAD_EIM_DA13__GPIO_3_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27		\
		(_MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13		\
		(_MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14		\
		(_MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS		\
		(_MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK		\
		(_MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16		\
		(_MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_TEST_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5		\
		(_MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA14__GPIO_3_14		\
		(_MX6Q_PAD_EIM_DA14__GPIO_3_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28		\
		(_MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14		\
		(_MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15		\
		(_MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1		\
		(_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4		\
		(_MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17		\
		(_MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_TEST_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA15__GPIO_3_15		\
		(_MX6Q_PAD_EIM_DA15__GPIO_3_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29		\
		(_MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15		\
		(_MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT		\
		(_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B		\
		(_MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_WAIT__GPIO_5_0		\
		(_MX6Q_PAD_EIM_WAIT__GPIO_5_0 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
#define  MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30		\
		(_MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25		\
		(_MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK		\
		(_MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16		\
		(_MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_BCLK__GPIO_6_31		\
		(_MX6Q_PAD_EIM_BCLK__GPIO_6_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31		\
		(_MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK		\
		(_MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK		\
		(_MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28		\
		(_MX6Q_PAD_DI0_DISP_CLK__MIPI_CORE_DPHY_TEST_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0		\
		(_MX6Q_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16		\
		(_MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0		\
		(_MX6Q_PAD_DI0_DISP_CLK__MMDC_MMDC_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15		\
		(_MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15		\
		(_MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC		\
		(_MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29		\
		(_MX6Q_PAD_DI0_PIN15__MIPI_CORE_DPHY_TEST_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1		\
		(_MX6Q_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN15__GPIO_4_17		\
		(_MX6Q_PAD_DI0_PIN15__GPIO_4_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1		\
		(_MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2		\
		(_MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2		\
		(_MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD		\
		(_MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30		\
		(_MX6Q_PAD_DI0_PIN2__MIPI_CORE_DPHY_TEST_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2		\
		(_MX6Q_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN2__GPIO_4_18		\
		(_MX6Q_PAD_DI0_PIN2__GPIO_4_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2		\
		(_MX6Q_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9		\
		(_MX6Q_PAD_DI0_PIN2__PL301_MX6QPER1_HADDR_9 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3		\
		(_MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3		\
		(_MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS		\
		(_MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31		\
		(_MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_TEST_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3		\
		(_MX6Q_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN3__GPIO_4_19		\
		(_MX6Q_PAD_DI0_PIN3__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3		\
		(_MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10		\
		(_MX6Q_PAD_DI0_PIN3__PL301_MX6QPER1_HADDR_10 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4		\
		(_MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4		\
		(_MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD		\
		(_MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN4__USDHC1_WP		\
		(_MX6Q_PAD_DI0_PIN4__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD		\
		(_MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN4__GPIO_4_20		\
		(_MX6Q_PAD_DI0_PIN4__GPIO_4_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4		\
		(_MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11		\
		(_MX6Q_PAD_DI0_PIN4__PL301_MX6QPER1_HADDR_11 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0		\
		(_MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0		\
		(_MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK		\
		(_MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0		\
		(_MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DEBUG_0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN		\
		(_MX6Q_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT0__GPIO_4_21		\
		(_MX6Q_PAD_DISP0_DAT0__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5		\
		(_MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1		\
		(_MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1		\
		(_MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI		\
		(_MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1		\
		(_MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DEBUG_1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL		\
		(_MX6Q_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT1__GPIO_4_22		\
		(_MX6Q_PAD_DISP0_DAT1__GPIO_4_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6		\
		(_MX6Q_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12		\
		(_MX6Q_PAD_DISP0_DAT1__PL301_MX6QPER1_HADDR_12 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2		\
		(_MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2		\
		(_MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO		\
		(_MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2		\
		(_MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE		\
		(_MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT2__GPIO_4_23		\
		(_MX6Q_PAD_DISP0_DAT2__GPIO_4_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7		\
		(_MX6Q_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13		\
		(_MX6Q_PAD_DISP0_DAT2__PL301_MX6QPER1_HADDR_13 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3		\
		(_MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3		\
		(_MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0		\
		(_MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3		\
		(_MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DEBUG_3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR		\
		(_MX6Q_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT3__GPIO_4_24		\
		(_MX6Q_PAD_DISP0_DAT3__GPIO_4_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8		\
		(_MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14		\
		(_MX6Q_PAD_DISP0_DAT3__PL301_MX6QPER1_HADDR_14 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4		\
		(_MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4		\
		(_MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1		\
		(_MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4		\
		(_MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DEBUG_4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB		\
		(_MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT4__GPIO_4_25		\
		(_MX6Q_PAD_DISP0_DAT4__GPIO_4_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9		\
		(_MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15		\
		(_MX6Q_PAD_DISP0_DAT4__PL301_MX6QPER1_HADDR_15 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5		\
		(_MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5		\
		(_MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2		\
		(_MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS		\
		(_MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS		\
		(_MX6Q_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT5__GPIO_4_26		\
		(_MX6Q_PAD_DISP0_DAT5__GPIO_4_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10		\
		(_MX6Q_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16		\
		(_MX6Q_PAD_DISP0_DAT5__PL301_MX6QPER1_HADDR_16 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6		\
		(_MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6		\
		(_MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3		\
		(_MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC		\
		(_MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE		\
		(_MX6Q_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT6__GPIO_4_27		\
		(_MX6Q_PAD_DISP0_DAT6__GPIO_4_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11		\
		(_MX6Q_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17		\
		(_MX6Q_PAD_DISP0_DAT6__PL301_MX6QPER1_HADDR_17 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7		\
		(_MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7		\
		(_MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY		\
		(_MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5		\
		(_MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DEBUG_5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0		\
		(_MX6Q_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT7__GPIO_4_28		\
		(_MX6Q_PAD_DISP0_DAT7__GPIO_4_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12		\
		(_MX6Q_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18		\
		(_MX6Q_PAD_DISP0_DAT7__PL301_MX6QPER1_HADDR_18 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8		\
		(_MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8		\
		(_MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT8__PWM1_PWMO		\
		(_MX6Q_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B		\
		(_MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1		\
		(_MX6Q_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT8__GPIO_4_29		\
		(_MX6Q_PAD_DISP0_DAT8__GPIO_4_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13		\
		(_MX6Q_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19		\
		(_MX6Q_PAD_DISP0_DAT8__PL301_MX6QPER1_HADDR_19 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9		\
		(_MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9		\
		(_MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT9__PWM2_PWMO		\
		(_MX6Q_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B		\
		(_MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2		\
		(_MX6Q_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT9__GPIO_4_30		\
		(_MX6Q_PAD_DISP0_DAT9__GPIO_4_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14		\
		(_MX6Q_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20		\
		(_MX6Q_PAD_DISP0_DAT9__PL301_MX6QPER1_HADDR_20 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10		\
		(_MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10		\
		(_MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6		\
		(_MX6Q_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3		\
		(_MX6Q_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT10__GPIO_4_31		\
		(_MX6Q_PAD_DISP0_DAT10__GPIO_4_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15		\
		(_MX6Q_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21		\
		(_MX6Q_PAD_DISP0_DAT10__PL301_MX6QPER1_HADDR_21 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11		\
		(_MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11		\
		(_MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7		\
		(_MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4		\
		(_MX6Q_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT11__GPIO_5_5		\
		(_MX6Q_PAD_DISP0_DAT11__GPIO_5_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16		\
		(_MX6Q_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22		\
		(_MX6Q_PAD_DISP0_DAT11__PL301_MX6QPER1_HADDR_22 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12		\
		(_MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12		\
		(_MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED		\
		(_MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5		\
		(_MX6Q_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT12__GPIO_5_6		\
		(_MX6Q_PAD_DISP0_DAT12__GPIO_5_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17		\
		(_MX6Q_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23		\
		(_MX6Q_PAD_DISP0_DAT12__PL301_MX6QPER1_HADDR_23 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13		\
		(_MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13		\
		(_MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS		\
		(_MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0		\
		(_MX6Q_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT13__GPIO_5_7		\
		(_MX6Q_PAD_DISP0_DAT13__GPIO_5_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18		\
		(_MX6Q_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24		\
		(_MX6Q_PAD_DISP0_DAT13__PL301_MX6QPER1_HADDR_24 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14		\
		(_MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14		\
		(_MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC		\
		(_MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1		\
		(_MX6Q_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT14__GPIO_5_8		\
		(_MX6Q_PAD_DISP0_DAT14__GPIO_5_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19		\
		(_MX6Q_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15		\
		(_MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15		\
		(_MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1		\
		(_MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1		\
		(_MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2		\
		(_MX6Q_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT15__GPIO_5_9		\
		(_MX6Q_PAD_DISP0_DAT15__GPIO_5_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20		\
		(_MX6Q_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25		\
		(_MX6Q_PAD_DISP0_DAT15__PL301_MX6QPER1_HADDR_25 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16		\
		(_MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16		\
		(_MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI		\
		(_MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC		\
		(_MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0		\
		(_MX6Q_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT16__GPIO_5_10		\
		(_MX6Q_PAD_DISP0_DAT16__GPIO_5_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21		\
		(_MX6Q_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26		\
		(_MX6Q_PAD_DISP0_DAT16__PL301_MX6QPER1_HADDR_26 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17		\
		(_MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17		\
		(_MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO		\
		(_MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD		\
		(_MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1		\
		(_MX6Q_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT17__GPIO_5_11		\
		(_MX6Q_PAD_DISP0_DAT17__GPIO_5_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22		\
		(_MX6Q_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27		\
		(_MX6Q_PAD_DISP0_DAT17__PL301_MX6QPER1_HADDR_27 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18		\
		(_MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18		\
		(_MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0		\
		(_MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS		\
		(_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS		\
		(_MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT18__GPIO_5_12		\
		(_MX6Q_PAD_DISP0_DAT18__GPIO_5_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23		\
		(_MX6Q_PAD_DISP0_DAT18__MMDC_MMDC_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2		\
		(_MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19		\
		(_MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19		\
		(_MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK		\
		(_MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD		\
		(_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC		\
		(_MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT19__GPIO_5_13		\
		(_MX6Q_PAD_DISP0_DAT19__GPIO_5_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24		\
		(_MX6Q_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3		\
		(_MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20		\
		(_MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20		\
		(_MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK		\
		(_MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC		\
		(_MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7		\
		(_MX6Q_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT20__GPIO_5_14		\
		(_MX6Q_PAD_DISP0_DAT20__GPIO_5_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25		\
		(_MX6Q_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28		\
		(_MX6Q_PAD_DISP0_DAT20__PL301_MX6QPER1_HADDR_28 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21		\
		(_MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21		\
		(_MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI		\
		(_MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD		\
		(_MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0		\
		(_MX6Q_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT21__GPIO_5_15		\
		(_MX6Q_PAD_DISP0_DAT21__GPIO_5_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26		\
		(_MX6Q_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29		\
		(_MX6Q_PAD_DISP0_DAT21__PL301_MX6QPER1_HADDR_29 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22		\
		(_MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22		\
		(_MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO		\
		(_MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS		\
		(_MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1		\
		(_MX6Q_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT22__GPIO_5_16		\
		(_MX6Q_PAD_DISP0_DAT22__GPIO_5_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27		\
		(_MX6Q_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30		\
		(_MX6Q_PAD_DISP0_DAT22__PL301_MX6QPER1_HADDR_30 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23		\
		(_MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23		\
		(_MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 | MUX_PAD_CTRL(MX6Q_DISP_PAD_CLT))
#define  MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0		\
		(_MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD		\
		(_MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2		\
		(_MX6Q_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT23__GPIO_5_17		\
		(_MX6Q_PAD_DISP0_DAT23__GPIO_5_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28		\
		(_MX6Q_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31		\
		(_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED		\
		(_MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_MDIO__ENET_MDIO		\
		(_MX6Q_PAD_ENET_MDIO__ENET_MDIO | \
		 MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_ENET_MDIO__ESAI1_SCKR		\
		(_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
#define  MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3		\
		(_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT		\
		(_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_MDIO__GPIO_1_22		\
		(_MX6Q_PAD_ENET_MDIO__GPIO_1_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK		\
		(_MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED		\
		(_MX6Q_PAD_ENET_REF_CLK__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK		\
		(_MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR		\
		(_MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
#define  MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4		\
		(_MX6Q_PAD_ENET_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_REF_CLK__GPIO_1_23		\
		(_MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK		\
		(_MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH		\
		(_MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_ENET_RX_ER__ENET_RX_ER		\
		(_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR		\
		(_MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
#define  MX6Q_PAD_ENET_RX_ER__SPDIF_IN1		\
		(_MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT		\
		(_MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_RX_ER__GPIO_1_24		\
		(_MX6Q_PAD_ENET_RX_ER__GPIO_1_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_RX_ER__PHY_TDI		\
		(_MX6Q_PAD_ENET_RX_ER__PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD		\
		(_MX6Q_PAD_ENET_RX_ER__ANATOP_USBPHY1_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED		\
		(_MX6Q_PAD_ENET_CRS_DV__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN		\
		(_MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT		\
		(_MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
#define  MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK		\
		(_MX6Q_PAD_ENET_CRS_DV__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_CRS_DV__GPIO_1_25		\
		(_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_CRS_DV__PHY_TDO		\
		(_MX6Q_PAD_ENET_CRS_DV__PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD		\
		(_MX6Q_PAD_ENET_CRS_DV__ANATOP_USBPHY1_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_ENET_RXD1__MLB_MLBSIG		\
		(_MX6Q_PAD_ENET_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_RXD1__ENET_RDATA_1		\
		(_MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_RXD1__ESAI1_FST		\
		(_MX6Q_PAD_ENET_RXD1__ESAI1_FST | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
#define  MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT		\
		(_MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_RXD1__GPIO_1_26		\
		(_MX6Q_PAD_ENET_RXD1__GPIO_1_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_RXD1__PHY_TCK		\
		(_MX6Q_PAD_ENET_RXD1__PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET		\
		(_MX6Q_PAD_ENET_RXD1__ANATOP_USBPHY1_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT		\
		(_MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_RXD0__ENET_RDATA_0		\
		(_MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_RXD0__ESAI1_HCKT		\
		(_MX6Q_PAD_ENET_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
#define  MX6Q_PAD_ENET_RXD0__SPDIF_OUT1		\
		(_MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_RXD0__GPIO_1_27		\
		(_MX6Q_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_RXD0__PHY_TMS		\
		(_MX6Q_PAD_ENET_RXD0__PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV		\
		(_MX6Q_PAD_ENET_RXD0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED		\
		(_MX6Q_PAD_ENET_TX_EN__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_TX_EN__ENET_TX_EN		\
		(_MX6Q_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2		\
		(_MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
#define  MX6Q_PAD_ENET_TX_EN__GPIO_1_28		\
		(_MX6Q_PAD_ENET_TX_EN__GPIO_1_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI		\
		(_MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH		\
		(_MX6Q_PAD_ENET_TX_EN__ANATOP_USBPHY2_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_ENET_TXD1__MLB_MLBCLK		\
		(_MX6Q_PAD_ENET_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_TXD1__ENET_TDATA_1		\
		(_MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3		\
		(_MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
#define  MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN		\
		(_MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_TXD1__GPIO_1_29		\
		(_MX6Q_PAD_ENET_TXD1__GPIO_1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO		\
		(_MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD		\
		(_MX6Q_PAD_ENET_TXD1__ANATOP_USBPHY2_TSTO_RX_HS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED		\
		(_MX6Q_PAD_ENET_TXD0__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_TXD0__ENET_TDATA_0		\
		(_MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1		\
		(_MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
#define  MX6Q_PAD_ENET_TXD0__GPIO_1_30		\
		(_MX6Q_PAD_ENET_TXD0__GPIO_1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK		\
		(_MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD		\
		(_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_ENET_MDC__MLB_MLBDAT		\
		(_MX6Q_PAD_ENET_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_MDC__ENET_MDC		\
		(_MX6Q_PAD_ENET_MDC__ENET_MDC | \
		 MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0		\
		(_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
#define  MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN		\
		(_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_MDC__GPIO_1_31		\
		(_MX6Q_PAD_ENET_MDC__GPIO_1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_MDC__SATA_PHY_TMS		\
		(_MX6Q_PAD_ENET_MDC__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET		\
		(_MX6Q_PAD_ENET_MDC__ANATOP_USBPHY2_TSTO_RX_DISCON_DET | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40		\
		(_MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41		\
		(_MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42		\
		(_MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43		\
		(_MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44		\
		(_MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45		\
		(_MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46		\
		(_MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47		\
		(_MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5		\
		(_MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5		\
		(_MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32		\
		(_MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33		\
		(_MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34		\
		(_MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35		\
		(_MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36		\
		(_MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37		\
		(_MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38		\
		(_MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39		\
		(_MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4		\
		(_MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4		\
		(_MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24		\
		(_MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25		\
		(_MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26		\
		(_MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27		\
		(_MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28		\
		(_MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29		\
		(_MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3		\
		(_MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30		\
		(_MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31		\
		(_MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3		\
		(_MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16		\
		(_MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17		\
		(_MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18		\
		(_MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19		\
		(_MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20		\
		(_MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21		\
		(_MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22		\
		(_MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2		\
		(_MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23		\
		(_MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2		\
		(_MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0		\
		(_MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1		\
		(_MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2		\
		(_MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3		\
		(_MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4		\
		(_MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5		\
		(_MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6		\
		(_MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7		\
		(_MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8		\
		(_MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9		\
		(_MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10		\
		(_MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11		\
		(_MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12		\
		(_MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13		\
		(_MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14		\
		(_MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15		\
		(_MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS		\
		(_MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0		\
		(_MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1		\
		(_MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS		\
		(_MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET		\
		(_MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0		\
		(_MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1		\
		(_MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0		\
		(_MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2		\
		(_MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0		\
		(_MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1		\
		(_MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1		\
		(_MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0		\
		(_MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1		\
		(_MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE		\
		(_MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0		\
		(_MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1		\
		(_MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2		\
		(_MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3		\
		(_MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4		\
		(_MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5		\
		(_MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0		\
		(_MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6		\
		(_MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7		\
		(_MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0		\
		(_MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8		\
		(_MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9		\
		(_MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10		\
		(_MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11		\
		(_MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12		\
		(_MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13		\
		(_MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14		\
		(_MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1		\
		(_MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15		\
		(_MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1		\
		(_MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48		\
		(_MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49		\
		(_MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50		\
		(_MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51		\
		(_MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52		\
		(_MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53		\
		(_MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54		\
		(_MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55		\
		(_MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6		\
		(_MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6		\
		(_MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56		\
		(_MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7		\
		(_MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57		\
		(_MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58		\
		(_MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59		\
		(_MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60		\
		(_MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7		\
		(_MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61		\
		(_MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62		\
		(_MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63		\
		(_MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_KEY_COL0__ECSPI1_SCLK		\
		(_MX6Q_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL0__ENET_RDATA_3		\
		(_MX6Q_PAD_KEY_COL0__ENET_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC		\
		(_MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL0__KPP_COL_0		\
		(_MX6Q_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL0__UART4_TXD		\
		(_MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL0__UART4_RXD		\
		(_MX6Q_PAD_KEY_COL0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL0__GPIO_4_6		\
		(_MX6Q_PAD_KEY_COL0__GPIO_4_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT		\
		(_MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST		\
		(_MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI		\
		(_MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW0__ENET_TDATA_3		\
		(_MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD		\
		(_MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW0__KPP_ROW_0		\
		(_MX6Q_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW0__UART4_TXD		\
		(_MX6Q_PAD_KEY_ROW0__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW0__UART4_RXD		\
		(_MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW0__GPIO_4_7		\
		(_MX6Q_PAD_KEY_ROW0__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT		\
		(_MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0		\
		(_MX6Q_PAD_KEY_ROW0__PL301_MX6QPER1_HADDR_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_KEY_COL1__ECSPI1_MISO		\
		(_MX6Q_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL1__ENET_MDIO		\
		(_MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS		\
		(_MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL1__KPP_COL_1		\
		(_MX6Q_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL1__UART5_TXD		\
		(_MX6Q_PAD_KEY_COL1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL1__UART5_RXD		\
		(_MX6Q_PAD_KEY_COL1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL1__GPIO_4_8		\
		(_MX6Q_PAD_KEY_COL1__GPIO_4_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL1__USDHC1_VSELECT		\
		(_MX6Q_PAD_KEY_COL1__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1		\
		(_MX6Q_PAD_KEY_COL1__PL301_MX6QPER1_HADDR_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_KEY_ROW1__ECSPI1_SS0		\
		(_MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW1__ENET_COL		\
		(_MX6Q_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD		\
		(_MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW1__KPP_ROW_1		\
		(_MX6Q_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW1__UART5_TXD		\
		(_MX6Q_PAD_KEY_ROW1__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW1__UART5_RXD		\
		(_MX6Q_PAD_KEY_ROW1__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW1__GPIO_4_9		\
		(_MX6Q_PAD_KEY_ROW1__GPIO_4_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT		\
		(_MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2		\
		(_MX6Q_PAD_KEY_ROW1__PL301_MX6QPER1_HADDR_2 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_KEY_COL2__ECSPI1_SS1		\
		(_MX6Q_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL2__ENET_RDATA_2		\
		(_MX6Q_PAD_KEY_COL2__ENET_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL2__CAN1_TXCAN		\
		(_MX6Q_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL2__KPP_COL_2		\
		(_MX6Q_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL2__ENET_MDC		\
		(_MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL2__GPIO_4_10		\
		(_MX6Q_PAD_KEY_COL2__GPIO_4_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP		\
		(_MX6Q_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3		\
		(_MX6Q_PAD_KEY_COL2__PL301_MX6QPER1_HADDR_3 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_KEY_ROW2__ECSPI1_SS2		\
		(_MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW2__ENET_TDATA_2		\
		(_MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW2__CAN1_RXCAN		\
		(_MX6Q_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW2__KPP_ROW_2		\
		(_MX6Q_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT		\
		(_MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW2__GPIO_4_11		\
		(_MX6Q_PAD_KEY_ROW2__GPIO_4_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE		\
		(_MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4		\
		(_MX6Q_PAD_KEY_ROW2__PL301_MX6QPER1_HADDR_4 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_KEY_COL3__ECSPI1_SS3		\
		(_MX6Q_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL3__ENET_CRS		\
		(_MX6Q_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL		\
		(_MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL3__KPP_COL_3		\
		(_MX6Q_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL3__I2C2_SCL		\
		(_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL3__GPIO_4_12		\
		(_MX6Q_PAD_KEY_COL3__GPIO_4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL3__SPDIF_IN1		\
		(_MX6Q_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5		\
		(_MX6Q_PAD_KEY_COL3__PL301_MX6QPER1_HADDR_5 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT		\
		(_MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK		\
		(_MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA		\
		(_MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW3__KPP_ROW_3		\
		(_MX6Q_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW3__I2C2_SDA		\
		(_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW3__GPIO_4_13		\
		(_MX6Q_PAD_KEY_ROW3__GPIO_4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT		\
		(_MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6		\
		(_MX6Q_PAD_KEY_ROW3__PL301_MX6QPER1_HADDR_6 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_KEY_COL4__CAN2_TXCAN		\
		(_MX6Q_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL4__IPU1_SISG_4		\
		(_MX6Q_PAD_KEY_COL4__IPU1_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC		\
		(_MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL4__KPP_COL_4		\
		(_MX6Q_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL4__UART5_CTS		\
		(_MX6Q_PAD_KEY_COL4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL4__UART5_RTS		\
		(_MX6Q_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL4__GPIO_4_14		\
		(_MX6Q_PAD_KEY_COL4__GPIO_4_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49		\
		(_MX6Q_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7		\
		(_MX6Q_PAD_KEY_COL4__PL301_MX6QPER1_HADDR_7 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_KEY_ROW4__CAN2_RXCAN		\
		(_MX6Q_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW4__IPU1_SISG_5		\
		(_MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR		\
		(_MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW4__KPP_ROW_4		\
		(_MX6Q_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW4__UART5_CTS		\
		(_MX6Q_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW4__GPIO_4_15		\
		(_MX6Q_PAD_KEY_ROW4__GPIO_4_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50		\
		(_MX6Q_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8		\
		(_MX6Q_PAD_KEY_ROW4__PL301_MX6QPER1_HADDR_8 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_GPIO_0__CCM_CLKO		\
		(_MX6Q_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(MX6Q_CCM_CLK0_PAD_CTRL))
#define  MX6Q_PAD_GPIO_0__KPP_COL_5		\
		(_MX6Q_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK		\
		(_MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_0__EPIT1_EPITO		\
		(_MX6Q_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_0__GPIO_1_0		\
		(_MX6Q_PAD_GPIO_0__GPIO_1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR		\
		(_MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5		\
		(_MX6Q_PAD_GPIO_0__SNVS_HP_WRAPPER_SNVS_VIO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_GPIO_1__ESAI1_SCKR		\
		(_MX6Q_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_1__WDOG2_WDOG_B		\
		(_MX6Q_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_1__KPP_ROW_5		\
		(_MX6Q_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_1__PWM2_PWMO		\
		(_MX6Q_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_1__GPIO_1_1		\
		(_MX6Q_PAD_GPIO_1__GPIO_1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_1__USDHC1_CD		\
		(_MX6Q_PAD_GPIO_1__USDHC1_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_GPIO_1__SRC_TESTER_ACK		\
		(_MX6Q_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_GPIO_9__ESAI1_FSR		\
		(_MX6Q_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_9__WDOG1_WDOG_B		\
		(_MX6Q_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_9__KPP_COL_6		\
		(_MX6Q_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_9__CCM_REF_EN_B		\
		(_MX6Q_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_9__PWM1_PWMO		\
		(_MX6Q_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
#define  MX6Q_PAD_GPIO_9__GPIO_1_9		\
		(_MX6Q_PAD_GPIO_9__GPIO_1_9 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
#define  MX6Q_PAD_GPIO_9__USDHC1_WP		\
		(_MX6Q_PAD_GPIO_9__USDHC1_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_GPIO_9__SRC_EARLY_RST		\
		(_MX6Q_PAD_GPIO_9__SRC_EARLY_RST | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_GPIO_3__ESAI1_HCKR		\
		(_MX6Q_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0		\
		(_MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_3__I2C3_SCL		\
		(_MX6Q_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT		\
		(_MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_3__CCM_CLKO2		\
		(_MX6Q_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_3__GPIO_1_3		\
		(_MX6Q_PAD_GPIO_3__GPIO_1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC		\
		(_MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_3__MLB_MLBCLK		\
		(_MX6Q_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_GPIO_6__ESAI1_SCKT		\
		(_MX6Q_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1		\
		(_MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_6__I2C3_SDA		\
		(_MX6Q_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0		\
		(_MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB		\
		(_MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_6__GPIO_1_6		\
		(_MX6Q_PAD_GPIO_6__GPIO_1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_6__USDHC2_LCTL		\
		(_MX6Q_PAD_GPIO_6__USDHC2_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_GPIO_6__MLB_MLBSIG		\
		(_MX6Q_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_GPIO_2__ESAI1_FST		\
		(_MX6Q_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2		\
		(_MX6Q_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_2__KPP_ROW_6		\
		(_MX6Q_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1		\
		(_MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0		\
		(_MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_2__GPIO_1_2		\
		(_MX6Q_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_2__USDHC2_WP		\
		(_MX6Q_PAD_GPIO_2__USDHC2_WP | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_GPIO_2__MLB_MLBDAT		\
		(_MX6Q_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_GPIO_4__ESAI1_HCKT		\
		(_MX6Q_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3		\
		(_MX6Q_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_4__KPP_COL_7		\
		(_MX6Q_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2		\
		(_MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1		\
		(_MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_4__GPIO_1_4		\
		(_MX6Q_PAD_GPIO_4__GPIO_1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_4__USDHC2_CD		\
		(_MX6Q_PAD_GPIO_4__USDHC2_CD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED		\
		(_MX6Q_PAD_GPIO_4__OCOTP_CTRL_WRAPPER_FUSE_LATCHED | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3		\
		(_MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4		\
		(_MX6Q_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_5__KPP_ROW_7		\
		(_MX6Q_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_5__CCM_CLKO		\
		(_MX6Q_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2		\
		(_MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_5__GPIO_1_5		\
		(_MX6Q_PAD_GPIO_5__GPIO_1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_5__I2C3_SCL		\
		(_MX6Q_PAD_GPIO_5__I2C3_SCL |  MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
#define  MX6Q_PAD_GPIO_5__CHEETAH_EVENTI		\
		(_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1		\
		(_MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_7__ECSPI5_RDY		\
		(_MX6Q_PAD_GPIO_7__ECSPI5_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_7__EPIT1_EPITO		\
		(_MX6Q_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_7__CAN1_TXCAN		\
		(_MX6Q_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_7__UART2_TXD		\
		(_MX6Q_PAD_GPIO_7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_GPIO_7__UART2_RXD		\
		(_MX6Q_PAD_GPIO_7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_GPIO_7__GPIO_1_7		\
		(_MX6Q_PAD_GPIO_7__GPIO_1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_7__SPDIF_PLOCK		\
		(_MX6Q_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE		\
		(_MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HOST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0		\
		(_MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT		\
		(_MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_8__EPIT2_EPITO		\
		(_MX6Q_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_8__CAN1_RXCAN		\
		(_MX6Q_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_8__UART2_TXD		\
		(_MX6Q_PAD_GPIO_8__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_GPIO_8__UART2_RXD		\
		(_MX6Q_PAD_GPIO_8__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_GPIO_8__GPIO_1_8		\
		(_MX6Q_PAD_GPIO_8__GPIO_1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_8__SPDIF_SRCLK		\
		(_MX6Q_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP		\
		(_MX6Q_PAD_GPIO_8__USBOH3_OTGUSB_PWRCTL_WAKEUP | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2		\
		(_MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN		\
		(_MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT		\
		(_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_16__USDHC1_LCTL		\
		(_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_GPIO_16__SPDIF_IN1		\
		(_MX6Q_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_16__GPIO_7_11		\
		(_MX6Q_PAD_GPIO_16__GPIO_7_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_16__I2C3_SDA		\
		(_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
#define  MX6Q_PAD_GPIO_16__SJC_DE_B		\
		(_MX6Q_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_GPIO_17__ESAI1_TX0		\
		(_MX6Q_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN		\
		(_MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_17__CCM_PMIC_RDY		\
		(_MX6Q_PAD_GPIO_17__CCM_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0		\
		(_MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_17__SPDIF_OUT1		\
		(_MX6Q_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(MX6Q_SPDIF_OUT_PAD_CTRL))
#define  MX6Q_PAD_GPIO_17__GPIO_7_12		\
		(_MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_17__SJC_JTAG_ACT		\
		(_MX6Q_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_GPIO_18__ESAI1_TX1		\
		(_MX6Q_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_18__ENET_RX_CLK		\
		(_MX6Q_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_18__USDHC3_VSELECT		\
		(_MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1		\
		(_MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK		\
		(_MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_18__GPIO_7_13		\
		(_MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL		\
		(_MX6Q_PAD_GPIO_18__SNVS_HP_WRAPPER_SNVS_VIO_5_CTL | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST		\
		(_MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_GPIO_19__KPP_COL_5		\
		(_MX6Q_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT		\
		(_MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_19__SPDIF_OUT1		\
		(_MX6Q_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_19__CCM_CLKO		\
		(_MX6Q_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_19__ECSPI1_RDY		\
		(_MX6Q_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_19__GPIO_4_5		\
		(_MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
#define  MX6Q_PAD_GPIO_19__ENET_TX_ER		\
		(_MX6Q_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_GPIO_19__SRC_INT_BOOT		\
		(_MX6Q_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK		\
		(_MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12		\
		(_MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0		\
		(_MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18		\
		(_MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29		\
		(_MX6Q_PAD_CSI0_PIXCLK__MMDC_MMDC_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO		\
		(_MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC		\
		(_MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13		\
		(_MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_MCLK__CCM_CLKO		\
		(_MX6Q_PAD_CSI0_MCLK__CCM_CLKO | MUX_PAD_CTRL(MX6Q_CCM_CLK0_PAD_CTRL))
#define  MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1		\
		(_MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_MCLK__GPIO_5_19		\
		(_MX6Q_PAD_CSI0_MCLK__GPIO_5_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30		\
		(_MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL		\
		(_MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN		\
		(_MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0		\
		(_MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14		\
		(_MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_DIAG_STATUS_BUS_MUX_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2		\
		(_MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20		\
		(_MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31		\
		(_MX6Q_PAD_CSI0_DATA_EN__MMDC_MMDC_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK		\
		(_MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC		\
		(_MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1		\
		(_MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15		\
		(_MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_DIAG_STATUS_BUS_MUX_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3		\
		(_MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_VSYNC__GPIO_5_21		\
		(_MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32		\
		(_MX6Q_PAD_CSI0_VSYNC__MMDC_MMDC_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0		\
		(_MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4		\
		(_MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2		\
		(_MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK		\
		(_MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT4__KPP_COL_5		\
		(_MX6Q_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC		\
		(_MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT4__GPIO_5_22		\
		(_MX6Q_PAD_CSI0_DAT4__GPIO_5_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43		\
		(_MX6Q_PAD_CSI0_DAT4__MMDC_MMDC_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1		\
		(_MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5		\
		(_MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3		\
		(_MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI		\
		(_MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT5__KPP_ROW_5		\
		(_MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD		\
		(_MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT5__GPIO_5_23		\
		(_MX6Q_PAD_CSI0_DAT5__GPIO_5_23 | MUX_PAD_CTRL(MX6Q_HIGH_DRV))
#define  MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44		\
		(_MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2		\
		(_MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6		\
		(_MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4		\
		(_MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO		\
		(_MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT6__KPP_COL_6		\
		(_MX6Q_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS		\
		(_MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT6__GPIO_5_24		\
		(_MX6Q_PAD_CSI0_DAT6__GPIO_5_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45		\
		(_MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3		\
		(_MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7		\
		(_MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5		\
		(_MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0		\
		(_MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT7__KPP_ROW_6		\
		(_MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD		\
		(_MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT7__GPIO_5_25		\
		(_MX6Q_PAD_CSI0_DAT7__GPIO_5_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46		\
		(_MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4		\
		(_MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8		\
		(_MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6		\
		(_MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK		\
		(_MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT8__KPP_COL_7		\
		(_MX6Q_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT8__I2C1_SDA		\
		(_MX6Q_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT8__GPIO_5_26		\
		(_MX6Q_PAD_CSI0_DAT8__GPIO_5_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47		\
		(_MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5		\
		(_MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9		\
		(_MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7		\
		(_MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI		\
		(_MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT9__KPP_ROW_7		\
		(_MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT9__I2C1_SCL		\
		(_MX6Q_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT9__GPIO_5_27		\
		(_MX6Q_PAD_CSI0_DAT9__GPIO_5_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48		\
		(_MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6		\
		(_MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10		\
		(_MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC		\
		(_MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO		\
		(_MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT10__UART1_TXD		\
		(_MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT10__UART1_RXD		\
		(_MX6Q_PAD_CSI0_DAT10__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4		\
		(_MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT10__GPIO_5_28		\
		(_MX6Q_PAD_CSI0_DAT10__GPIO_5_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33		\
		(_MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7		\
		(_MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11		\
		(_MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS		\
		(_MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0		\
		(_MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT11__UART1_TXD		\
		(_MX6Q_PAD_CSI0_DAT11__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT11__UART1_RXD		\
		(_MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5		\
		(_MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT11__GPIO_5_29		\
		(_MX6Q_PAD_CSI0_DAT11__GPIO_5_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34		\
		(_MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8		\
		(_MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12		\
		(_MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8		\
		(_MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16		\
		(_MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_DIAG_STATUS_BUS_MUX_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT12__UART4_TXD		\
		(_MX6Q_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT12__UART4_RXD		\
		(_MX6Q_PAD_CSI0_DAT12__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6		\
		(_MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT12__GPIO_5_30		\
		(_MX6Q_PAD_CSI0_DAT12__GPIO_5_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35		\
		(_MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9		\
		(_MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13		\
		(_MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9		\
		(_MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17		\
		(_MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_DIAG_STATUS_BUS_MUX_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT13__UART4_TXD		\
		(_MX6Q_PAD_CSI0_DAT13__UART4_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT13__UART4_RXD		\
		(_MX6Q_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7		\
		(_MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT13__GPIO_5_31		\
		(_MX6Q_PAD_CSI0_DAT13__GPIO_5_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36		\
		(_MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10		\
		(_MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14		\
		(_MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10		\
		(_MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18		\
		(_MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_DIAG_STATUS_BUS_MUX_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT14__UART5_TXD		\
		(_MX6Q_PAD_CSI0_DAT14__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT14__UART5_RXD		\
		(_MX6Q_PAD_CSI0_DAT14__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8		\
		(_MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT14__GPIO_6_0		\
		(_MX6Q_PAD_CSI0_DAT14__GPIO_6_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37		\
		(_MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11		\
		(_MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15		\
		(_MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11		\
		(_MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19		\
		(_MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_DIAG_STATUS_BUS_MUX_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT15__UART5_TXD		\
		(_MX6Q_PAD_CSI0_DAT15__UART5_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT15__UART5_RXD		\
		(_MX6Q_PAD_CSI0_DAT15__UART5_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9		\
		(_MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT15__GPIO_6_1		\
		(_MX6Q_PAD_CSI0_DAT15__GPIO_6_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38		\
		(_MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12		\
		(_MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16		\
		(_MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12		\
		(_MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20		\
		(_MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_DIAG_STATUS_BUS_MUX_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT16__UART4_CTS		\
		(_MX6Q_PAD_CSI0_DAT16__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT16__UART4_RTS		\
		(_MX6Q_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10		\
		(_MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT16__GPIO_6_2		\
		(_MX6Q_PAD_CSI0_DAT16__GPIO_6_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39		\
		(_MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13		\
		(_MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17		\
		(_MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13		\
		(_MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21		\
		(_MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_DIAG_STATUS_BUS_MUX_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT17__UART4_CTS		\
		(_MX6Q_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11		\
		(_MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT17__GPIO_6_3		\
		(_MX6Q_PAD_CSI0_DAT17__GPIO_6_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40		\
		(_MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14		\
		(_MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18		\
		(_MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14		\
		(_MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22		\
		(_MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_DIAG_STATUS_BUS_MUX_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT18__UART5_CTS		\
		(_MX6Q_PAD_CSI0_DAT18__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT18__UART5_RTS		\
		(_MX6Q_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12		\
		(_MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT18__GPIO_6_4		\
		(_MX6Q_PAD_CSI0_DAT18__GPIO_6_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41		\
		(_MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15		\
		(_MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19		\
		(_MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15		\
		(_MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23		\
		(_MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_DIAG_STATUS_BUS_MUX_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT19__UART5_CTS		\
		(_MX6Q_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13		\
		(_MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT19__GPIO_6_5		\
		(_MX6Q_PAD_CSI0_DAT19__GPIO_6_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42		\
		(_MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9		\
		(_MX6Q_PAD_CSI0_DAT19__ANATOP_ANATOP_TESTO_9 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_JTAG_TMS__SJC_TMS		\
		(_MX6Q_PAD_JTAG_TMS__SJC_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_JTAG_MOD__SJC_MOD		\
		(_MX6Q_PAD_JTAG_MOD__SJC_MOD | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB		\
		(_MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_JTAG_TDI__SJC_TDI		\
		(_MX6Q_PAD_JTAG_TDI__SJC_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_JTAG_TCK__SJC_TCK		\
		(_MX6Q_PAD_JTAG_TCK__SJC_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_JTAG_TDO__SJC_TDO		\
		(_MX6Q_PAD_JTAG_TDO__SJC_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3		\
		(_MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2		\
		(_MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK		\
		(_MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1		\
		(_MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0		\
		(_MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3		\
		(_MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK		\
		(_MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2		\
		(_MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1		\
		(_MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0		\
		(_MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1		\
		(_MX6Q_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM		\
		(_MX6Q_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ		\
		(_MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_POR_B__SRC_POR_B		\
		(_MX6Q_PAD_POR_B__SRC_POR_B | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1		\
		(_MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_RESET_IN_B__SRC_RESET_B		\
		(_MX6Q_PAD_RESET_IN_B__SRC_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0		\
		(_MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_TEST_MODE__TCU_TEST_MODE		\
		(_MX6Q_PAD_TEST_MODE__TCU_TEST_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ		\
		(_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_100MHZ		\
		(_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_200MHZ		\
		(_MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD3_DAT7__UART1_TXD		\
		(_MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT7__UART1_RXD		\
		(_MX6Q_PAD_SD3_DAT7__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24		\
		(_MX6Q_PAD_SD3_DAT7__PCIE_CTRL_DIAG_STATUS_BUS_MUX_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0		\
		(_MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0		\
		(_MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT7__GPIO_6_17		\
		(_MX6Q_PAD_SD3_DAT7__GPIO_6_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12		\
		(_MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_TEST_IN_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV		\
		(_MX6Q_PAD_SD3_DAT7__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ		\
		(_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_100MHZ		\
		(_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_200MHZ		\
		(_MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD3_DAT6__UART1_TXD		\
		(_MX6Q_PAD_SD3_DAT6__UART1_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT6__UART1_RXD		\
		(_MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25		\
		(_MX6Q_PAD_SD3_DAT6__PCIE_CTRL_DIAG_STATUS_BUS_MUX_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1		\
		(_MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1		\
		(_MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT6__GPIO_6_18		\
		(_MX6Q_PAD_SD3_DAT6__GPIO_6_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13		\
		(_MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_TEST_IN_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10		\
		(_MX6Q_PAD_SD3_DAT6__ANATOP_ANATOP_TESTO_10 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ		\
		(_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_100MHZ		\
		(_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_200MHZ		\
		(_MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD3_DAT5__UART2_TXD		\
		(_MX6Q_PAD_SD3_DAT5__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT5__UART2_RXD		\
		(_MX6Q_PAD_SD3_DAT5__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26		\
		(_MX6Q_PAD_SD3_DAT5__PCIE_CTRL_DIAG_STATUS_BUS_MUX_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2		\
		(_MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2		\
		(_MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT5__GPIO_7_0		\
		(_MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14		\
		(_MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_TEST_IN_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11		\
		(_MX6Q_PAD_SD3_DAT5__ANATOP_ANATOP_TESTO_11 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ		\
		(_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_100MHZ		\
		(_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_200MHZ		\
		(_MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD3_DAT4__UART2_TXD		\
		(_MX6Q_PAD_SD3_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT4__UART2_RXD		\
		(_MX6Q_PAD_SD3_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27		\
		(_MX6Q_PAD_SD3_DAT4__PCIE_CTRL_DIAG_STATUS_BUS_MUX_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3		\
		(_MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3		\
		(_MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT4__GPIO_7_1		\
		(_MX6Q_PAD_SD3_DAT4__GPIO_7_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15		\
		(_MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_TEST_IN_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12		\
		(_MX6Q_PAD_SD3_DAT4__ANATOP_ANATOP_TESTO_12 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ		\
		(_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD3_CMD__USDHC3_CMD_100MHZ		\
		(_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD3_CMD__USDHC3_CMD_200MHZ		\
		(_MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD3_CMD__UART2_CTS		\
		(_MX6Q_PAD_SD3_CMD__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_CMD__CAN1_TXCAN		\
		(_MX6Q_PAD_SD3_CMD__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4		\
		(_MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4		\
		(_MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_CMD__GPIO_7_2		\
		(_MX6Q_PAD_SD3_CMD__GPIO_7_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16		\
		(_MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_TEST_IN_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13		\
		(_MX6Q_PAD_SD3_CMD__ANATOP_ANATOP_TESTO_13 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ		\
		(_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD3_CLK__USDHC3_CLK_100MHZ		\
		(_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD3_CLK__USDHC3_CLK_200MHZ		\
		(_MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD3_CLK__UART2_CTS		\
		(_MX6Q_PAD_SD3_CLK__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_CLK__UART2_RTS		\
		(_MX6Q_PAD_SD3_CLK__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_CLK__CAN1_RXCAN		\
		(_MX6Q_PAD_SD3_CLK__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5		\
		(_MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5		\
		(_MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_CLK__GPIO_7_3		\
		(_MX6Q_PAD_SD3_CLK__GPIO_7_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17		\
		(_MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_TEST_IN_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14		\
		(_MX6Q_PAD_SD3_CLK__ANATOP_ANATOP_TESTO_14 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ		\
		(_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_100MHZ	\
		(_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_200MHZ	\
		(_MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD3_DAT0__UART1_CTS		\
		(_MX6Q_PAD_SD3_DAT0__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT0__CAN2_TXCAN		\
		(_MX6Q_PAD_SD3_DAT0__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6		\
		(_MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6		\
		(_MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT0__GPIO_7_4		\
		(_MX6Q_PAD_SD3_DAT0__GPIO_7_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18		\
		(_MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_TEST_IN_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15		\
		(_MX6Q_PAD_SD3_DAT0__ANATOP_ANATOP_TESTO_15 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ		\
		(_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_100MHZ		\
		(_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_200MHZ		\
		(_MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD3_DAT1__UART1_CTS		\
		(_MX6Q_PAD_SD3_DAT1__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT1__UART1_RTS		\
		(_MX6Q_PAD_SD3_DAT1__UART1_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT1__CAN2_RXCAN		\
		(_MX6Q_PAD_SD3_DAT1__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7		\
		(_MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7		\
		(_MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT1__GPIO_7_5		\
		(_MX6Q_PAD_SD3_DAT1__GPIO_7_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19		\
		(_MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_TEST_IN_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0		\
		(_MX6Q_PAD_SD3_DAT1__ANATOP_ANATOP_TESTI_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ		\
		(_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_100MHZ		\
		(_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_200MHZ		\
		(_MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28		\
		(_MX6Q_PAD_SD3_DAT2__PCIE_CTRL_DIAG_STATUS_BUS_MUX_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8		\
		(_MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8		\
		(_MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT2__GPIO_7_6		\
		(_MX6Q_PAD_SD3_DAT2__GPIO_7_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20		\
		(_MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_TEST_IN_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1		\
		(_MX6Q_PAD_SD3_DAT2__ANATOP_ANATOP_TESTI_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ		\
		(_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_100MHZ		\
		(_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_200MHZ		\
		(_MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD3_DAT3__UART3_CTS		\
		(_MX6Q_PAD_SD3_DAT3__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29		\
		(_MX6Q_PAD_SD3_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9		\
		(_MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9		\
		(_MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT3__GPIO_7_7		\
		(_MX6Q_PAD_SD3_DAT3__GPIO_7_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21		\
		(_MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_TEST_IN_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2		\
		(_MX6Q_PAD_SD3_DAT3__ANATOP_ANATOP_TESTI_2 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD3_RST__USDHC3_RST		\
		(_MX6Q_PAD_SD3_RST__USDHC3_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD3_RST__UART3_CTS		\
		(_MX6Q_PAD_SD3_RST__UART3_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_RST__UART3_RTS		\
		(_MX6Q_PAD_SD3_RST__UART3_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30		\
		(_MX6Q_PAD_SD3_RST__PCIE_CTRL_DIAG_STATUS_BUS_MUX_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10		\
		(_MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10		\
		(_MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_RST__GPIO_7_8		\
		(_MX6Q_PAD_SD3_RST__GPIO_7_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22		\
		(_MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_TEST_IN_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3		\
		(_MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_CLE__RAWNAND_CLE		\
		(_MX6Q_PAD_NANDF_CLE__RAWNAND_CLE | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_NANDF_CLE__IPU2_SISG_4		\
		(_MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31		\
		(_MX6Q_PAD_NANDF_CLE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11		\
		(_MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11		\
		(_MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CLE__GPIO_6_7		\
		(_MX6Q_PAD_NANDF_CLE__GPIO_6_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23		\
		(_MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_TEST_IN_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0		\
		(_MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_ALE__RAWNAND_ALE		\
		(_MX6Q_PAD_NANDF_ALE__RAWNAND_ALE | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_NANDF_ALE__USDHC4_RST		\
		(_MX6Q_PAD_NANDF_ALE__USDHC4_RST | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0		\
		(_MX6Q_PAD_NANDF_ALE__PCIE_CTRL_DIAG_STATUS_BUS_MUX_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12		\
		(_MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12		\
		(_MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_ALE__GPIO_6_8		\
		(_MX6Q_PAD_NANDF_ALE__GPIO_6_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24		\
		(_MX6Q_PAD_NANDF_ALE__MIPI_CORE_DPHY_TEST_IN_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1		\
		(_MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN		\
		(_MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5		\
		(_MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1		\
		(_MX6Q_PAD_NANDF_WP_B__PCIE_CTRL_DIAG_STATUS_BUS_MUX_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13		\
		(_MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13		\
		(_MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFD_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_WP_B__GPIO_6_9		\
		(_MX6Q_PAD_NANDF_WP_B__GPIO_6_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32		\
		(_MX6Q_PAD_NANDF_WP_B__MIPI_CORE_DPHY_TEST_OUT_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0		\
		(_MX6Q_PAD_NANDF_WP_B__PL301_MX6QPER1_HSIZE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_RB0__RAWNAND_READY0		\
		(_MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL0))
#define  MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1		\
		(_MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2		\
		(_MX6Q_PAD_NANDF_RB0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14		\
		(_MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14		\
		(_MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_RB0__GPIO_6_10		\
		(_MX6Q_PAD_NANDF_RB0__GPIO_6_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33		\
		(_MX6Q_PAD_NANDF_RB0__MIPI_CORE_DPHY_TEST_OUT_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1		\
		(_MX6Q_PAD_NANDF_RB0__PL301_MX6QPER1_HSIZE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N		\
		(_MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15		\
		(_MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15		\
		(_MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS0__GPIO_6_11		\
		(_MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2		\
		(_MX6Q_PAD_NANDF_CS0__PL301_MX6QPER1_HSIZE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N		\
		(_MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT		\
		(_MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT		\
		(_MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3		\
		(_MX6Q_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS1__GPIO_6_14		\
		(_MX6Q_PAD_NANDF_CS1__GPIO_6_14 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT		\
		(_MX6Q_PAD_NANDF_CS1__PL301_MX6QPER1_HREADYOUT | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N		\
		(_MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_NANDF_CS2__IPU1_SISG_0		\
		(_MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS2__ESAI1_TX0		\
		(_MX6Q_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE		\
		(_MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS2__CCM_CLKO2		\
		(_MX6Q_PAD_NANDF_CS2__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS2__GPIO_6_15		\
		(_MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS2__IPU2_SISG_0		\
		(_MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N		\
		(_MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_NANDF_CS3__IPU1_SISG_1		\
		(_MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS3__ESAI1_TX1		\
		(_MX6Q_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26		\
		(_MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4		\
		(_MX6Q_PAD_NANDF_CS3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS3__GPIO_6_16		\
		(_MX6Q_PAD_NANDF_CS3__GPIO_6_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS3__IPU2_SISG_1		\
		(_MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_CS3__TPSMP_CLK		\
		(_MX6Q_PAD_NANDF_CS3__TPSMP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ		\
		(_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD4_CMD__USDHC4_CMD_100MHZ	\
		(_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD4_CMD__USDHC4_CMD_200MHZ	\
		(_MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD4_CMD__RAWNAND_RDN		\
		(_MX6Q_PAD_SD4_CMD__RAWNAND_RDN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_SD4_CMD__UART3_TXD		\
		(_MX6Q_PAD_SD4_CMD__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD4_CMD__UART3_RXD		\
		(_MX6Q_PAD_SD4_CMD__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5		\
		(_MX6Q_PAD_SD4_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_CMD__GPIO_7_9		\
		(_MX6Q_PAD_SD4_CMD__GPIO_7_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR		\
		(_MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ	\
		(_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD4_CLK__USDHC4_CLK_100MHZ	\
		(_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD4_CLK__USDHC4_CLK_200MHZ	\
		(_MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD4_CLK__RAWNAND_WRN		\
		(_MX6Q_PAD_SD4_CLK__RAWNAND_WRN | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_SD4_CLK__UART3_TXD		\
		(_MX6Q_PAD_SD4_CLK__UART3_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD4_CLK__UART3_RXD		\
		(_MX6Q_PAD_SD4_CLK__UART3_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6		\
		(_MX6Q_PAD_SD4_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_CLK__GPIO_7_10		\
		(_MX6Q_PAD_SD4_CLK__GPIO_7_10 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_D0__RAWNAND_D0		\
		(_MX6Q_PAD_NANDF_D0__RAWNAND_D0 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_NANDF_D0__USDHC1_DAT4		\
		(_MX6Q_PAD_NANDF_D0__USDHC1_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0		\
		(_MX6Q_PAD_NANDF_D0__GPU3D_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16		\
		(_MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16		\
		(_MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D0__GPIO_2_0		\
		(_MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0		\
		(_MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0		\
		(_MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_D1__RAWNAND_D1		\
		(_MX6Q_PAD_NANDF_D1__RAWNAND_D1 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_NANDF_D1__USDHC1_DAT5		\
		(_MX6Q_PAD_NANDF_D1__USDHC1_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1		\
		(_MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17		\
		(_MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17		\
		(_MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D1__GPIO_2_1		\
		(_MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1		\
		(_MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1		\
		(_MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_D2__RAWNAND_D2		\
		(_MX6Q_PAD_NANDF_D2__RAWNAND_D2 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_NANDF_D2__USDHC1_DAT6		\
		(_MX6Q_PAD_NANDF_D2__USDHC1_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2		\
		(_MX6Q_PAD_NANDF_D2__GPU3D_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18		\
		(_MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18		\
		(_MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D2__GPIO_2_2		\
		(_MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2		\
		(_MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2		\
		(_MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_D3__RAWNAND_D3		\
		(_MX6Q_PAD_NANDF_D3__RAWNAND_D3 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_NANDF_D3__USDHC1_DAT7		\
		(_MX6Q_PAD_NANDF_D3__USDHC1_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3		\
		(_MX6Q_PAD_NANDF_D3__GPU3D_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19		\
		(_MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19		\
		(_MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D3__GPIO_2_3		\
		(_MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3		\
		(_MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3		\
		(_MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_D4__RAWNAND_D4		\
		(_MX6Q_PAD_NANDF_D4__RAWNAND_D4 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_NANDF_D4__USDHC2_DAT4		\
		(_MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4		\
		(_MX6Q_PAD_NANDF_D4__GPU3D_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20		\
		(_MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20		\
		(_MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D4__GPIO_2_4		\
		(_MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4		\
		(_MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4		\
		(_MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_D5__RAWNAND_D5		\
		(_MX6Q_PAD_NANDF_D5__RAWNAND_D5 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_NANDF_D5__USDHC2_DAT5		\
		(_MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5		\
		(_MX6Q_PAD_NANDF_D5__GPU3D_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21		\
		(_MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21		\
		(_MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D5__GPIO_2_5		\
		(_MX6Q_PAD_NANDF_D5__GPIO_2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5		\
		(_MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5		\
		(_MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_D6__RAWNAND_D6		\
		(_MX6Q_PAD_NANDF_D6__RAWNAND_D6 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_NANDF_D6__USDHC2_DAT6		\
		(_MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6		\
		(_MX6Q_PAD_NANDF_D6__GPU3D_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22		\
		(_MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22		\
		(_MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D6__GPIO_2_6		\
		(_MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6		\
		(_MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6		\
		(_MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_NANDF_D7__RAWNAND_D7		\
		(_MX6Q_PAD_NANDF_D7__RAWNAND_D7 | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL2))
#define  MX6Q_PAD_NANDF_D7__USDHC2_DAT7		\
		(_MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7		\
		(_MX6Q_PAD_NANDF_D7__GPU3D_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23		\
		(_MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23		\
		(_MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D7__GPIO_2_7		\
		(_MX6Q_PAD_NANDF_D7__GPIO_2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7		\
		(_MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7		\
		(_MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD4_DAT0__RAWNAND_D8		\
		(_MX6Q_PAD_SD4_DAT0__RAWNAND_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ	\
		(_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_100MHZ	\
		(_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_200MHZ	\
		(_MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD4_DAT0__RAWNAND_DQS		\
		(_MX6Q_PAD_SD4_DAT0__RAWNAND_DQS | MUX_PAD_CTRL(MX6Q_GPMI_PAD_CTRL1))
#define  MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24		\
		(_MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24		\
		(_MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT0__GPIO_2_8		\
		(_MX6Q_PAD_SD4_DAT0__GPIO_2_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8		\
		(_MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8		\
		(_MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD4_DAT1__RAWNAND_D9		\
		(_MX6Q_PAD_SD4_DAT1__RAWNAND_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ	\
		(_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_100MHZ	\
		(_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_200MHZ	\
		(_MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD4_DAT1__PWM3_PWMO		\
		(_MX6Q_PAD_SD4_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25		\
		(_MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25		\
		(_MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT1__GPIO_2_9		\
		(_MX6Q_PAD_SD4_DAT1__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9		\
		(_MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9		\
		(_MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD4_DAT2__RAWNAND_D10		\
		(_MX6Q_PAD_SD4_DAT2__RAWNAND_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ	\
		(_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_100MHZ	\
		(_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_200MHZ	\
		(_MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD4_DAT2__PWM4_PWMO		\
		(_MX6Q_PAD_SD4_DAT2__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26		\
		(_MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26		\
		(_MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT2__GPIO_2_10		\
		(_MX6Q_PAD_SD4_DAT2__GPIO_2_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10		\
		(_MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10		\
		(_MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD4_DAT3__RAWNAND_D11		\
		(_MX6Q_PAD_SD4_DAT3__RAWNAND_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ	\
		(_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_100MHZ	\
		(_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_200MHZ	\
		(_MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27		\
		(_MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27		\
		(_MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT3__GPIO_2_11		\
		(_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11		\
		(_MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11		\
		(_MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD4_DAT4__RAWNAND_D12		\
		(_MX6Q_PAD_SD4_DAT4__RAWNAND_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ	\
		(_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_100MHZ	\
		(_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_200MHZ	\
		(_MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD4_DAT4__UART2_TXD		\
		(_MX6Q_PAD_SD4_DAT4__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT4__UART2_RXD		\
		(_MX6Q_PAD_SD4_DAT4__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28		\
		(_MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28		\
		(_MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT4__GPIO_2_12		\
		(_MX6Q_PAD_SD4_DAT4__GPIO_2_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12		\
		(_MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12		\
		(_MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD4_DAT5__RAWNAND_D13		\
		(_MX6Q_PAD_SD4_DAT5__RAWNAND_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ	\
		(_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_100MHZ	\
		(_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_200MHZ	\
		(_MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD4_DAT5__UART2_CTS		\
		(_MX6Q_PAD_SD4_DAT5__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT5__UART2_RTS		\
		(_MX6Q_PAD_SD4_DAT5__UART2_RTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29		\
		(_MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29		\
		(_MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT5__GPIO_2_13		\
		(_MX6Q_PAD_SD4_DAT5__GPIO_2_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13		\
		(_MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13		\
		(_MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD4_DAT6__RAWNAND_D14		\
		(_MX6Q_PAD_SD4_DAT6__RAWNAND_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ	\
		(_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_100MHZ	\
		(_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_200MHZ	\
		(_MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD4_DAT6__UART2_CTS		\
		(_MX6Q_PAD_SD4_DAT6__UART2_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30		\
		(_MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30		\
		(_MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT6__GPIO_2_14		\
		(_MX6Q_PAD_SD4_DAT6__GPIO_2_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14		\
		(_MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14		\
		(_MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD4_DAT7__RAWNAND_D15		\
		(_MX6Q_PAD_SD4_DAT7__RAWNAND_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ	\
		(_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_100MHZ	\
		(_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_100MHZ))
#define  MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_200MHZ	\
		(_MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_200MHZ))
#define  MX6Q_PAD_SD4_DAT7__UART2_TXD		\
		(_MX6Q_PAD_SD4_DAT7__UART2_TXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT7__UART2_RXD		\
		(_MX6Q_PAD_SD4_DAT7__UART2_RXD | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31		\
		(_MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31		\
		(_MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT7__GPIO_2_15		\
		(_MX6Q_PAD_SD4_DAT7__GPIO_2_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15		\
		(_MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15		\
		(_MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD1_DAT1__USDHC1_DAT1		\
		(_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT1__ECSPI5_SS0		\
		(_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT1__PWM3_PWMO		\
		(_MX6Q_PAD_SD1_DAT1__PWM3_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT1__GPT_CAPIN2		\
		(_MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7		\
		(_MX6Q_PAD_SD1_DAT1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT1__GPIO_1_17		\
		(_MX6Q_PAD_SD1_DAT1__GPIO_1_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0		\
		(_MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8		\
		(_MX6Q_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_8 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD1_DAT0__USDHC1_DAT0		\
		(_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT0__ECSPI5_MISO		\
		(_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS		\
		(_MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT0__GPT_CAPIN1		\
		(_MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8		\
		(_MX6Q_PAD_SD1_DAT0__PCIE_CTRL_DIAG_STATUS_BUS_MUX_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT0__GPIO_1_16		\
		(_MX6Q_PAD_SD1_DAT0__GPIO_1_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1		\
		(_MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7		\
		(_MX6Q_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_7 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD1_DAT3__USDHC1_DAT3		\
		(_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT3__ECSPI5_SS2		\
		(_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3		\
		(_MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT3__PWM1_PWMO		\
		(_MX6Q_PAD_SD1_DAT3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B		\
		(_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT3__GPIO_1_21		\
		(_MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB		\
		(_MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6		\
		(_MX6Q_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_6 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD1_CMD__USDHC1_CMD		\
		(_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD1_CMD__ECSPI5_MOSI		\
		(_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_CMD__PWM4_PWMO		\
		(_MX6Q_PAD_SD1_CMD__PWM4_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_CMD__GPT_CMPOUT1		\
		(_MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_CMD__GPIO_1_18		\
		(_MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5		\
		(_MX6Q_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_5 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD1_DAT2__USDHC1_DAT2		\
		(_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT2__ECSPI5_SS1		\
		(_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2		\
		(_MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT2__PWM2_PWMO		\
		(_MX6Q_PAD_SD1_DAT2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B		\
		(_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT2__GPIO_1_19		\
		(_MX6Q_PAD_SD1_DAT2__GPIO_1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB		\
		(_MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4		\
		(_MX6Q_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_4 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD1_CLK__USDHC1_CLK		\
		(_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD1_CLK__ECSPI5_SCLK		\
		(_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT		\
		(_MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_CLK__GPT_CLKIN		\
		(_MX6Q_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_CLK__GPIO_1_20		\
		(_MX6Q_PAD_SD1_CLK__GPIO_1_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_CLK__PHY_DTB_0		\
		(_MX6Q_PAD_SD1_CLK__PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0		\
		(_MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD2_CLK__USDHC2_CLK		\
		(_MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD2_CLK__ECSPI5_SCLK		\
		(_MX6Q_PAD_SD2_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_CLK__KPP_COL_5		\
		(_MX6Q_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS		\
		(_MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9		\
		(_MX6Q_PAD_SD2_CLK__PCIE_CTRL_DIAG_STATUS_BUS_MUX_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_CLK__GPIO_1_10		\
		(_MX6Q_PAD_SD2_CLK__GPIO_1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_CLK__PHY_DTB_1		\
		(_MX6Q_PAD_SD2_CLK__PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1		\
		(_MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD2_CMD__USDHC2_CMD		\
		(_MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD2_CMD__ECSPI5_MOSI		\
		(_MX6Q_PAD_SD2_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_CMD__KPP_ROW_5		\
		(_MX6Q_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC		\
		(_MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10		\
		(_MX6Q_PAD_SD2_CMD__PCIE_CTRL_DIAG_STATUS_BUS_MUX_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_CMD__GPIO_1_11		\
		(_MX6Q_PAD_SD2_CMD__GPIO_1_11 | MUX_PAD_CTRL(NO_PAD_CTRL))

#define  MX6Q_PAD_SD2_DAT3__USDHC2_DAT3		\
		(_MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT3__ECSPI5_SS3		\
		(_MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT3__KPP_COL_6		\
		(_MX6Q_PAD_SD2_DAT3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC		\
		(_MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11		\
		(_MX6Q_PAD_SD2_DAT3__PCIE_CTRL_DIAG_STATUS_BUS_MUX_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT3__GPIO_1_12		\
		(_MX6Q_PAD_SD2_DAT3__GPIO_1_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT3__SJC_DONE		\
		(_MX6Q_PAD_SD2_DAT3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL))
#define  MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3		\
		(_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 | MUX_PAD_CTRL(NO_PAD_CTRL))

#endif