omap-secure.c
3.57 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
/*
* OMAP Secure API infrastructure.
*
* Copyright (C) 2011 Texas Instruments, Inc.
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
* Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
*
*
* This program is free software,you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/memblock.h>
#include <asm/cacheflush.h>
#include <asm/memblock.h>
#include "omap-secure.h"
static phys_addr_t omap_secure_memblock_base;
/**
* omap_sec_dispatcher: Routine to dispatch low power secure
* service routines
* @idx: The HAL API index
* @flag: The flag indicating criticality of operation
* @nargs: Number of valid arguments out of four.
* @arg1, arg2, arg3 args4: Parameters passed to secure API
*
* Return the non-zero error value on failure.
*/
u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
u32 arg3, u32 arg4)
{
u32 ret;
u32 param[5];
param[0] = nargs;
param[1] = arg1;
param[2] = arg2;
param[3] = arg3;
param[4] = arg4;
/*
* Secure API needs physical address
* pointer for the parameters
*/
flush_cache_all();
outer_clean_range(__pa(param), __pa(param + 5));
ret = omap_smc2(idx, flag, __pa(param));
return ret;
}
/* Allocate the memory to save secure ram */
int __init omap_secure_ram_reserve_memblock(void)
{
u32 size = OMAP_SECURE_RAM_STORAGE;
size = ALIGN(size, SECTION_SIZE);
omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE);
return 0;
}
phys_addr_t omap_secure_ram_mempool_base(void)
{
return omap_secure_memblock_base;
}
/**
* rx51_secure_dispatcher: Routine to dispatch secure PPA API calls
* @idx: The PPA API index
* @process: Process ID
* @flag: The flag indicating criticality of operation
* @nargs: Number of valid arguments out of four.
* @arg1, arg2, arg3 args4: Parameters passed to secure API
*
* Return the non-zero error value on failure.
*
* NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because
* it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1
*/
u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
u32 arg1, u32 arg2, u32 arg3, u32 arg4)
{
u32 ret;
u32 param[5];
param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */
param[1] = arg1;
param[2] = arg2;
param[3] = arg3;
param[4] = arg4;
/*
* Secure API needs physical address
* pointer for the parameters
*/
local_irq_disable();
local_fiq_disable();
flush_cache_all();
outer_clean_range(__pa(param), __pa(param + 5));
ret = omap_smc3(idx, process, flag, __pa(param));
flush_cache_all();
local_fiq_enable();
local_irq_enable();
return ret;
}
/**
* rx51_secure_update_aux_cr: Routine to modify the contents of Auxiliary Control Register
* @set_bits: bits to set in ACR
* @clr_bits: bits to clear in ACR
*
* Return the non-zero error value on failure.
*/
u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits)
{
u32 acr;
/* Read ACR */
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
acr &= ~clear_bits;
acr |= set_bits;
return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR,
0,
FLAG_START_CRITICAL,
1, acr, 0, 0, 0);
}
/**
* rx51_secure_rng_call: Routine for HW random generator
*/
u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag)
{
return rx51_secure_dispatcher(RX51_PPA_HWRNG,
0,
NO_FLAG,
3, ptr, count, flag, 0);
}