From bfe0cf499b653422bed0c1459046207c77e30bd9 Mon Sep 17 00:00:00 2001 From: byungbok Date: Sun, 30 Aug 2015 15:23:07 +0900 Subject: [PATCH] webconn tools --- DTK.700.350.175.087-192.NSIH.txt | 229 +++++++++++++++++++++++++++++++++++++++ README.md | 2 + usb-downloader | Bin 0 -> 38421 bytes 3 files changed, 231 insertions(+) create mode 100755 DTK.700.350.175.087-192.NSIH.txt create mode 100644 README.md create mode 100755 usb-downloader diff --git a/DTK.700.350.175.087-192.NSIH.txt b/DTK.700.350.175.087-192.NSIH.txt new file mode 100755 index 0000000..1edfd31 --- /dev/null +++ b/DTK.700.350.175.087-192.NSIH.txt @@ -0,0 +1,229 @@ +//------------------------------------------------------------------------------ +// Magiceyes Boot Header Format +//------------------------------------------------------------------------------ + +4648424D // 0x000 : Header ID = 0x4648424D ("MBHF") + +00200000 // 0x004 : Bootcode size +80000000 // 0x008 : Bootcode Load address +80000000 // 0x00C : Bootcode Excute address + +//------------------------------------------------------------------------------ +// OPTION +//------------------------------------------------------------------------------ +// [0] : Update DRAM configuration +// [1] : PHYZQENB +// [2] : PHYDLOCK +// [3] : Update Fast Channel Arbiter +// [4] : Update Slow Channel Arbiter +// [5] : Change PLL +// [6] : Update MCUS +// [7] : Writes memories : Addr, Data, Addr, Data, .... , 0 (End) +// [31:8] : Reserved for future use. must be 0 +//------------------------------------------------------------------------------ +//000000C0 // 0x010 : OPTION +000000E7 // 0x010 : OPTION +00000000 // 0x014 : DELAY - Delay counter, 0 ~ 0xFFFFFFFE + +//------------------------------------------------------------------------------ +// MCU-D registers +//------------------------------------------------------------------------------ +//02C00134 // 0x018 : CONFIG ; // 0x00 +//32A11055 // 0x01C : TIME0 ; // 0x04 +////00008002 // 0x020 : ENABLE ; // 0x08 +////00008007 // 0x020 : ENABLE ; // 0x08 +//00008003 // 0x020 : ENABLE ; // 0x08 +//65220100 // 0x024 : TIME1 ; // 0x10 +//20184200 // 0x028 : FASTCH[0] ; // 0x20 +//21080A10 // 0x02C : FASTCH[1] ; // 0x24 +//00084210 // 0x030 : FASTCH[2] ; // 0x28 +//06D1040C // 0x034 : SLOWCH[0] ; // 0x2C +//107338A4 // 0x038 : SLOWCH[1] ; // 0x30 +//0005A92F // 0x03C : SLOWCH[2] ; // 0x34 +//00000000 // 0x040 : DQSOFFSET ; // 0x94 +//F001D9DE // 0x044 : PHYDLL ; // 0x98 +//00000000 // 0x048 : PHYMODE ; // 0x9C +//00000003 // 0x04C : DLLLOCKSTART; // 0xA0 +//0000003B // 0x050 : DLLLOCKFORCE; // 0xA4 +//00000002 // 0x054 : ZQSTART ; // 0xAC - for Manul ZQ +//00000015 // 0x058 : ZQFORCE ; // 0xB0 - for Manul ZQ +//00000075 // 0x05C : ZQENB ; // 0xB4 +//00000001 // 0x060 : UPDATE ; // 0xB8 + +// 400 Mhz +02c10134 // 0x018 : CONFIG ; // 0x00 +3200f055 // 0x01C : TIME0 ; // 0x04 +00008003 // 0x020 : ENABLE ; // 0x08 +85223b00 // 0x024 : TIME1 ; // 0x10 +20184200 // 0x028 : FASTCH[0] ; // 0x20 +21080A10 // 0x02C : FASTCH[1] ; // 0x24 +00084210 // 0x030 : FASTCH[2] ; // 0x28 +06D1040C // 0x034 : SLOWCH[0] ; // 0x2C +107338A4 // 0x038 : SLOWCH[1] ; // 0x30 +0005A92F // 0x03C : SLOWCH[2] ; // 0x34 +00000000 // 0x040 : DQSOFFSET ; // 0x94 +7000A0A6 // 0x044 : PHYDLL ; // 0x98 +00000000 // 0x048 : PHYMODE ; // 0x9C +00000003 // 0x04C : DLLLOCKSTART; // 0xA0 +00000014 // 0x050 : DLLLOCKFORCE; // 0xA4 +00000002 // 0x054 : ZQSTART ; // 0xAC - for Manul ZQ +00000015 // 0x058 : ZQFORCE ; // 0xB0 - for Manul ZQ +00000074 // 0x05C : ZQENB ; // 0xB4 +00000001 // 0x060 : UPDATE ; // 0xB8 + + +//------------------------------------------------------------------------------ +// CLKPWR registers +//------------------------------------------------------------------------------ +//00000F01 // 0x064 : U32 CLKMODE[0] ; PLL0 / 2 / 16 +//00000700 // 0x064 : U32 CLKMODE[0] ; PLL0 / 0 / 8 +//00000300 // 0x064 : U32 CLKMODE[0] ; PLL0 / 0 / 4 +//00000103 // 0x064 : U32 CLKMODE[0] ; PLL0 / 4 / 2 +//00000101 // 0x064 : U32 CLKMODE[0] ; PLL0 / 2 / 2 +//00000400 // 0x064 : U32 CLKMODE[0] ; PLL0 / 1 / 5 +00000300 // 0x064 : U32 CLKMODE[0] ; PLL0 / 1 / 4 + +//00001733 // 0x068 : U32 CLKMODE[1] ; FCLK / 4 / 8 / 2 +00001131 // 0x068 : U32 CLKMODE[1] ; FCLK / 2 / 2 / 2 +//00001137 // 0x068 : U32 CLKMODE[1] ; FCLK / 4 / 1 / 2 +//00001101 // 0x068 : U32 CLKMODE[1] ; PLL0 / 2 / 2 / 2 + +000d5E01 // 0x06C : U32 PLLSET[0] ; @700Mhz +//000D0801 // 0x06C : U32 PLLSET[0] ; P=3, M=264, S=1 +//000C8501 // 0x06C : U32 PLLSET[0] ; P=3, M=133, S=1 +//000d5E01 // 0x06C : U32 PLLSET[0] ; P=3, M=350, S=1 -> 700 Mhz + +//000D2703 // 0x070 : U32 PLLSET[1] ; P=3, M=295, S=3 -> 147.500000 Mhz +00090003 // 0x070 : U32 PLLSET[1] ; P=2, M=256, S=3 -> 192.000000 Mhz + + +//------------------------------------------------------------------------------ +// MCUS +//------------------------------------------------------------------------------ +// static1 : 3-3-16-3-3 +4000039E // 0x074 : MEMBW +2F222220 // 0x078 : MEMTIMEACS[0] +0000F000 // 0x07C : MEMTIMEACS[1] +2F222220 // 0x080 : MEMTIMECOS[0] +00000300 // 0x084 : MEMTIMECOS[1] +0F0F0F05 // 0x088 : MEMTIMEACC[0] +0F010F0F // 0x08C : MEMTIMEACC[1] +04000000 // 0x090 : MEMTIMEACC[2] +0F0F0F05 // 0x094 : MEMTIMESACC[0] +0F010F0F // 0x098 : MEMTIMESACC[1] +00000000 // 0x09C : MEMTIMESACC[2] +00000000 // 0x0A0 : MEMTIMEWACC[0] +00000000 // 0x0A4 : MEMTIMEWACC[1] +00000000 // 0x0A8 : MEMTIMEWACC[2] +2F222220 // 0x0AC : MEMTIMECOH[0] +00000300 // 0x0B0 : MEMTIMECOH[1] +2F222220 // 0x0B4 : MEMTIMECAH[0] +00000300 // 0x0B8 : MEMTIMECAH[1] +00000000 // 0x0BC : MEMBURST +00000000 // 0x0C0 : Reserved +00005555 // 0x0C4 : MEMWAIT + +// static1 : 1-1-3-1-1 +//4000039E // 0x074 : MEMBW +//2F222200 // 0x078 : MEMTIMEACS[0] +//0000F000 // 0x07C : MEMTIMEACS[1] +//2F222200 // 0x080 : MEMTIMECOS[0] +//00000300 // 0x084 : MEMTIMECOS[1] +//0F0F0205 // 0x088 : MEMTIMEACC[0] +//0F010F0F // 0x08C : MEMTIMEACC[1] +//04000000 // 0x090 : MEMTIMEACC[2] +//0F0F0205 // 0x094 : MEMTIMESACC[0] +//0F010F0F // 0x098 : MEMTIMESACC[1] +//00000000 // 0x09C : MEMTIMESACC[2] +//00000000 // 0x0A0 : MEMTIMEWACC[0] +//00000000 // 0x0A4 : MEMTIMEWACC[1] +//00000000 // 0x0A8 : MEMTIMEWACC[2] +//2F222200 // 0x0AC : MEMTIMECOH[0] +//00000300 // 0x0B0 : MEMTIMECOH[1] +//2F222200 // 0x0B4 : MEMTIMECAH[0] +//00000300 // 0x0B8 : MEMTIMECAH[1] +//00000000 // 0x0BC : MEMBURST +//00000000 // 0x0C0 : Reserved +//00005555 // 0x0C4 : MEMWAIT + +//------------------------------------------------------------------------------ +// Reserved : +//------------------------------------------------------------------------------ +C000A0E4 // 0x0C8 : GPIOD ALTH +55554000 // 0x0CC : GPIOD[31:23] = { SA[8], SD[15:8] } +C000A120 // 0x0D0 : GPIOE ALTL +00055555 // 0x0D4 : GPIOE[ 9: 0] = { SA[18:9] } +00000000 // 0x0D8 +00000000 // 0x0DC +00000000 // 0x0E0 +00000000 // 0x0E4 +00000000 // 0x0E8 +00000000 // 0x0EC +00000000 // 0x0F0 +00000000 // 0x0F4 +00000000 // 0x0F8 +00000000 // 0x0FC +00000000 // 0x100 +00000000 // 0x104 +00000000 // 0x108 +00000000 // 0x10C +00000000 // 0x110 +00000000 // 0x114 +00000000 // 0x118 +00000000 // 0x11C +00000000 // 0x120 +00000000 // 0x124 +00000000 // 0x128 +00000000 // 0x12C +00000000 // 0x130 +00000000 // 0x134 +00000000 // 0x138 +00000000 // 0x13C +00000000 // 0x140 +00000000 // 0x144 +00000000 // 0x148 +00000000 // 0x14C +00000000 // 0x150 +00000000 // 0x154 +00000000 // 0x158 +00000000 // 0x15C +00000000 // 0x160 +00000000 // 0x164 +00000000 // 0x168 +00000000 // 0x16C +00000000 // 0x170 +00000000 // 0x174 +00000000 // 0x178 +00000000 // 0x17C +00000000 // 0x180 +00000000 // 0x184 +00000000 // 0x188 +00000000 // 0x18C +00000000 // 0x190 +00000000 // 0x194 +00000000 // 0x198 +00000000 // 0x19C +00000000 // 0x1A0 +00000000 // 0x1A4 +00000000 // 0x1A8 +00000000 // 0x1AC +00000000 // 0x1B0 +00000000 // 0x1B4 +00000000 // 0x1B8 +00000000 // 0x1BC +00000000 // 0x1C0 +00000000 // 0x1C4 +00000000 // 0x1C8 +00000000 // 0x1CC +00000000 // 0x1D0 +00000000 // 0x1D4 +00000000 // 0x1D8 +00000000 // 0x1DC +00000000 // 0x1E0 +00000000 // 0x1E4 +00000000 // 0x1E8 +00000000 // 0x1EC +00000000 // 0x1F0 +00000000 // 0x1F4 +00000000 // 0x1F8 +00000000 // 0x1FC diff --git a/README.md b/README.md new file mode 100644 index 0000000..5348265 --- /dev/null +++ b/README.md @@ -0,0 +1,2 @@ +Webconn에서 사용하는 tools + diff --git a/usb-downloader b/usb-downloader new file mode 100755 index 0000000000000000000000000000000000000000..b00a765c353752a65dc84fd75ac44f0edbcf5e66 GIT binary patch literal 38421 zcmeHwdwf*Y_3u72dCZV82@fF%>Hq=bgFFCfS{)Q2X#v?T=cus4YaOqP6u$(OP`8(pK%n_ghqK?sx6I*PN3x$+f+|-@W&r z9zM)o>$}%pYwfky-sjAjb9Oe&uA1X848ey(oGXYsp5v2{`V`{OI>~CRRJestj2B}? z29R|8_sJS66~*N-t(r@hmUE&^!~ar;0!ke|NpLw@!GcTnkV>*=9zIQ~@`nYACbl%U#a2&TT{?B*)G39Xk-|x`-??yvWY3?!NV>#v%mYV055s>7HPxTKvt#Hl zqa)^z|6sxkhtI6^=1jW(w^Vlu{*w;s*LA=48X~R2O_&$|$KwC2*?)NZvA^BC_Q(~r zqaWG&LH3)^y_fy-J3kwOssWFMP}rZqF|_Cpe`NstqXF=<2hd+WfPCHn@;3}1|I-2R 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