/*
 * Copyright 2016 Texas Instruments, Inc.
 *
 * K2G Industrial Communication Engine device tree
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;
#include "keystone-k2g.dtsi"
#include <dt-bindings/net/ti-dp83867.h>

/ {
	compatible =  "ti,k2g-ice", "ti,k2g", "ti,keystone";
	model = "Texas Instruments K2G Industrial Communication Engine";

	memory {
		device_type = "memory";
		reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dsp_common_mpm_area: dsp_reserved_mpm_area {
			compatible = "shared-dma-pool";
			reg = <0x00000008 0x1d000000 0x00000000 0x2800000>;
			no-map;
			status = "okay";
		};

		dsp_common_cma_pool: dsp_common_cma_pool {
			compatible = "shared-dma-pool";
			reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
			reusable;
		};
	};

	aliases {
		ethernet1 = &pruss0_emac0;
		ethernet2 = &pruss0_emac1;
		ethernet3 = &pruss1_emac0;
		ethernet4 = &pruss1_emac1;
	};

	vmain: fixedregulator-vmain {
		compatible = "regulator-fixed";
		regulator-name = "vmain_fixed";
		/* Actual range from 12 to 24v */
		regulator-min-microvolt = <24000000>;
		regulator-max-microvolt = <24000000>;
		regulator-always-on;
	};

	v5_0: fixedregulator-v5_0 {
		/* TPS54531 */
		compatible = "regulator-fixed";
		regulator-name = "v5_0_fixed";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vmain>;
		regulator-always-on;
	};

	vdd_3v3: fixedregulator-vdd_3v3 {
		/* TLV62084 */
		compatible = "regulator-fixed";
		regulator-name = "vdd_3v3_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&v5_0>;
		regulator-always-on;
	};

	vdd_1v8: fixedregulator-vdd_1v8 {
		/* TLV62084 */
		compatible = "regulator-fixed";
		regulator-name = "vdd_1v8_fixed";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&v5_0>;
		regulator-always-on;
	};

	vdds_ddr: fixedregulator-vdds_ddr {
		/* TLV62080 */
		compatible = "regulator-fixed";
		regulator-name = "vdds_ddr_fixed";
		regulator-min-microvolt = <1350000>;
		regulator-max-microvolt = <1350000>;
		vin-supply = <&v5_0>;
		regulator-always-on;
	};

	vref_ddr: fixedregulator-vref_ddr {
		/* LP2996A */
		compatible = "regulator-fixed";
		regulator-name = "vref_ddr_fixed";
		regulator-min-microvolt = <675000>;
		regulator-max-microvolt = <675000>;
		vin-supply = <&vdd_3v3>;
		regulator-always-on;
	};

	vtt_ddr: fixedregulator-vtt_ddr {
		/* LP2996A */
		compatible = "regulator-fixed";
		regulator-name = "vtt_ddr_fixed";
		regulator-min-microvolt = <675000>;
		regulator-max-microvolt = <675000>;
		vin-supply = <&vdd_3v3>;
		regulator-always-on;
	};

	vdd_0v9: fixedregulator-vdd_0v9 {
		/* TPS62180 */
		compatible = "regulator-fixed";
		regulator-name = "vdd_0v9_fixed";
		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <900000>;
		vin-supply = <&v5_0>;
		regulator-always-on;
	};


	vddb: fixedregulator-vddb {
		/* TPS22945 */
		compatible = "regulator-fixed";
		regulator-name = "vddb_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		gpio = <&gpio1 53 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	soc {
		mpm_mem: dspmem@9d000000 {
			compatible = "ti,keystone-dsp-mem";
			reg = <0x9d000000 0x2800000>;
		};
	};

	rotary-in0 {
		compatible = "rotary-encoder";
		gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>,
			<&pca9536 2 GPIO_ACTIVE_HIGH>,
			<&pca9536 1 GPIO_ACTIVE_HIGH>,
			<&pca9536 0 GPIO_ACTIVE_HIGH>;
		linux,axis = <0>; /* ABS_X */
		rotary-encoder,steps = <10>;
		rotary-encoder,absolute-encoder;
	};

	leds1 {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&user_leds>;

		led0 {
			label = "status0:red:cpu0";
			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "cpu0";
		};

		led1 {
			label = "status0:green:usr";
			gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led2 {
			label = "status0:yellow:usr";
			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led3 {
			label = "status1:red:mmc0";
			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "mmc0";
		};

		led4 {
			label = "status1:green:usr";
			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led5 {
			label = "status1:yellow:usr";
			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led6 {
			label = "status2:red:usr";
			gpios = <&gpio0 44 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led7 {
			label = "status2:green:usr";
			gpios = <&gpio0 43 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led8 {
			label = "status2:yellow:usr";
			gpios = <&gpio0 42 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led9 {
			label = "status3:red:usr";
			gpios = <&gpio0 41 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led10 {
			label = "status3:green:usr";
			gpios = <&gpio0 101 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led11 {
			label = "status3:yellow:usr";
			gpios = <&gpio0 102 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led12 {
			label = "status4:green:heartbeat";
			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	/* Dual-MAC Ethernet application node on PRU-ICSS0 */
	pruss0_eth {
		compatible = "ti,k2g-prueth";
		pruss = <&pruss0>;
		sram = <&msm_ram>;
		interrupt-parent = <&pruss0_intc>;

		pruss0_emac0: ethernet-mii0 {
			phy-handle = <&pruss0_eth0_phy>;
			phy-mode = "mii";
			interrupts = <20>, <22>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		pruss0_emac1: ethernet-mii1 {
			phy-handle = <&pruss0_eth1_phy>;
			phy-mode = "mii";
			interrupts = <21>, <23>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};

	/* Dual-MAC Ethernet application node on PRU-ICSS1 */
	pruss1_eth {
		compatible = "ti,k2g-prueth";
		pruss = <&pruss1>;
		sram = <&msm_ram>;
		interrupt-parent = <&pruss1_intc>;

		pruss1_emac0: ethernet-mii0 {
			phy-handle = <&pruss1_eth0_phy>;
			phy-mode = "mii";
			interrupts = <20>, <22>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		pruss1_emac1: ethernet-mii1 {
			phy-handle = <&pruss1_eth1_phy>;
			phy-mode = "mii";
			interrupts = <21>, <23>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};
};

&k2g_pinctrl {

	uart0_pins: pinmux_uart0_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
			K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
		>;
	};

	mmc1_pins: pinmux_mmc1_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x10FC) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat3.mmc1_dat3 */
			K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat2.mmc1_dat2 */
			K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat1.mmc1_dat1 */
			K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat0.mmc1_dat0 */
			K2G_CORE_IOPAD(0x110C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_clk.mmc1_clk */
			K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_cmd.mmc1_cmd */
			K2G_CORE_IOPAD(0x1114) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* mmc1_sdcd.gpio0_69 */
			K2G_CORE_IOPAD(0x1118) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_sdwp.mmc1_sdwp */
			K2G_CORE_IOPAD(0x111C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_pow.mmc1_pow */
		>;
	};

	qspi_pins: pinmux_qspi_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
			K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
			K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
			K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
			K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
			K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
			K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
		>;
	};

	i2c0_pins: pinmux_i2c0_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
			K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
		>;
	};

	i2c1_pins: pinmux_i2c1_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c1_scl.i2c1_scl */
			K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c1_sda.i2c1_sda */
		>;
	};

	user_leds: pinmux_user_leds {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x102c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_ad11.gpio0_11 */
			K2G_CORE_IOPAD(0x1030) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_ad12.gpio0_12 */
			K2G_CORE_IOPAD(0x1034) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_ad13.gpio0_13 */
			K2G_CORE_IOPAD(0x1038) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_ad14.gpio0_14 */
			K2G_CORE_IOPAD(0x103c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_ad15.gpio0_15 */
			K2G_CORE_IOPAD(0x1040) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_clk.gpio0_16 */
			K2G_CORE_IOPAD(0x104c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_wen.gpio0_19 */
			K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* dss_data9.gpio0_44 */
			K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* dss_data10.gpio0_43 */
			K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* dss_data11.gpio0_42 */
			K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* dss_data12.gpio0_41 */
			K2G_CORE_IOPAD(0x11b8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* spi2_scsn0.gpio0_101 */
			K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* spi2_scsn1.gpio0_102 */
		>;
	};

	pruss0_mdio_default: pruss0_mdio_default {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x12cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* pr0_mdio_data.pr0_mdio_data */
			K2G_CORE_IOPAD(0x12d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)	/* pr0_mdio_mdclk.pr0_mdio_mdclk */
			K2G_CORE_IOPAD(0x105c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE3)	/* gpmc_wait1.gpio0_23 (pr0_mii0_resetn) */
			K2G_CORE_IOPAD(0x1070) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_csn2.gpio0_28 (pr0_mii0_intn) */
			K2G_CORE_IOPAD(0x1054) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE3)	/* gpmc_be1n.gpio0_21 (pr0_mii1_resetn) */
			K2G_CORE_IOPAD(0x1074) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_csn3.gpio0_29 (pr0_mii1_intn) */
		>;
	};

	pruss1_mdio_default: pruss1_mdio_default {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* pr1_mdio_data.pr1_mdio_data */
			K2G_CORE_IOPAD(0x1378) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)	/* pr1_mdio_mdclk.pr1_mdio_mdclk */
			K2G_CORE_IOPAD(0x1050) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE3)	/* gpmc_be0ncle.gpio0_20 (pr1_mii0_resetn) */
			K2G_CORE_IOPAD(0x1044) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_advnale.gpio0_17 (pr1_mii0_intn) */
			K2G_CORE_IOPAD(0x1060) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE3)	/* gpmc_wpn.gpio0_24 (pr1_mii1_resetn) */
			K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_wait0.gpio0_22 (pr1_mii1_intn) */
		>;
	};

	pruss0_eth_default: pruss0_eth_default {
		pinctrl-single,pins = <
			/* PRUSS0 External Mux routing */
			K2G_CORE_IOPAD(0x11d4) (BUFFER_CLASS_B | MUX_MODE3)			/* uart0_ctsn.gpio0_106 */
			K2G_CORE_IOPAD(0x11d8) (BUFFER_CLASS_B | MUX_MODE3)			/* uart0_rtsn.gpio0_107 */
			K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | MUX_MODE3)			/* dcan0_rx.gpio1_57 */
			K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | MUX_MODE3)			/* dcan0_tx.gpio1_56 */
			K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | MUX_MODE3)			/* qspi_csn2.gpio1_66 */
			K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | MUX_MODE3)			/* qspi_csn3.gpio1_67 */

			/* PRUSS0 PRU0 Ethernet */
			K2G_CORE_IOPAD(0x122c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru0_gpo0.pr0_pru0_gpi0 (pr0_mii0_rxd0) */
			K2G_CORE_IOPAD(0x1230) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru0_gpo1.pr0_pru0_gpi1 (pr0_mii0_rxd1) */
			K2G_CORE_IOPAD(0x1234) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru0_gpo2.pr0_pru0_gpi2 (pr0_mii0_rxd2) */
			K2G_CORE_IOPAD(0x1238) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru0_gpo3.pr0_pru0_gpi3 (pr0_mii0_rxd3) */
			K2G_CORE_IOPAD(0x123c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru0_gpo4.pr0_pru0_gpi4 (pr0_mii0_rxdv) */
			K2G_CORE_IOPAD(0x1240) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru0_gpo5.pr0_pru0_gpi5 (pr0_mii0_rxer) */
			K2G_CORE_IOPAD(0x1244) (BUFFER_CLASS_B | MUX_MODE1)			/* pr0_pru0_gpo6.pr0_pru0_gpi6 (pr0_mii_mr0_clk) */

			K2G_CORE_IOPAD(0x124c) (BUFFER_CLASS_B | MUX_MODE1)			/* pr0_pru0_gpo8.pr0_pru0_gpi8 (pr0_mii0_rxlink) */
			K2G_CORE_IOPAD(0x1250) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru0_gpo9.pr0_pru0_gpi9 (pr0_mii0_col) */
			K2G_CORE_IOPAD(0x1254) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru0_gpo10.pr0_pru0_gpi10 (pr0_mii0_crs) */

			K2G_CORE_IOPAD(0x12a8) (BUFFER_CLASS_B | MUX_MODE0)			/* pr0_pru1_gpo11.pr0_pru1_gpo11 (pr0_mii0_txd0) */
			K2G_CORE_IOPAD(0x12ac) (BUFFER_CLASS_B | MUX_MODE0)			/* pr0_pru1_gpo12.pr0_pru1_gpo12 (pr0_mii0_txd1) */
			K2G_CORE_IOPAD(0x12b0) (BUFFER_CLASS_B | MUX_MODE0)			/* pr0_pru1_gpo13.pr0_pru1_gpo13 (pr0_mii0_txd2) */
			K2G_CORE_IOPAD(0x12b4) (BUFFER_CLASS_B | MUX_MODE0)			/* pr0_pru1_gpo14.pr0_pru1_gpo14 (pr0_mii0_txd3) */
			K2G_CORE_IOPAD(0x12b8) (BUFFER_CLASS_B | MUX_MODE0)			/* pr0_pru1_gpo15.pr0_pru1_gpo15 (pr0_mii0_txen) */
			K2G_CORE_IOPAD(0x12bc) (BUFFER_CLASS_B | MUX_MODE1)			/* pr0_pru1_gpo16.pr0_pru1_gpo16 (pr0_mii_mt0_clk) */

			/* PRUSS0 PRU1 Ethernet */
			K2G_CORE_IOPAD(0x127c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru1_gpo0.pr0_pru1_gpi0 (pr0_mii1_rxd0) */
			K2G_CORE_IOPAD(0x1280) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru1_gpo1.pr0_pru1_gpi1 (pr0_mii1_rxd1) */
			K2G_CORE_IOPAD(0x1284) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru1_gpo2.pr0_pru1_gpi2 (pr0_mii1_rxd2) */
			K2G_CORE_IOPAD(0x1288) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru1_gpo3.pr0_pru1_gpi3 (pr0_mii1_rxd3) */
			K2G_CORE_IOPAD(0x128c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru1_gpo4.pr0_pru1_gpi4 (pr0_mii1_rxdv) */
			K2G_CORE_IOPAD(0x1290) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru1_gpo5.pr0_pru1_gpi5 (pr0_mii1_rxer) */
			K2G_CORE_IOPAD(0x1294) (BUFFER_CLASS_B | MUX_MODE1)			/* pr0_pru1_gpo6.pr0_pru1_gpi6 (pr0_mii_mr1_clk) */

			K2G_CORE_IOPAD(0x129c) (BUFFER_CLASS_B | MUX_MODE1)			/* pr0_pru1_gpo8.pr0_pru1_gpi8 (pr0_mii1_rxlink) */
			K2G_CORE_IOPAD(0x12a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru1_gpo9.pr0_pru1_gpi9 (pr0_mii1_col) */
			K2G_CORE_IOPAD(0x12a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr0_pru1_gpo10.pr0_pru1_gpi10 (pr0_mii1_crs) */

			K2G_CORE_IOPAD(0x1258) (BUFFER_CLASS_B | MUX_MODE0)			/* pr0_pru0_gpo11.pr0_pru0_gpo11 (pr0_mii1_txd0) */
			K2G_CORE_IOPAD(0x125c) (BUFFER_CLASS_B | MUX_MODE0)			/* pr0_pru0_gpo12.pr0_pru0_gpo12 (pr0_mii1_txd1) */
			K2G_CORE_IOPAD(0x1260) (BUFFER_CLASS_B | MUX_MODE0)			/* pr0_pru0_gpo13.pr0_pru0_gpo13 (pr0_mii1_txd2) */
			K2G_CORE_IOPAD(0x1264) (BUFFER_CLASS_B | MUX_MODE0)			/* pr0_pru0_gpo14.pr0_pru0_gpo14 (pr0_mii1_txd3) */
			K2G_CORE_IOPAD(0x1268) (BUFFER_CLASS_B | MUX_MODE0)			/* pr0_pru0_gpo15.pr0_pru0_gpo15 (pr0_mii1_txen) */
			K2G_CORE_IOPAD(0x126c) (BUFFER_CLASS_B | MUX_MODE1)			/* pr0_pru0_gpo16.pr0_pru0_gpo16 (pr0_mii_mt1_clk) */
		>;
	};

	pruss1_eth_default: pruss1_eth_default {
		pinctrl-single,pins = <
			/* PRUSS1 PRU0 Ethernet */
			K2G_CORE_IOPAD(0x12d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr1_pru0_gpo0.pr1_pru0_gpi0 (pr1_mii0_rxd0) */
			K2G_CORE_IOPAD(0x12d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr1_pru0_gpo1.pr1_pru0_gpi1 (pr1_mii0_rxd1) */
			K2G_CORE_IOPAD(0x12dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr1_pru0_gpo2.pr1_pru0_gpi2 (pr1_mii0_rxd2) */
			K2G_CORE_IOPAD(0x12e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr1_pru0_gpo3.pr1_pru0_gpi3 (pr1_mii0_rxd3) */
			K2G_CORE_IOPAD(0x12e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr1_pru0_gpo4.pr1_pru0_gpi4 (pr1_mii0_rxdv) */
			K2G_CORE_IOPAD(0x12e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr1_pru0_gpo5.pr1_pru0_gpi5 (pr1_mii0_rxer) */
			K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | MUX_MODE1)			/* pr1_pru0_gpo6.pr1_pru0_gpi6 (pr1_mii_mr0_clk) */

			K2G_CORE_IOPAD(0x12f4) (BUFFER_CLASS_B | MUX_MODE1)			/* pr1_pru0_gpo8.pr1_pru0_gpi8 (pr1_mii0_rxlink) */
			K2G_CORE_IOPAD(0x12f8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr1_pru0_gpo9.pr1_pru0_gpi9 (pr1_mii0_col) */
			K2G_CORE_IOPAD(0x12fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr1_pru0_gpo10.pr1_pru0_gpi10 (pr1_mii0_crs) */

			K2G_CORE_IOPAD(0x1350) (BUFFER_CLASS_B | MUX_MODE0)			/* pr1_pru1_gpo11.pr1_pru1_gpo11 (pr1_mii0_txd0) */
			K2G_CORE_IOPAD(0x1354) (BUFFER_CLASS_B | MUX_MODE0)			/* pr1_pru1_gpo12.pr1_pru1_gpo12 (pr1_mii0_txd1) */
			K2G_CORE_IOPAD(0x1358) (BUFFER_CLASS_B | MUX_MODE0)			/* pr1_pru1_gpo13.pr1_pru1_gpo13 (pr1_mii0_txd2) */
			K2G_CORE_IOPAD(0x135c) (BUFFER_CLASS_B | MUX_MODE0)			/* pr1_pru1_gpo14.pr1_pru1_gpo14 (pr1_mii0_txd3) */
			K2G_CORE_IOPAD(0x1360) (BUFFER_CLASS_B | MUX_MODE0)			/* pr1_pru1_gpo15.pr1_pru1_gpo15 (pr1_mii0_txen) */
			K2G_CORE_IOPAD(0x1364) (BUFFER_CLASS_B | MUX_MODE1)			/* pr1_pru1_gpo16.pr1_pru1_gpo16 (pr1_mii_mt0_clk) */

			/* PRUSS1 PRU1 Ethernet */
			K2G_CORE_IOPAD(0x1324) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr1_pru1_gpo0.pr1_pru1_gpi0 (pr1_mii1_rxd0) */
			K2G_CORE_IOPAD(0x132c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr1_pru1_gpo2.pr1_pru1_gpi2 (pr1_mii1_rxd2) */
			K2G_CORE_IOPAD(0x1330) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr1_pru1_gpo3.pr1_pru1_gpi3 (pr1_mii1_rxd3) */
			K2G_CORE_IOPAD(0x1334) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr1_pru1_gpo4.pr1_pru1_gpi4 (pr1_mii1_rxdv) */
			K2G_CORE_IOPAD(0x1338) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr1_pru1_gpo5.pr1_pru1_gpi5 (pr1_mii1_rxer) */
			K2G_CORE_IOPAD(0x133c) (BUFFER_CLASS_B | MUX_MODE1)			/* pr1_pru1_gpo6.pr1_pru1_gpi6 (pr1_mii_mr1_clk) */

			K2G_CORE_IOPAD(0x1344) (BUFFER_CLASS_B | MUX_MODE1)			/* pr1_pru1_gpo8.pr1_pru1_gpi8 (pr1_mii1_rxlink) */
			K2G_CORE_IOPAD(0x1348) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr1_pru1_gpo9.pr1_pru1_gpi9 (pr1_mii1_col) */
			K2G_CORE_IOPAD(0x134c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* pr1_pru1_gpo10.pr1_pru1_gpi10 (pr1_mii1_crs) */

			K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | MUX_MODE0)			/* pr1_pru0_gpo11.pr1_pru0_gpo11 (pr1_mii1_txd0) */
			K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | MUX_MODE0)			/* pr1_pru0_gpo12.pr1_pru0_gpo12 (pr1_mii1_txd1) */
			K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | MUX_MODE0)			/* pr1_pru0_gpo13.pr1_pru0_gpo13 (pr1_mii1_txd2) */
			K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | MUX_MODE0)			/* pr1_pru0_gpo14.pr1_pru0_gpo14 (pr1_mii1_txd3) */
			K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | MUX_MODE0)			/* pr1_pru0_gpo15.pr1_pru0_gpo15 (pr1_mii1_txen) */
			K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | MUX_MODE1)			/* pr1_pru0_gpo16.pr1_pru0_gpo16 (pr1_mii_mt1_clk) */
		>;
	};

	rgmii_pins: pinmux_rmgii_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_B | MUX_MODE1)			/* mii_txclk.rgmii_txc */
			K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_B | MUX_MODE1)			/* mii_rxclk.rgmii_rxc */
			K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* mii_rxd3.rgmii_rxd3 */
			K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* mii_rxd2.rgmii_rxd2 */
			K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* mii_rxd1.rgmii_rxd1 */
			K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* mii_rxd0.rgmii_rxd0 */
			K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1)	/* mii_rxdv.rgmii_rxctl */
			K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_B | MUX_MODE1)			/* mii_txd3.rgmii_txd3 */
			K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_B | MUX_MODE1)			/* mii_txd2.rgmii_txd2 */
			K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_B | MUX_MODE1)			/* mii_txd1.rgmii_txd1 */
			K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_B | MUX_MODE1)			/* mii_txd0.rgmii_txd0 */
			K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_B | MUX_MODE1)			/* mii_txen.rgmii_txctl */
		>;
	};

	mdio_pins: pinmux_mdio_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | MUX_MODE0)			/* mdio_data.mdio_data */
			K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | MUX_MODE0)			/* mdio_clk.mdio_clk */
		>;
	};
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	vmmc-supply = <&vdd_3v3>;
	cd-gpios = <&gpio0 69 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&qspi {
	pinctrl-names = "default";
	pinctrl-0 = <&qspi_pins>;
	status = "okay";

	flash0: m25p80@0 {
		compatible = "s25fl256s1", "jedec,spi-nor";
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <96000000>;
		#address-cells = <1>;
		#size-cells = <1>;
		cdns,read-delay = <2>;
		cdns,tshsl-ns = <500>;
		cdns,tsd2d-ns = <500>;
		cdns,tchsh-ns = <119>;
		cdns,tslch-ns = <119>;

		partition@0 {
			label = "QSPI.u-boot";
			reg = <0x00000000 0x00100000>;
		};
		partition@1 {
			label = "QSPI.u-boot-env";
			reg = <0x00100000 0x00040000>;
		};
		partition@2 {
			label = "QSPI.skern";
			reg = <0x00140000 0x0040000>;
		};
		partition@3 {
			label = "QSPI.pmmc-firmware";
			reg = <0x00180000 0x0040000>;
		};
		partition@4 {
			label = "QSPI.kernel";
			reg = <0x001c0000 0x0800000>;
		};
		partition@5 {
			label = "QSPI.u-boot-spl-os";
			reg = <0x009c0000 0x0040000>;
		};
		partition@6 {
			label = "QSPI.file-system";
			reg = <0x00a00000 0x1600000>;
		};
	};
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "okay";

	eeprom@50 {
		compatible = "atmel,24c256";
		reg = <0x50>;
	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "okay";
	clock-frequency = <400000>;

	/* osd9616p0899-10 */
	display@3c {
		compatible = "solomon,ssd1306fb-i2c";
		reg = <0x3c>;
		reset-gpios = <&gpio1 52 GPIO_ACTIVE_HIGH>;
		vbat-supply = <&vddb>;
		solomon,height = <16>;
		solomon,width = <96>;
		solomon,com-seq;
		solomon,com-invdir;
		solomon,page-offset = <0>;
		solomon,prechargep1 = <2>;
		solomon,prechargep2 = <13>;
	};

	pca9536: gpio@41 {
		compatible = "ti,pca9536";
		reg = <0x41>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&gpio0 {
	status = "okay";
};

&dsp0 {
	memory-region = <&dsp_common_cma_pool>;
};

&pru0_0 {
	ti,pruss-gp-mux-sel = <2>;	/* MII mux, needed for PR0_MII0 & PR0_MII1 */
};

&pru0_1 {
	ti,pruss-gp-mux-sel = <2>;	/* MII mux, needed for PR0_MII1 & PR0_MII1 */
};

&pru1_0 {
	ti,pruss-gp-mux-sel = <2>;	/* MII mux, needed for PR1_MII0 & PR1_MII1 */
};

&pru1_1 {
	ti,pruss-gp-mux-sel = <2>;	/* MII mux, needed for PR1_MII1 & PR1_MII1 */
};

&pruss0 {
	pinctrl-0 = <&pruss0_eth_default>;
	pinctrl-names = "default";
};

&pruss1 {
	pinctrl-0 = <&pruss1_eth_default>;
	pinctrl-names = "default";
};

&pruss0_mdio {
	status = "okay";
	pinctrl-0 = <&pruss0_mdio_default>;
	pinctrl-names = "default";
	reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
		      <&gpio0 21 GPIO_ACTIVE_LOW>;
	reset-delay-us = <20>;

	pruss0_eth0_phy: ethernet-phy@0 {
		reg = <0>;
		interrupt-parent = <&gpio0>;
		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
	};

	pruss0_eth1_phy: ethernet-phy@1 {
		reg = <1>;
		interrupt-parent = <&gpio0>;
		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
	};
};

&pruss1_mdio {
	status = "okay";
	pinctrl-0 = <&pruss1_mdio_default>;
	pinctrl-names = "default";
	reset-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>,
		      <&gpio0 24 GPIO_ACTIVE_LOW>;
	reset-delay-us = <20>;

	pruss1_eth0_phy: ethernet-phy@2 {
		reg = <2>;
		interrupt-parent = <&gpio0>;
		interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
	};

	pruss1_eth1_phy: ethernet-phy@3 {
		reg = <3>;
		interrupt-parent = <&gpio0>;
		interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
	};
};

&qmss {
	status = "okay";
};

&knav_dmas {
	status = "okay";
};

&gbe_subsys {
	status = "okay";
};

&netcp {
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>;
	status = "okay";
};

&mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;
	status = "okay";
	ethphy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
		ti,min-output-impedance;
		ti,strap-mode = <DP83867_4LEVEL_STRAP_MODE1>;
	};
};

&gbe0 {
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii-id";
};