/* * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ /dts-v1/; #include "dra72x.dtsi" #include #include #include "am57xx-idk-common.dtsi" / { model = "TI AM5718 IDK"; compatible = "ti,am5718-idk", "ti,am5718", "ti,dra722", "ti,dra72", "ti,dra7"; aliases { ethernet2 = &pruss1_emac0; ethernet3 = &pruss1_emac1; ethernet4 = &pruss2_emac0; ethernet5 = &pruss2_emac1; }; memory { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; ipu2_cma_pool: ipu2_cma@95800000 { compatible = "shared-dma-pool"; reg = <0x0 0x95800000 0x0 0x3800000>; reusable; status = "okay"; }; dsp1_cma_pool: dsp1_cma@99000000 { compatible = "shared-dma-pool"; reg = <0x0 0x99000000 0x0 0x4000000>; reusable; status = "okay"; }; ipu1_cma_pool: ipu1_cma@9d000000 { compatible = "shared-dma-pool"; reg = <0x0 0x9d000000 0x0 0x2000000>; reusable; status = "okay"; }; }; leds@1 { compatible = "gpio-leds"; led@0 { label = "status0:red:cpu0"; gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "cpu0"; }; led@1 { label = "status0:green:usr"; gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led@2 { label = "status0:blue:heartbeat"; gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "heartbeat"; }; led@3 { label = "status1:red:usr"; gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led@4 { label = "status1:green:usr"; gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; default-state = "off"; }; led@5 { label = "status1:blue:mmc0"; gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "mmc0"; }; }; /* Dual mac ethernet application node on icss2 */ pruss1_eth: pruss1_eth { status = "okay"; compatible = "ti,am57-prueth"; pruss = <&pruss1>; sram = <&ocmcram1>; interrupt-parent = <&pruss1_intc>; pruss1_emac0: ethernet-mii0 { phy-handle = <&pruss1_eth0_phy>; phy-mode = "mii"; interrupts = <20>, <22>; interrupt-names = "rx", "tx"; /* Filled in by bootloader */ local-mac-address = [00 00 00 00 00 00]; }; pruss1_emac1: ethernet-mii1 { phy-handle = <&pruss1_eth1_phy>; phy-mode = "mii"; interrupts = <21>, <23>; interrupt-names = "rx", "tx"; /* Filled in by bootloader */ local-mac-address = [00 00 00 00 00 00]; }; }; }; &dra7_pmx_core { mmc1_pins_default: mmc1_pins_default { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; mmc1_pins_hs: mmc1_pins_hs { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; mmc1_pins_sdr50: pinmux_mmc1_sdr50_pins { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; mmc1_pins_sdr104: pinmux_mmc1_sdr104_pins { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; mmc2_pins_default: mmc2_pins_default { pinctrl-single,pins = < 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ >; }; mmc2_pins_hs: mmc2_pins_hs { pinctrl-single,pins = < 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ >; }; mmc2_pins_ddr_1_8v: mmc2_pins_ddr_1_8v { pinctrl-single,pins = < 0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ >; }; }; &dra7_iodelay_core { mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf { pinctrl-single,pins = < 0x618 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */ 0x624 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_IN */ 0x630 (A_DELAY(495) | G_DELAY(0)) /* CFG_MMC1_DAT0_IN */ 0x63C (A_DELAY(116) | G_DELAY(0)) /* CFG_MMC1_DAT1_IN */ 0x648 (A_DELAY(117) | G_DELAY(0)) /* CFG_MMC1_DAT2_IN */ 0x654 (A_DELAY(32) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */ 0x620 (A_DELAY(1224) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */ 0x62C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ 0x638 (A_DELAY(44) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ 0x644 (A_DELAY(64) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ 0x650 (A_DELAY(79) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ 0x65C (A_DELAY(87) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ 0x64C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ >; }; mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf { pinctrl-single,pins = < 0x620 (A_DELAY(520) | G_DELAY(320)) /* CFG_MMC1_CLK_OUT */ 0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ 0x638 (A_DELAY(40) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ 0x644 (A_DELAY(83) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ 0x650 (A_DELAY(98) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ 0x65c (A_DELAY(106) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ 0x628 (A_DELAY(51) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ 0x640 (A_DELAY(363) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ 0x64c (A_DELAY(199) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ 0x658 (A_DELAY(273) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ >; }; mmc2_iodelay_ddr_1_8v_conf: mmc2_iodelay_ddr_1_8v_conf { pinctrl-single,pins = < 0x18c (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_IN */ 0x1a4 (A_DELAY(121) | G_DELAY(0)) /* CFG_GPMC_A20_IN */ 0x1b0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_IN */ 0x1bc (A_DELAY(20) | G_DELAY(0)) /* CFG_GPMC_A22_IN */ 0x1c8 (A_DELAY(108) | G_DELAY(0)) /* CFG_GPMC_A23_IN */ 0x1d4 (A_DELAY(31) | G_DELAY(0)) /* CFG_GPMC_A24_IN */ 0x1e0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */ 0x1ec (A_DELAY(24) | G_DELAY(0)) /* CFG_GPMC_A26_IN */ 0x1f8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_IN */ 0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */ 0x194 (A_DELAY(152) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */ 0x1ac (A_DELAY(206) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */ 0x1b8 (A_DELAY(78) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */ 0x1c4 (A_DELAY(2) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */ 0x1d0 (A_DELAY(266) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */ 0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */ 0x1e8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */ 0x1f4 (A_DELAY(43) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */ 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */ 0x368 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */ 0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */ 0x1a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */ 0x1b4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */ 0x1c0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */ 0x1d8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */ 0x1e4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */ 0x1f0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */ 0x1fc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */ 0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */ >; }; }; &mmc1 { pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; pinctrl-0 = <&mmc1_pins_default>; pinctrl-1 = <&mmc1_pins_hs>; pinctrl-2 = <&mmc1_pins_sdr12>; pinctrl-3 = <&mmc1_pins_sdr25>; pinctrl-4 = <&mmc1_pins_sdr50>; pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>; pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_conf>; }; &mmc2 { pinctrl-names = "default", "hs", "ddr_1_8v"; pinctrl-0 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_conf>; }; &oppdm_mpu { vdd-supply = <&smps12_reg>; }; &oppdm_dspeve { vdd-supply = <&smps45_reg>; }; &oppdm_gpu { vdd-supply = <&smps6_reg>; }; &oppdm_ivahd { vdd-supply = <&smps45_reg>; }; &oppdm_core { vdd-supply = <&smps7_reg>; }; &mailbox5 { status = "okay"; mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { status = "okay"; }; mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { status = "okay"; }; }; &mmu0_dsp1 { status = "okay"; }; &mmu1_dsp1 { status = "okay"; }; &mmu_ipu1 { status = "okay"; }; &mmu_ipu2 { status = "okay"; }; &ipu2 { status = "okay"; memory-region = <&ipu2_cma_pool>; mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; timers = <&timer3>; watchdog-timers = <&timer4>, <&timer9>; }; &ipu1 { status = "okay"; memory-region = <&ipu1_cma_pool>; mboxes = <&mailbox5 &mbox_ipu1_ipc3x>; timers = <&timer11>; }; &dsp1 { status = "okay"; memory-region = <&dsp1_cma_pool>; mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; timers = <&timer5>; }; &ov2659_1 { remote-endpoint = <&vin1b>; }; &vin1b { status = "okay"; endpoint@2 { slave-mode; remote-endpoint = <&ov2659_1>; }; }; &vip1 { status = "okay"; }; &sn65hvs882 { load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; }; &pruss1_mdio { status = "okay"; reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; reset-delay-us = <2>; /* PHY datasheet states 1uS min */ pruss1_eth0_phy: ethernet-phy@0 { reg = <0>; interrupt-parent = <&gpio3>; interrupts = <28 IRQ_TYPE_EDGE_FALLING>; }; pruss1_eth1_phy: ethernet-phy@1 { reg = <1>; interrupt-parent = <&gpio3>; interrupts = <29 IRQ_TYPE_EDGE_FALLING>; }; }; &pruss2_mdio { reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; reset-delay-us = <2>; /* PHY datasheet states 1uS min */ }; &pru1_1 { ti,pruss-gp-mux-sel = <4>; /* MII2, needed for PRUSS1_MII1 */ }; &pru2_0 { ti,pruss-gp-mux-sel = <4>; /* MII2, needed for PRUSS1_MII0 */ }; &pru2_1 { ti,pruss-gp-mux-sel = <4>; /* MII2, needed for PRUSS1_MII1 */ }; &omap_dwc3_2 { extcon = <&extcon_usb2>; }; &extcon_usb2 { id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>; };