/*
 * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include "dra72-evm-common.dtsi"
/ {
	model = "TI DRA722";

	memory {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ipu2_cma_pool: ipu2_cma@95800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95800000 0x0 0x3800000>;
			reusable;
			status = "okay";
		};

		dsp1_cma_pool: dsp1_cma@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		ipu1_cma_pool: ipu1_cma@9d000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9d000000 0x0 0x2000000>;
			reusable;
			status = "okay";
		};
	};
};

&i2c1 {
	tps65917: tps65917@58 {
		reg = <0x58>;

		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
	};
};

#include "dra72-evm-tps65917.dtsi"

&dra7_pmx_core {
	mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_hs: pinmux_mmc1_hs_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_sdr50: pinmux_mmc1_sdr50_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_clk.mmc1_clk */
			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_cmd.mmc1_cmd */
			0x35C (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat0.mmc1_dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat1.mmc1_dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat2.mmc1_dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
		pinctrl-single,pins = <
			0x354	(PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)	/* mmc1_clk.mmc1_clk */
			0x358	(PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)	/* mmc1_cmd.mmc1_cmd */
			0x35C	(PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)	/* mmc1_dat0.mmc1_dat0 */
			0x360	(PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)	/* mmc1_dat1.mmc1_dat1 */
			0x364	(PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)	/* mmc1_dat2.mmc1_dat2 */
			0x368	(PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc1_pins_sdr104: pinmux_mmc1_sdr104_pins {
		pinctrl-single,pins = <
			0x354	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_clk.mmc1_clk */
			0x358	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_cmd.mmc1_cmd */
			0x35C	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat0.mmc1_dat0 */
			0x360	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat1.mmc1_dat1 */
			0x364	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat2.mmc1_dat2 */
			0x368	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc2_pins_hs: pinmux_mmc2_hs_pins {
		pinctrl-single,pins = <
			0x08C	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a19.mmc2_dat4 */
			0x090	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a20.mmc2_dat5 */
			0x094	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a21.mmc2_dat6 */
			0x098	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a22.mmc2_dat7 */
			0x09C	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a23.mmc2_clk */
			0x0A0	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a24.mmc2_dat0 */
			0x0A4	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a25.mmc2_dat1 */
			0x0A8	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a26.mmc2_dat2 */
			0x0AC	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a27.mmc2_dat3 */
			0x0B0	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_cs1.mmc2_cmd */
		>;
	};

	mmc2_pins_ddr_1_8v: pinmux_mmc2_ddr_1_8v_pins {
		pinctrl-single,pins = <
			0x08C	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a19.mmc2_dat4 */
			0x090	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a20.mmc2_dat5 */
			0x094	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a21.mmc2_dat6 */
			0x098	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a22.mmc2_dat7 */
			0x09C	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a23.mmc2_clk */
			0x0A0	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a24.mmc2_dat0 */
			0x0A4	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a25.mmc2_dat1 */
			0x0A8	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a26.mmc2_dat2 */
			0x0AC	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a27.mmc2_dat3 */
			0x0B0	(PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_cs1.mmc2_cmd */
		>;
	};

	mmc2_pins_hs200_1_8v: pinmux_mmc2_hs200_1_8v_pins {
		pinctrl-single,pins = <
			0x08C	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)	/* gpmc_a19.mmc2_dat4 */
			0x090	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)	/* gpmc_a20.mmc2_dat5 */
			0x094	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)	/* gpmc_a21.mmc2_dat6 */
			0x098	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)	/* gpmc_a22.mmc2_dat7 */
			0x09C	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)	/* gpmc_a23.mmc2_clk */
			0x0A0	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)	/* gpmc_a24.mmc2_dat0 */
			0x0A4	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)	/* gpmc_a25.mmc2_dat1 */
			0x0A8	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)	/* gpmc_a26.mmc2_dat2 */
			0x0AC	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)	/* gpmc_a27.mmc2_dat3 */
			0x0B0	(PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)	/* gpmc_cs1.mmc2_cmd */
		>;
	};
};

&dra7_iodelay_core {

	mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
		pinctrl-single,pins = <
			0x620 (A_DELAY(560) | G_DELAY(365))	/* CFG_MMC1_CLK_OUT */
			0x62C (A_DELAY(0)   | G_DELAY(0))	/* CFG_MMC1_CMD_OUT */
			0x638 (A_DELAY(29)  | G_DELAY(0))	/* CFG_MMC1_DAT0_OUT */
			0x644 (A_DELAY(0)   | G_DELAY(0))	/* CFG_MMC1_DAT1_OUT */
			0x650 (A_DELAY(47)  | G_DELAY(0))	/* CFG_MMC1_DAT2_OUT */
			0x65C (A_DELAY(30)  | G_DELAY(0))	/* CFG_MMC1_DAT3_OUT */
			0x628 (A_DELAY(125) | G_DELAY(0))	/* CFG_MMC1_CMD_OEN */
			0x634 (A_DELAY(43)  | G_DELAY(0))	/* CFG_MMC1_DAT0_OEN */
			0x640 (A_DELAY(433) | G_DELAY(0))	/* CFG_MMC1_DAT1_OEN */
			0x64C (A_DELAY(287) | G_DELAY(0))	/* CFG_MMC1_DAT2_OEN */
			0x658 (A_DELAY(351) | G_DELAY(0))	/* CFG_MMC1_DAT3_OEN */
		>;
	};

	mmc2_iodelay_hs200_1_8v_conf: mmc2_iodelay_hs200_1_8v_conf {
		pinctrl-single,pins = <
			0x194 (A_DELAY(150) | G_DELAY(95))	/* CFG_GPMC_A19_OUT */
			0x1AC (A_DELAY(250) | G_DELAY(0))	/* CFG_GPMC_A20_OUT */
			0x1B8 (A_DELAY(125) | G_DELAY(0))	/* CFG_GPMC_A21_OUT */
			0x1C4 (A_DELAY(100) | G_DELAY(0))	/* CFG_GPMC_A22_OUT */
			0x1D0 (A_DELAY(870) | G_DELAY(415))	/* CFG_GPMC_A23_OUT */
			0x1DC (A_DELAY(30)  | G_DELAY(0))	/* CFG_GPMC_A24_OUT */
			0x1E8 (A_DELAY(200) | G_DELAY(0))	/* CFG_GPMC_A25_OUT */
			0x1F4 (A_DELAY(200) | G_DELAY(0))	/* CFG_GPMC_A26_OUT */
			0x200 (A_DELAY(0)   | G_DELAY(0))	/* CFG_GPMC_A27_OUT */
			0x368 (A_DELAY(240) | G_DELAY(0))	/* CFG_GPMC_CS1_OUT */
			0x190 (A_DELAY(695) | G_DELAY(0))	/* CFG_GPMC_A19_OEN */
			0x1A8 (A_DELAY(924) | G_DELAY(0))	/* CFG_GPMC_A20_OEN */
			0x1B4 (A_DELAY(719) | G_DELAY(0))	/* CFG_GPMC_A21_OEN */
			0x1C0 (A_DELAY(824) | G_DELAY(0))	/* CFG_GPMC_A22_OEN */
			0x1D8 (A_DELAY(877) | G_DELAY(0))	/* CFG_GPMC_A24_OEN */
			0x1E4 (A_DELAY(446) | G_DELAY(0))	/* CFG_GPMC_A25_OEN */
			0x1F0 (A_DELAY(847) | G_DELAY(0))	/* CFG_GPMC_A26_OEN */
			0x1FC (A_DELAY(586) | G_DELAY(0))	/* CFG_GPMC_A27_OEN */
			0x364 (A_DELAY(1039) | G_DELAY(0))	/* CFG_GPMC_CS1_OEN */
		>;
	};
};

&hdmi {
	vdda_video-supply = <&ldo5_reg>;
};

&pcf_gpio_21 {
	interrupt-parent = <&gpio6>;
	interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
};

&mmc1 {
	pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_hs>;
	pinctrl-2 = <&mmc1_pins_sdr12>;
	pinctrl-3 = <&mmc1_pins_sdr25>;
	pinctrl-4 = <&mmc1_pins_sdr50>;
	pinctrl-5 = <&mmc1_pins_ddr50>;
	pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_conf>;
};

&mmc2 {
	pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	pinctrl-2 = <&mmc2_pins_ddr_1_8v>;
	pinctrl-3 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_conf>;
};

&mac {
	slaves = <1>;
	mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <3>;
	phy-mode = "rgmii";
};

&ipu2 {
	status = "okay";
	memory-region = <&ipu2_cma_pool>;
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_cma_pool>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_cma_pool>;
};