Blame view

kernel/linux-rt-4.4.41/arch/mips/include/asm/octeon/cvmx-smix-defs.h 11 KB
5113f6f70   김현기   kernel add
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
  /***********************license start***************
   * Author: Cavium Networks
   *
   * Contact: support@caviumnetworks.com
   * This file is part of the OCTEON SDK
   *
   * Copyright (c) 2003-2012 Cavium Networks
   *
   * This file is free software; you can redistribute it and/or modify
   * it under the terms of the GNU General Public License, Version 2, as
   * published by the Free Software Foundation.
   *
   * This file is distributed in the hope that it will be useful, but
   * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
   * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
   * NONINFRINGEMENT.  See the GNU General Public License for more
   * details.
   *
   * You should have received a copy of the GNU General Public License
   * along with this file; if not, write to the Free Software
   * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
   * or visit http://www.gnu.org/licenses/.
   *
   * This file may also be available under a different license from Cavium.
   * Contact Cavium Networks for more information
   ***********************license end**************************************/
  
  #ifndef __CVMX_SMIX_DEFS_H__
  #define __CVMX_SMIX_DEFS_H__
  
  static inline uint64_t CVMX_SMIX_CLK(unsigned long offset)
  {
  	switch (cvmx_get_octeon_family()) {
  	case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
  		return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
  	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  		return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
  	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  		return CVMX_ADD_IO_SEG(0x0001180000003818ull) + (offset) * 128;
  	}
  	return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
  }
  
  static inline uint64_t CVMX_SMIX_CMD(unsigned long offset)
  {
  	switch (cvmx_get_octeon_family()) {
  	case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
  		return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
  	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  		return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
  	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  		return CVMX_ADD_IO_SEG(0x0001180000003800ull) + (offset) * 128;
  	}
  	return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
  }
  
  static inline uint64_t CVMX_SMIX_EN(unsigned long offset)
  {
  	switch (cvmx_get_octeon_family()) {
  	case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
  		return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
  	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  		return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
  	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  		return CVMX_ADD_IO_SEG(0x0001180000003820ull) + (offset) * 128;
  	}
  	return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
  }
  
  static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset)
  {
  	switch (cvmx_get_octeon_family()) {
  	case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
  		return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
  	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  		return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
  	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  		return CVMX_ADD_IO_SEG(0x0001180000003810ull) + (offset) * 128;
  	}
  	return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
  }
  
  static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset)
  {
  	switch (cvmx_get_octeon_family()) {
  	case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
  		return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
  	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  		return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
  	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  		return CVMX_ADD_IO_SEG(0x0001180000003808ull) + (offset) * 128;
  	}
  	return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
  }
  
  union cvmx_smix_clk {
  	uint64_t u64;
  	struct cvmx_smix_clk_s {
  #ifdef __BIG_ENDIAN_BITFIELD
  		uint64_t reserved_25_63:39;
  		uint64_t mode:1;
  		uint64_t reserved_21_23:3;
  		uint64_t sample_hi:5;
  		uint64_t sample_mode:1;
  		uint64_t reserved_14_14:1;
  		uint64_t clk_idle:1;
  		uint64_t preamble:1;
  		uint64_t sample:4;
  		uint64_t phase:8;
  #else
  		uint64_t phase:8;
  		uint64_t sample:4;
  		uint64_t preamble:1;
  		uint64_t clk_idle:1;
  		uint64_t reserved_14_14:1;
  		uint64_t sample_mode:1;
  		uint64_t sample_hi:5;
  		uint64_t reserved_21_23:3;
  		uint64_t mode:1;
  		uint64_t reserved_25_63:39;
  #endif
  	} s;
  	struct cvmx_smix_clk_cn30xx {
  #ifdef __BIG_ENDIAN_BITFIELD
  		uint64_t reserved_21_63:43;
  		uint64_t sample_hi:5;
  		uint64_t sample_mode:1;
  		uint64_t reserved_14_14:1;
  		uint64_t clk_idle:1;
  		uint64_t preamble:1;
  		uint64_t sample:4;
  		uint64_t phase:8;
  #else
  		uint64_t phase:8;
  		uint64_t sample:4;
  		uint64_t preamble:1;
  		uint64_t clk_idle:1;
  		uint64_t reserved_14_14:1;
  		uint64_t sample_mode:1;
  		uint64_t sample_hi:5;
  		uint64_t reserved_21_63:43;
  #endif
  	} cn30xx;
  	struct cvmx_smix_clk_cn30xx cn31xx;
  	struct cvmx_smix_clk_cn30xx cn38xx;
  	struct cvmx_smix_clk_cn30xx cn38xxp2;
  	struct cvmx_smix_clk_s cn50xx;
  	struct cvmx_smix_clk_s cn52xx;
  	struct cvmx_smix_clk_s cn52xxp1;
  	struct cvmx_smix_clk_s cn56xx;
  	struct cvmx_smix_clk_s cn56xxp1;
  	struct cvmx_smix_clk_cn30xx cn58xx;
  	struct cvmx_smix_clk_cn30xx cn58xxp1;
  	struct cvmx_smix_clk_s cn61xx;
  	struct cvmx_smix_clk_s cn63xx;
  	struct cvmx_smix_clk_s cn63xxp1;
  	struct cvmx_smix_clk_s cn66xx;
  	struct cvmx_smix_clk_s cn68xx;
  	struct cvmx_smix_clk_s cn68xxp1;
  	struct cvmx_smix_clk_s cnf71xx;
  };
  
  union cvmx_smix_cmd {
  	uint64_t u64;
  	struct cvmx_smix_cmd_s {
  #ifdef __BIG_ENDIAN_BITFIELD
  		uint64_t reserved_18_63:46;
  		uint64_t phy_op:2;
  		uint64_t reserved_13_15:3;
  		uint64_t phy_adr:5;
  		uint64_t reserved_5_7:3;
  		uint64_t reg_adr:5;
  #else
  		uint64_t reg_adr:5;
  		uint64_t reserved_5_7:3;
  		uint64_t phy_adr:5;
  		uint64_t reserved_13_15:3;
  		uint64_t phy_op:2;
  		uint64_t reserved_18_63:46;
  #endif
  	} s;
  	struct cvmx_smix_cmd_cn30xx {
  #ifdef __BIG_ENDIAN_BITFIELD
  		uint64_t reserved_17_63:47;
  		uint64_t phy_op:1;
  		uint64_t reserved_13_15:3;
  		uint64_t phy_adr:5;
  		uint64_t reserved_5_7:3;
  		uint64_t reg_adr:5;
  #else
  		uint64_t reg_adr:5;
  		uint64_t reserved_5_7:3;
  		uint64_t phy_adr:5;
  		uint64_t reserved_13_15:3;
  		uint64_t phy_op:1;
  		uint64_t reserved_17_63:47;
  #endif
  	} cn30xx;
  	struct cvmx_smix_cmd_cn30xx cn31xx;
  	struct cvmx_smix_cmd_cn30xx cn38xx;
  	struct cvmx_smix_cmd_cn30xx cn38xxp2;
  	struct cvmx_smix_cmd_s cn50xx;
  	struct cvmx_smix_cmd_s cn52xx;
  	struct cvmx_smix_cmd_s cn52xxp1;
  	struct cvmx_smix_cmd_s cn56xx;
  	struct cvmx_smix_cmd_s cn56xxp1;
  	struct cvmx_smix_cmd_cn30xx cn58xx;
  	struct cvmx_smix_cmd_cn30xx cn58xxp1;
  	struct cvmx_smix_cmd_s cn61xx;
  	struct cvmx_smix_cmd_s cn63xx;
  	struct cvmx_smix_cmd_s cn63xxp1;
  	struct cvmx_smix_cmd_s cn66xx;
  	struct cvmx_smix_cmd_s cn68xx;
  	struct cvmx_smix_cmd_s cn68xxp1;
  	struct cvmx_smix_cmd_s cnf71xx;
  };
  
  union cvmx_smix_en {
  	uint64_t u64;
  	struct cvmx_smix_en_s {
  #ifdef __BIG_ENDIAN_BITFIELD
  		uint64_t reserved_1_63:63;
  		uint64_t en:1;
  #else
  		uint64_t en:1;
  		uint64_t reserved_1_63:63;
  #endif
  	} s;
  	struct cvmx_smix_en_s cn30xx;
  	struct cvmx_smix_en_s cn31xx;
  	struct cvmx_smix_en_s cn38xx;
  	struct cvmx_smix_en_s cn38xxp2;
  	struct cvmx_smix_en_s cn50xx;
  	struct cvmx_smix_en_s cn52xx;
  	struct cvmx_smix_en_s cn52xxp1;
  	struct cvmx_smix_en_s cn56xx;
  	struct cvmx_smix_en_s cn56xxp1;
  	struct cvmx_smix_en_s cn58xx;
  	struct cvmx_smix_en_s cn58xxp1;
  	struct cvmx_smix_en_s cn61xx;
  	struct cvmx_smix_en_s cn63xx;
  	struct cvmx_smix_en_s cn63xxp1;
  	struct cvmx_smix_en_s cn66xx;
  	struct cvmx_smix_en_s cn68xx;
  	struct cvmx_smix_en_s cn68xxp1;
  	struct cvmx_smix_en_s cnf71xx;
  };
  
  union cvmx_smix_rd_dat {
  	uint64_t u64;
  	struct cvmx_smix_rd_dat_s {
  #ifdef __BIG_ENDIAN_BITFIELD
  		uint64_t reserved_18_63:46;
  		uint64_t pending:1;
  		uint64_t val:1;
  		uint64_t dat:16;
  #else
  		uint64_t dat:16;
  		uint64_t val:1;
  		uint64_t pending:1;
  		uint64_t reserved_18_63:46;
  #endif
  	} s;
  	struct cvmx_smix_rd_dat_s cn30xx;
  	struct cvmx_smix_rd_dat_s cn31xx;
  	struct cvmx_smix_rd_dat_s cn38xx;
  	struct cvmx_smix_rd_dat_s cn38xxp2;
  	struct cvmx_smix_rd_dat_s cn50xx;
  	struct cvmx_smix_rd_dat_s cn52xx;
  	struct cvmx_smix_rd_dat_s cn52xxp1;
  	struct cvmx_smix_rd_dat_s cn56xx;
  	struct cvmx_smix_rd_dat_s cn56xxp1;
  	struct cvmx_smix_rd_dat_s cn58xx;
  	struct cvmx_smix_rd_dat_s cn58xxp1;
  	struct cvmx_smix_rd_dat_s cn61xx;
  	struct cvmx_smix_rd_dat_s cn63xx;
  	struct cvmx_smix_rd_dat_s cn63xxp1;
  	struct cvmx_smix_rd_dat_s cn66xx;
  	struct cvmx_smix_rd_dat_s cn68xx;
  	struct cvmx_smix_rd_dat_s cn68xxp1;
  	struct cvmx_smix_rd_dat_s cnf71xx;
  };
  
  union cvmx_smix_wr_dat {
  	uint64_t u64;
  	struct cvmx_smix_wr_dat_s {
  #ifdef __BIG_ENDIAN_BITFIELD
  		uint64_t reserved_18_63:46;
  		uint64_t pending:1;
  		uint64_t val:1;
  		uint64_t dat:16;
  #else
  		uint64_t dat:16;
  		uint64_t val:1;
  		uint64_t pending:1;
  		uint64_t reserved_18_63:46;
  #endif
  	} s;
  	struct cvmx_smix_wr_dat_s cn30xx;
  	struct cvmx_smix_wr_dat_s cn31xx;
  	struct cvmx_smix_wr_dat_s cn38xx;
  	struct cvmx_smix_wr_dat_s cn38xxp2;
  	struct cvmx_smix_wr_dat_s cn50xx;
  	struct cvmx_smix_wr_dat_s cn52xx;
  	struct cvmx_smix_wr_dat_s cn52xxp1;
  	struct cvmx_smix_wr_dat_s cn56xx;
  	struct cvmx_smix_wr_dat_s cn56xxp1;
  	struct cvmx_smix_wr_dat_s cn58xx;
  	struct cvmx_smix_wr_dat_s cn58xxp1;
  	struct cvmx_smix_wr_dat_s cn61xx;
  	struct cvmx_smix_wr_dat_s cn63xx;
  	struct cvmx_smix_wr_dat_s cn63xxp1;
  	struct cvmx_smix_wr_dat_s cn66xx;
  	struct cvmx_smix_wr_dat_s cn68xx;
  	struct cvmx_smix_wr_dat_s cn68xxp1;
  	struct cvmx_smix_wr_dat_s cnf71xx;
  };
  
  #endif