Blame view

kernel/linux-rt-4.4.41/arch/mips/include/asm/netlogic/mips-extns.h 8.08 KB
5113f6f70   김현기   kernel add
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
  /*
   * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
   * reserved.
   *
   * This software is available to you under a choice of one of two
   * licenses.  You may choose to be licensed under the terms of the GNU
   * General Public License (GPL) Version 2, available from the file
   * COPYING in the main directory of this source tree, or the NetLogic
   * license below:
   *
   * Redistribution and use in source and binary forms, with or without
   * modification, are permitted provided that the following conditions
   * are met:
   *
   * 1. Redistributions of source code must retain the above copyright
   *    notice, this list of conditions and the following disclaimer.
   * 2. Redistributions in binary form must reproduce the above copyright
   *    notice, this list of conditions and the following disclaimer in
   *    the documentation and/or other materials provided with the
   *    distribution.
   *
   * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
   * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
   * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
   * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
   * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
   * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   */
  
  #ifndef _ASM_NLM_MIPS_EXTS_H
  #define _ASM_NLM_MIPS_EXTS_H
  
  /*
   * XLR and XLP interrupt request and interrupt mask registers
   */
  /*
   * NOTE: Do not save/restore flags around write_c0_eimr().
   * On non-R2 platforms the flags has part of EIMR that is shadowed in STATUS
   * register. Restoring flags will overwrite the lower 8 bits of EIMR.
   *
   * Call with interrupts disabled.
   */
  #define write_c0_eimr(val)						\
  do {									\
  	if (sizeof(unsigned long) == 4) {				\
  		__asm__ __volatile__(					\
  			".set\tmips64
  \t"				\
  			"dsll\t%L0, %L0, 32
  \t"			\
  			"dsrl\t%L0, %L0, 32
  \t"			\
  			"dsll\t%M0, %M0, 32
  \t"			\
  			"or\t%L0, %L0, %M0
  \t"				\
  			"dmtc0\t%L0, $9, 7
  \t"				\
  			".set\tmips0"					\
  			: : "r" (val));					\
  	} else								\
  		__write_64bit_c0_register($9, 7, (val));		\
  } while (0)
  
  /*
   * Handling the 64 bit EIMR and EIRR registers in 32-bit mode with
   * standard functions will be very inefficient. This provides
   * optimized functions for the normal operations on the registers.
   *
   * Call with interrupts disabled.
   */
  static inline void ack_c0_eirr(int irq)
  {
  	__asm__ __volatile__(
  		".set	push
  \t"
  		".set	mips64
  \t"
  		".set	noat
  \t"
  		"li	$1, 1
  \t"
  		"dsllv	$1, $1, %0
  \t"
  		"dmtc0	$1, $9, 6
  \t"
  		".set	pop"
  		: : "r" (irq));
  }
  
  static inline void set_c0_eimr(int irq)
  {
  	__asm__ __volatile__(
  		".set	push
  \t"
  		".set	mips64
  \t"
  		".set	noat
  \t"
  		"li	$1, 1
  \t"
  		"dsllv	%0, $1, %0
  \t"
  		"dmfc0	$1, $9, 7
  \t"
  		"or	$1, %0
  \t"
  		"dmtc0	$1, $9, 7
  \t"
  		".set	pop"
  		: "+r" (irq));
  }
  
  static inline void clear_c0_eimr(int irq)
  {
  	__asm__ __volatile__(
  		".set	push
  \t"
  		".set	mips64
  \t"
  		".set	noat
  \t"
  		"li	$1, 1
  \t"
  		"dsllv	%0, $1, %0
  \t"
  		"dmfc0	$1, $9, 7
  \t"
  		"or	$1, %0
  \t"
  		"xor	$1, %0
  \t"
  		"dmtc0	$1, $9, 7
  \t"
  		".set	pop"
  		: "+r" (irq));
  }
  
  /*
   * Read c0 eimr and c0 eirr, do AND of the two values, the result is
   * the interrupts which are raised and are not masked.
   */
  static inline uint64_t read_c0_eirr_and_eimr(void)
  {
  	uint64_t val;
  
  #ifdef CONFIG_64BIT
  	val = __read_64bit_c0_register($9, 6) & __read_64bit_c0_register($9, 7);
  #else
  	__asm__ __volatile__(
  		".set	push
  \t"
  		".set	mips64
  \t"
  		".set	noat
  \t"
  		"dmfc0	%M0, $9, 6
  \t"
  		"dmfc0	%L0, $9, 7
  \t"
  		"and	%M0, %L0
  \t"
  		"dsll	%L0, %M0, 32
  \t"
  		"dsra	%M0, %M0, 32
  \t"
  		"dsra	%L0, %L0, 32
  \t"
  		".set	pop"
  		: "=r" (val));
  #endif
  	return val;
  }
  
  static inline int hard_smp_processor_id(void)
  {
  	return __read_32bit_c0_register($15, 1) & 0x3ff;
  }
  
  static inline int nlm_nodeid(void)
  {
  	uint32_t prid = read_c0_prid() & PRID_IMP_MASK;
  
  	if ((prid == PRID_IMP_NETLOGIC_XLP9XX) ||
  			(prid == PRID_IMP_NETLOGIC_XLP5XX))
  		return (__read_32bit_c0_register($15, 1) >> 7) & 0x7;
  	else
  		return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
  }
  
  static inline unsigned int nlm_core_id(void)
  {
  	uint32_t prid = read_c0_prid() & PRID_IMP_MASK;
  
  	if ((prid == PRID_IMP_NETLOGIC_XLP9XX) ||
  			(prid == PRID_IMP_NETLOGIC_XLP5XX))
  		return (read_c0_ebase() & 0x7c) >> 2;
  	else
  		return (read_c0_ebase() & 0x1c) >> 2;
  }
  
  static inline unsigned int nlm_thread_id(void)
  {
  	return read_c0_ebase() & 0x3;
  }
  
  #define __read_64bit_c2_split(source, sel)				\
  ({									\
  	unsigned long long __val;					\
  	unsigned long __flags;						\
  									\
  	local_irq_save(__flags);					\
  	if (sel == 0)							\
  		__asm__ __volatile__(					\
  			".set\tmips64
  \t"				\
  			"dmfc2\t%M0, " #source "
  \t"			\
  			"dsll\t%L0, %M0, 32
  \t"			\
  			"dsra\t%M0, %M0, 32
  \t"			\
  			"dsra\t%L0, %L0, 32
  \t"			\
  			".set\tmips0
  \t"				\
  			: "=r" (__val));				\
  	else								\
  		__asm__ __volatile__(					\
  			".set\tmips64
  \t"				\
  			"dmfc2\t%M0, " #source ", " #sel "
  \t"		\
  			"dsll\t%L0, %M0, 32
  \t"			\
  			"dsra\t%M0, %M0, 32
  \t"			\
  			"dsra\t%L0, %L0, 32
  \t"			\
  			".set\tmips0
  \t"				\
  			: "=r" (__val));				\
  	local_irq_restore(__flags);					\
  									\
  	__val;								\
  })
  
  #define __write_64bit_c2_split(source, sel, val)			\
  do {									\
  	unsigned long __flags;						\
  									\
  	local_irq_save(__flags);					\
  	if (sel == 0)							\
  		__asm__ __volatile__(					\
  			".set\tmips64
  \t"				\
  			"dsll\t%L0, %L0, 32
  \t"			\
  			"dsrl\t%L0, %L0, 32
  \t"			\
  			"dsll\t%M0, %M0, 32
  \t"			\
  			"or\t%L0, %L0, %M0
  \t"				\
  			"dmtc2\t%L0, " #source "
  \t"			\
  			".set\tmips0
  \t"				\
  			: : "r" (val));					\
  	else								\
  		__asm__ __volatile__(					\
  			".set\tmips64
  \t"				\
  			"dsll\t%L0, %L0, 32
  \t"			\
  			"dsrl\t%L0, %L0, 32
  \t"			\
  			"dsll\t%M0, %M0, 32
  \t"			\
  			"or\t%L0, %L0, %M0
  \t"				\
  			"dmtc2\t%L0, " #source ", " #sel "
  \t"		\
  			".set\tmips0
  \t"				\
  			: : "r" (val));					\
  	local_irq_restore(__flags);					\
  } while (0)
  
  #define __read_32bit_c2_register(source, sel)				\
  ({ uint32_t __res;							\
  	if (sel == 0)							\
  		__asm__ __volatile__(					\
  			".set\tmips32
  \t"				\
  			"mfc2\t%0, " #source "
  \t"			\
  			".set\tmips0
  \t"				\
  			: "=r" (__res));				\
  	else								\
  		__asm__ __volatile__(					\
  			".set\tmips32
  \t"				\
  			"mfc2\t%0, " #source ", " #sel "
  \t"		\
  			".set\tmips0
  \t"				\
  			: "=r" (__res));				\
  	__res;								\
  })
  
  #define __read_64bit_c2_register(source, sel)				\
  ({ unsigned long long __res;						\
  	if (sizeof(unsigned long) == 4)					\
  		__res = __read_64bit_c2_split(source, sel);		\
  	else if (sel == 0)						\
  		__asm__ __volatile__(					\
  			".set\tmips64
  \t"				\
  			"dmfc2\t%0, " #source "
  \t"			\
  			".set\tmips0
  \t"				\
  			: "=r" (__res));				\
  	else								\
  		__asm__ __volatile__(					\
  			".set\tmips64
  \t"				\
  			"dmfc2\t%0, " #source ", " #sel "
  \t"		\
  			".set\tmips0
  \t"				\
  			: "=r" (__res));				\
  	__res;								\
  })
  
  #define __write_64bit_c2_register(register, sel, value)			\
  do {									\
  	if (sizeof(unsigned long) == 4)					\
  		__write_64bit_c2_split(register, sel, value);		\
  	else if (sel == 0)						\
  		__asm__ __volatile__(					\
  			".set\tmips64
  \t"				\
  			"dmtc2\t%z0, " #register "
  \t"			\
  			".set\tmips0
  \t"				\
  			: : "Jr" (value));				\
  	else								\
  		__asm__ __volatile__(					\
  			".set\tmips64
  \t"				\
  			"dmtc2\t%z0, " #register ", " #sel "
  \t"	\
  			".set\tmips0
  \t"				\
  			: : "Jr" (value));				\
  } while (0)
  
  #define __write_32bit_c2_register(reg, sel, value)			\
  ({									\
  	if (sel == 0)							\
  		__asm__ __volatile__(					\
  			".set\tmips32
  \t"				\
  			"mtc2\t%z0, " #reg "
  \t"			\
  			".set\tmips0
  \t"				\
  			: : "Jr" (value));				\
  	else								\
  		__asm__ __volatile__(					\
  			".set\tmips32
  \t"				\
  			"mtc2\t%z0, " #reg ", " #sel "
  \t"		\
  			".set\tmips0
  \t"				\
  			: : "Jr" (value));				\
  })
  
  #endif /*_ASM_NLM_MIPS_EXTS_H */