Blame view

kernel/linux-rt-4.4.41/arch/powerpc/include/asm/ps3gpu.h 2.44 KB
5113f6f70   김현기   kernel add
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
  /*
   *  PS3 GPU declarations.
   *
   *  Copyright 2009 Sony Corporation
   *
   *  This program is free software; you can redistribute it and/or modify
   *  it under the terms of the GNU General Public License as published by
   *  the Free Software Foundation; version 2 of the License.
   *
   *  This program is distributed in the hope that it will be useful,
   *  but WITHOUT ANY WARRANTY; without even the implied warranty of
   *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   *  GNU General Public License for more details.
   *
   *  You should have received a copy of the GNU General Public License
   *  along with this program.
   *  If not, see <http://www.gnu.org/licenses/>.
   */
  
  #ifndef _ASM_POWERPC_PS3GPU_H
  #define _ASM_POWERPC_PS3GPU_H
  
  #include <linux/mutex.h>
  
  #include <asm/lv1call.h>
  
  
  #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC	0x101
  #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP	0x102
  
  #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP	0x600
  #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT		0x601
  #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC	0x602
  #define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE	0x603
  
  #define L1GPU_FB_BLIT_WAIT_FOR_COMPLETION	(1ULL << 32)
  
  #define L1GPU_DISPLAY_SYNC_HSYNC		1
  #define L1GPU_DISPLAY_SYNC_VSYNC		2
  
  
  /* mutex synchronizing GPU accesses and video mode changes */
  extern struct mutex ps3_gpu_mutex;
  
  
  static inline int lv1_gpu_display_sync(u64 context_handle, u64 head,
  				       u64 ddr_offset)
  {
  	return lv1_gpu_context_attribute(context_handle,
  					 L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC,
  					 head, ddr_offset, 0, 0);
  }
  
  static inline int lv1_gpu_display_flip(u64 context_handle, u64 head,
  				       u64 ddr_offset)
  {
  	return lv1_gpu_context_attribute(context_handle,
  					 L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP,
  					 head, ddr_offset, 0, 0);
  }
  
  static inline int lv1_gpu_fb_setup(u64 context_handle, u64 xdr_lpar,
  				   u64 xdr_size, u64 ioif_offset)
  {
  	return lv1_gpu_context_attribute(context_handle,
  					 L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP,
  					 xdr_lpar, xdr_size, ioif_offset, 0);
  }
  
  static inline int lv1_gpu_fb_blit(u64 context_handle, u64 ddr_offset,
  				  u64 ioif_offset, u64 sync_width, u64 pitch)
  {
  	return lv1_gpu_context_attribute(context_handle,
  					 L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
  					 ddr_offset, ioif_offset, sync_width,
  					 pitch);
  }
  
  static inline int lv1_gpu_fb_close(u64 context_handle)
  {
  	return lv1_gpu_context_attribute(context_handle,
  					 L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0,
  					 0, 0, 0);
  }
  
  #endif /* _ASM_POWERPC_PS3GPU_H */