5113f6f70
김현기
kernel add
|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
|
/*
* Copyright (C) 2014 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include "clk.h"
struct pistachio_clk_provider *
pistachio_clk_alloc_provider(struct device_node *node, unsigned int num_clks)
{
struct pistachio_clk_provider *p;
p = kzalloc(sizeof(*p), GFP_KERNEL);
if (!p)
return p;
p->clk_data.clks = kcalloc(num_clks, sizeof(struct clk *), GFP_KERNEL);
if (!p->clk_data.clks)
goto free_provider;
p->clk_data.clk_num = num_clks;
p->node = node;
p->base = of_iomap(node, 0);
if (!p->base) {
pr_err("Failed to map clock provider registers
");
goto free_clks;
}
return p;
free_clks:
kfree(p->clk_data.clks);
free_provider:
kfree(p);
return NULL;
}
void pistachio_clk_register_provider(struct pistachio_clk_provider *p)
{
unsigned int i;
for (i = 0; i < p->clk_data.clk_num; i++) {
if (IS_ERR(p->clk_data.clks[i]))
pr_warn("Failed to register clock %d: %ld
", i,
PTR_ERR(p->clk_data.clks[i]));
}
of_clk_add_provider(p->node, of_clk_src_onecell_get, &p->clk_data);
}
void pistachio_clk_register_gate(struct pistachio_clk_provider *p,
struct pistachio_gate *gate,
unsigned int num)
{
struct clk *clk;
unsigned int i;
for (i = 0; i < num; i++) {
clk = clk_register_gate(NULL, gate[i].name, gate[i].parent,
CLK_SET_RATE_PARENT,
p->base + gate[i].reg, gate[i].shift,
0, NULL);
p->clk_data.clks[gate[i].id] = clk;
}
}
void pistachio_clk_register_mux(struct pistachio_clk_provider *p,
struct pistachio_mux *mux,
unsigned int num)
{
struct clk *clk;
unsigned int i;
for (i = 0; i < num; i++) {
clk = clk_register_mux(NULL, mux[i].name, mux[i].parents,
mux[i].num_parents,
CLK_SET_RATE_NO_REPARENT,
p->base + mux[i].reg, mux[i].shift,
get_count_order(mux[i].num_parents),
0, NULL);
p->clk_data.clks[mux[i].id] = clk;
}
}
void pistachio_clk_register_div(struct pistachio_clk_provider *p,
struct pistachio_div *div,
unsigned int num)
{
struct clk *clk;
unsigned int i;
for (i = 0; i < num; i++) {
clk = clk_register_divider(NULL, div[i].name, div[i].parent,
0, p->base + div[i].reg, 0,
div[i].width, div[i].div_flags,
NULL);
p->clk_data.clks[div[i].id] = clk;
}
}
void pistachio_clk_register_fixed_factor(struct pistachio_clk_provider *p,
struct pistachio_fixed_factor *ff,
unsigned int num)
{
struct clk *clk;
unsigned int i;
for (i = 0; i < num; i++) {
clk = clk_register_fixed_factor(NULL, ff[i].name, ff[i].parent,
0, 1, ff[i].div);
p->clk_data.clks[ff[i].id] = clk;
}
}
void pistachio_clk_force_enable(struct pistachio_clk_provider *p,
unsigned int *clk_ids, unsigned int num)
{
unsigned int i;
int err;
for (i = 0; i < num; i++) {
struct clk *clk = p->clk_data.clks[clk_ids[i]];
if (IS_ERR(clk))
continue;
err = clk_prepare_enable(clk);
if (err)
pr_err("Failed to enable clock %s: %d
",
__clk_get_name(clk), err);
}
}
|