Blame view

kernel/linux-rt-4.4.41/arch/x86/include/asm/tsc.h 1.26 KB
5113f6f70   김현기   kernel add
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
  /*
   * x86 TSC related functions
   */
  #ifndef _ASM_X86_TSC_H
  #define _ASM_X86_TSC_H
  
  #include <asm/processor.h>
  
  #define NS_SCALE	10 /* 2^10, carefully chosen */
  #define US_SCALE	32 /* 2^32, arbitralrily chosen */
  
  /*
   * Standard way to access the cycle counter.
   */
  typedef unsigned long long cycles_t;
  
  extern unsigned int cpu_khz;
  extern unsigned int tsc_khz;
  
  extern void disable_TSC(void);
  
  static inline cycles_t get_cycles(void)
  {
  #ifndef CONFIG_X86_TSC
  	if (!cpu_has_tsc)
  		return 0;
  #endif
  
  	return rdtsc();
  }
  
  extern void tsc_init(void);
  extern void mark_tsc_unstable(char *reason);
  extern int unsynchronized_tsc(void);
  extern int check_tsc_unstable(void);
  extern int check_tsc_disabled(void);
  extern unsigned long native_calibrate_tsc(void);
  extern unsigned long long native_sched_clock_from_tsc(u64 tsc);
  
  extern int tsc_clocksource_reliable;
  
  /*
   * Boot-time check whether the TSCs are synchronized across
   * all CPUs/cores:
   */
  extern void check_tsc_sync_source(int cpu);
  extern void check_tsc_sync_target(void);
  
  extern int notsc_setup(char *);
  extern void tsc_save_sched_clock_state(void);
  extern void tsc_restore_sched_clock_state(void);
  
  /* MSR based TSC calibration for Intel Atom SoC platforms */
  unsigned long try_msr_calibrate_tsc(void);
  
  #endif /* _ASM_X86_TSC_H */