/*
   * (C) Copyright 2014
   * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   *
   * Based on:
   * Copyright (C) 2012 Freescale Semiconductor, Inc.
   *
   * Author: Fabio Estevam <fabio.estevam@freescale.com>
   *
   * SPDX-License-Identifier:	GPL-2.0+
   */
  
  #include <asm/arch/clock.h>
  #include <asm/arch/imx-regs.h>
  #include <asm/arch/iomux.h>
  #include <asm/arch/mx6-pins.h>
  #include <asm/errno.h>
  #include <asm/gpio.h>
  #include <asm/imx-common/iomux-v3.h>
  #include <asm/imx-common/boot_mode.h>
  #include <asm/imx-common/mxc_i2c.h>
  #include <asm/imx-common/video.h>
  #include <mmc.h>
  #include <fsl_esdhc.h>
  #include <miiphy.h>
  #include <netdev.h>
  #include <asm/arch/mxc_hdmi.h>
  #include <asm/arch/crm_regs.h>
  #include <linux/fb.h>
  #include <ipu_pixfmt.h>
  #include <asm/io.h>
  #include <asm/arch/sys_proto.h>
  #include <pwm.h>
  
  DECLARE_GLOBAL_DATA_PTR;
  
  #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
  	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
  	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  
  #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
  	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
  	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  
  #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
  	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  
  #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  
  #define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
  	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
  	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  
  #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  
  #define DISP_PAD_CTRL	(0x10)
  
  #define ECSPI4_CS1		IMX_GPIO_NR(5, 2)
  
  struct i2c_pads_info i2c_pad_info1 = {
  	.scl = {
  		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
  		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
  		.gp = IMX_GPIO_NR(5, 27)
  	},
  	.sda = {
  		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
  		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
  		.gp = IMX_GPIO_NR(5, 26)
  	}
  };
  
  struct i2c_pads_info i2c_pad_info2 = {
  	.scl = {
  		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
  		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
  		.gp = IMX_GPIO_NR(4, 12)
  	},
  	.sda = {
  		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
  		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  		.gp = IMX_GPIO_NR(4, 13)
  	}
  };
  
  struct i2c_pads_info i2c_pad_info3 = {
  	.scl = {
  		.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
  		.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
  		.gp = IMX_GPIO_NR(3, 17)
  	},
  	.sda = {
  		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
  		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
  		.gp = IMX_GPIO_NR(3, 18)
  	}
  };
  
  int dram_init(void)
  {
  	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  
  	return 0;
  }
  
  iomux_v3_cfg_t const uart1_pads[] = {
  	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  };
  
  iomux_v3_cfg_t const uart5_pads[] = {
  	MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  	MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  };
  
  iomux_v3_cfg_t const gpio_pads[] = {
  	/* LED enable */
  	MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
  	/* spi flash WP protect */
  	MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  	/* backlight enable */
  	MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  	/* LED yellow */
  	MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
  	/* LED red */
  	MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  	/* LED green */
  	MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  	/* LED blue */
  	MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
  	/* i2c4 scl */
  	MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  	/* i2c4 sda */
  	MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  	/* spi CS 1 */
  	MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  };
  
  static iomux_v3_cfg_t const misc_pads[] = {
  	MX6_PAD_GPIO_1__USB_OTG_ID		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	/* OTG Power enable */
  	MX6_PAD_EIM_D31__GPIO3_IO31		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_KEY_ROW4__GPIO4_IO15		| MUX_PAD_CTRL(NO_PAD_CTRL),
  };
  
  iomux_v3_cfg_t const enet_pads[] = {
  	MX6_PAD_GPIO_16__ENET_REF_CLK	| MUX_PAD_CTRL(0x4001b0a8),
  	MX6_PAD_ENET_MDIO__ENET_MDIO	| MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_ENET_MDC__ENET_MDC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_ENET_TX_EN__ENET_TX_EN	| MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_ENET_RX_ER__ENET_RX_ER	| MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_ENET_CRS_DV__ENET_RX_EN	| MUX_PAD_CTRL(ENET_PAD_CTRL),
  };
  
  static void setup_iomux_enet(void)
  {
  	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  
  	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  
  	/* set GPIO_16 as ENET_REF_CLK_OUT */
  	setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
  }
  
  iomux_v3_cfg_t const usdhc1_pads[] = {
  	MX6_PAD_SD1_CLK__SD1_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD1_CMD__SD1_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD1_DAT0__SD1_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD1_DAT1__SD1_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD1_DAT2__SD1_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD1_DAT3__SD1_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
  };
  
  iomux_v3_cfg_t const usdhc2_pads[] = {
  	MX6_PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
  };
  
  iomux_v3_cfg_t const ecspi4_pads[] = {
  	MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
  };
  
  static iomux_v3_cfg_t const display_pads[] = {
  	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
  	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
  	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
  	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
  	MX6_PAD_DI0_PIN4__GPIO4_IO20,
  	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
  	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
  	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
  	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
  	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
  	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
  	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
  	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
  	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
  	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
  	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
  	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
  	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
  	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
  	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
  	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
  	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
  	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
  	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
  	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
  	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
  	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
  	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
  	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
  };
  
  static iomux_v3_cfg_t const backlight_pads[] = {
  	MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  };
  
  int board_spi_cs_gpio(unsigned bus, unsigned cs)
  {
  	return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
  		? (IMX_GPIO_NR(3, 20)) : -1;
  }
  
  static void setup_spi(void)
  {
  	int i;
  
  	imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
  	for (i = 0; i < 3; i++)
  		enable_spi_clk(true, i);
  
  	/* set cs1 to high */
  	gpio_direction_output(ECSPI4_CS1, 1);
  }
  
  static void setup_iomux_gpio(void)
  {
  	imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
  }
  
  static void setup_iomux_uart(void)
  {
  	imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
  }
  
  #ifdef CONFIG_FSL_ESDHC
  struct fsl_esdhc_cfg usdhc_cfg[2] = {
  	{USDHC1_BASE_ADDR},
  	{USDHC2_BASE_ADDR},
  };
  
  int board_mmc_getcd(struct mmc *mmc)
  {
  	return 1;
  }
  
  int board_mmc_init(bd_t *bis)
  {
  	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  
  	imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  
  	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |
  		fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
  }
  #endif
  
  /*
   * Do not overwrite the console
   * Use always serial for U-Boot console
   */
  int overwrite_console(void)
  {
  	return 1;
  }
  
  int board_eth_init(bd_t *bis)
  {
  	struct iomuxc *iomuxc_regs =
  				(struct iomuxc *)IOMUXC_BASE_ADDR;
  	int ret;
  
  	setup_iomux_enet();
  	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
  	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
  
  	ret = enable_fec_anatop_clock(ENET_50MHZ);
  	if (ret)
  		return ret;
  
  	return cpu_eth_init(bis);
  }
  #if defined(CONFIG_VIDEO_IPUV3)
  
  static void enable_lvds(struct display_info_t const *dev)
  {
  	imx_iomux_v3_setup_multiple_pads(
  		display_pads,
  		 ARRAY_SIZE(display_pads));
  	imx_iomux_v3_setup_multiple_pads(
  		backlight_pads,
  		 ARRAY_SIZE(backlight_pads));
  
  	/* enable backlight PWM 3 */
  	if (pwm_init(2, 0, 0))
  		goto error;
  	/* duty cycle 500ns, period: 3000ns */
  	if (pwm_config(2, 500, 3000))
  		goto error;
  	if (pwm_enable(2))
  		goto error;
  	return;
  
  error:
  	puts("error init pwm for backlight
  ");
  	return;
  }
  
  struct display_info_t const displays[] = {
  	{
  		.bus	= -1,
  		.addr	= 0,
  		.pixfmt	= IPU_PIX_FMT_RGB24,
  		.detect	= NULL,
  		.enable	= enable_lvds,
  		.mode	= {
  			.name           = "lb07wv8",
  			.refresh        = 60,
  			.xres           = 800,
  			.yres           = 480,
  			.pixclock       = 33246,
  			.left_margin    = 88,
  			.right_margin   = 88,
  			.upper_margin   = 10,
  			.lower_margin   = 10,
  			.hsync_len      = 80,
  			.vsync_len      = 25,
  			.sync           = 0,
  			.vmode          = FB_VMODE_NONINTERLACED
  		}
  	}
  };
  size_t display_count = ARRAY_SIZE(displays);
  
  static void setup_display(void)
  {
  	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  	int reg;
  
  	enable_ipu_clock();
  
  	reg = readl(&mxc_ccm->cs2cdr);
  	/* select pll 5 clock */
  	reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
  	reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
  	writel(reg, &mxc_ccm->cs2cdr);
  
  	imx_iomux_v3_setup_multiple_pads(backlight_pads,
  					 ARRAY_SIZE(backlight_pads));
  }
  
  /* no console on this board */
  int board_cfb_skip(void)
  {
  	return 1;
  }
  #endif
  
  int board_early_init_f(void)
  {
  	setup_iomux_uart();
  	setup_iomux_gpio();
  
  #if defined(CONFIG_VIDEO_IPUV3)
  	setup_display();
  #endif
  	return 0;
  }
  
  iomux_v3_cfg_t nfc_pads[] = {
  	MX6_PAD_NANDF_CLE__NAND_CLE		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_NANDF_ALE__NAND_ALE		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_NANDF_WP_B__NAND_WP_B	| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_NANDF_RB0__NAND_READY_B	| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_NANDF_CS0__NAND_CE0_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_NANDF_CS1__NAND_CE1_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_NANDF_CS2__NAND_CE2_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_NANDF_CS3__NAND_CE3_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_SD4_CMD__NAND_RE_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_SD4_CLK__NAND_WE_B		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_NANDF_D0__NAND_DATA00		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_NANDF_D1__NAND_DATA01		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_NANDF_D2__NAND_DATA02		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_NANDF_D3__NAND_DATA03		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_NANDF_D4__NAND_DATA04		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_NANDF_D5__NAND_DATA05		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_NANDF_D6__NAND_DATA06		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_NANDF_D7__NAND_DATA07		| MUX_PAD_CTRL(NO_PAD_CTRL),
  	MX6_PAD_SD4_DAT0__NAND_DQS		| MUX_PAD_CTRL(NO_PAD_CTRL),
  };
  
  static void setup_gpmi_nand(void)
  {
  	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  
  	/* config gpmi nand iomux */
  	imx_iomux_v3_setup_multiple_pads(nfc_pads,
  					 ARRAY_SIZE(nfc_pads));
  
  	/* config gpmi and bch clock to 100 MHz */
  	clrsetbits_le32(&mxc_ccm->cs2cdr,
  			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  
  	/* enable gpmi and bch clock gating */
  	setbits_le32(&mxc_ccm->CCGR4,
  		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  
  	/* enable apbh clock gating */
  	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  }
  
  int board_init(void)
  {
  	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  
  	/* address of boot parameters */
  	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  
  	setup_spi();
  
  	setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
  		  &i2c_pad_info1);
  	setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
  		  &i2c_pad_info2);
  	setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
  		  &i2c_pad_info3);
  
  	/* i2c4 not used, set it to gpio input */
  	gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl");
  	gpio_direction_input(IMX_GPIO_NR(1, 7));
  	gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda");
  	gpio_direction_input(IMX_GPIO_NR(1, 8));
  
  	/* SPI NOR Flash read only */
  	gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
  	gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
  	gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
  
  	/* enable LED */
  	gpio_request(IMX_GPIO_NR(2, 13), "LED ena");
  	gpio_direction_output(IMX_GPIO_NR(2, 13), 0);
  
  	gpio_request(IMX_GPIO_NR(1, 3), "LED yellow");
  	gpio_direction_output(IMX_GPIO_NR(1, 3), 1);
  	gpio_request(IMX_GPIO_NR(1, 4), "LED red");
  	gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
  	gpio_request(IMX_GPIO_NR(1, 5), "LED green");
  	gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
  	gpio_request(IMX_GPIO_NR(1, 6), "LED blue");
  	gpio_direction_output(IMX_GPIO_NR(1, 6), 1);
  
  	setup_gpmi_nand();
  
  	/* GPIO_1 for USB_OTG_ID */
  	setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK);
  	imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
  
  	return 0;
  }
  
  int checkboard(void)
  {
  	puts("Board: aristaitenos
  ");
  	return 0;
  }
  
  #ifdef CONFIG_USB_EHCI_MX6
  int board_ehci_hcd_init(int port)
  {
  	int ret;
  
  	ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr");
  	if (!ret)
  		gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1);
  	ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr");
  	if (!ret)
  		gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1);
  	return 0;
  }
  
  int board_ehci_power(int port, int on)
  {
  	if (port)
  		gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on);
  	else
  		gpio_set_value(ARISTAINETOS_USB_H1_PWR, on);
  	return 0;
  }
  #endif