6b13f685e
김민수
BSP 최초 추가
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#ifndef __CONFIG_BF537_PNAV_H__
#define __CONFIG_BF537_PNAV_H__
#include <asm/config-pre.h>
#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
#define CONFIG_CLKIN_HZ 24576000
#define CONFIG_CLKIN_HALF 0
#define CONFIG_PLL_BYPASS 0
#define CONFIG_VCO_MULT 20
#define CONFIG_CCLK_DIV 1
#define CONFIG_SCLK_DIV 4
#define CONFIG_MEM_ADD_WDTH 10
#define CONFIG_MEM_SIZE 64
#define CONFIG_EBIU_SDRRC_VAL 0x3b7
#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
#define CONFIG_EBIU_AMGCTL_VAL 0xFF
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC
#define CONFIG_RMII
#endif
#define CONFIG_HOSTNAME bf537-pnav
#define CONFIG_LIB_RAND
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 71
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x4000
#else
#define ENV_IS_EMBEDDED
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR 0x20004000
#define CONFIG_ENV_OFFSET 0x4000
#endif
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_SECT_SIZE 0x2000
#ifdef ENV_IS_EMBEDDED
# define LDS_BOARD_TEXT \
arch/blackfin/lib/built-in.o (.text*); \
arch/blackfin/cpu/built-in.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
#define CONFIG_NAND_PLAT
#define CONFIG_SYS_NAND_BASE 0x20100000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
#define BFIN_NAND_WRITE(addr, cmd) \
do { \
bfin_write8(addr, cmd); \
SSYNC(); \
} while (0)
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
#define CONFIG_BAUDRATE 115200
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
#define CONFIG_SYS_JFFS2_FIRST_BANK 0
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
#define CONFIG_BOOTCOMMAND "run nandboot"
#define CONFIG_BOOTARGS_ROOT "/dev/mtdblock1 rw rootfstype=yaffs"
#include <configs/bfin_adi_common.h>
#endif
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