CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP isin little-endian mode. CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP isin big-endian mode. CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V. Accessing ESDHC registers can be determined by ESDHC IP's endianmodeor processor's endian mode.
BSP 최초 추가