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bootloader/u-boot_2015_04/board/vpac270/vpac270.c 2.36 KB
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  /*
   * Voipac PXA270 Support
   *
   * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   *
   * SPDX-License-Identifier:	GPL-2.0+
   */
  
  #include <common.h>
  #include <asm/arch/hardware.h>
  #include <asm/arch/regs-mmc.h>
  #include <asm/arch/pxa.h>
  #include <netdev.h>
  #include <serial.h>
  #include <asm/io.h>
  #include <usb.h>
  
  DECLARE_GLOBAL_DATA_PTR;
  
  /*
   * Miscelaneous platform dependent initialisations
   */
  int board_init(void)
  {
  	/* We have RAM, disable cache */
  	dcache_disable();
  	icache_disable();
  
  	/* memory and cpu-speed are setup before relocation */
  	/* so we do _nothing_ here */
  
  	/* Arch number of vpac270 */
  	gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
  
  	/* adress of boot parameters */
  	gd->bd->bi_boot_params = 0xa0000100;
  
  	return 0;
  }
  
  int dram_init(void)
  {
  #ifndef	CONFIG_ONENAND
  	pxa2xx_dram_init();
  #endif
  	gd->ram_size = PHYS_SDRAM_1_SIZE;
  	return 0;
  }
  
  void dram_init_banksize(void)
  {
  	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  
  #ifdef	CONFIG_RAM_256M
  	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  #endif
  }
  
  #ifdef	CONFIG_CMD_MMC
  int board_mmc_init(bd_t *bis)
  {
  	pxa_mmc_register(0);
  	return 0;
  }
  #endif
  
  #ifdef	CONFIG_CMD_USB
  int board_usb_init(int index, enum usb_init_type init)
  {
  	writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
  		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
  		UHCHR);
  
  	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  
  	while (readl(UHCHR) & UHCHR_FSBIR)
  		;
  
  	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
  	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
  
  	/* Clear any OTG Pin Hold */
  	if (readl(PSSR) & PSSR_OTGPH)
  		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
  
  	writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
  	writel(readl(UHCRHDA) | 0x100, UHCRHDA);
  
  	/* Set port power control mask bits, only 3 ports. */
  	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
  
  	/* enable port 2 */
  	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
  		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
  
  	return 0;
  }
  
  int board_usb_cleanup(int index, enum usb_init_type init)
  {
  	return 0;
  }
  
  void usb_board_stop(void)
  {
  	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
  	udelay(11);
  	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
  
  	writel(readl(UHCCOMS) | 1, UHCCOMS);
  	udelay(10);
  
  	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
  
  	return;
  }
  #endif
  
  #ifdef CONFIG_DRIVER_DM9000
  int board_eth_init(bd_t *bis)
  {
  	return dm9000_initialize(bis);
  }
  #endif