6b13f685e
김민수
BSP 최초 추가
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#ifndef __FTSDMC021_H
#define __FTSDMC021_H
#ifndef __ASSEMBLY__
struct ftsdmc021 {
unsigned int tp1;
unsigned int tp2;
unsigned int cr1;
unsigned int cr2;
unsigned int bank0_bsr;
unsigned int bank1_bsr;
unsigned int bank2_bsr;
unsigned int bank3_bsr;
unsigned int bank4_bsr;
unsigned int bank5_bsr;
unsigned int bank6_bsr;
unsigned int bank7_bsr;
unsigned int ragr;
unsigned int frr;
unsigned int ebisr;
unsigned int rsved[25];
unsigned int crr;
unsigned int cfr;
};
#endif /* __ASSEMBLY__ */
#define FTSDMC021_TP1_TCL(x) ((x) & 0x3) /* CAS Latency */
#define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4) /* W-Recovery Time */
#define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8) /* Auto-Refresh Cycle */
#define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12) /* RAS-to-CAS Delay */
#define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16) /* Precharge Cycle */
#define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20)
#define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff) /* Refresh interval */
#define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16)
#define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20)
#define FTSDMC021_CR1_BNKSIZE(x) ((x) & 0xf) /* Bank Size */
#define FTSDMC021_CR1_MBW(x) (((x) & 0x3) << 4) /* Bus Width */
#define FTSDMC021_CR1_DSZ(x) (((x) & 0x7) << 8) /* SDRAM Size */
#define FTSDMC021_CR1_DDW(x) (((x) & 0x3) << 12) /* Data Width */
#define FTSDMC021_CR1_MA2T(x) (1 << 16)
#define FTSDMC021_BANK_SIZE(x) (ffs(x) - 1)
#define FTSDMC021_CR2_SREF (1 << 0) /* Self-Refresh Mode */
#define FTSDMC021_CR2_PWDN (1 << 1) /* Power Down Operation Mode */
#define FTSDMC021_CR2_ISMR (1 << 2) /* Start Set-Mode-Register */
#define FTSDMC021_CR2_IREF (1 << 3) /* Init Refresh Start Flag */
#define FTSDMC021_CR2_IPREC (1 << 4) /* Init Pre-Charge Start Flag */
#define FTSDMC021_CR2_REFTYPE (1 << 5)
#define FTSDMC021_BANK_ENABLE (1 << 12)
#define FTSDMC021_BANK_BASE(x) ((x) & 0xfff)
#define FTSDMC021_RAGR_CH1GW(x) (((x) & 0xff) << 0)
#define FTSDMC021_RAGR_CH2GW(x) (((x) & 0xff) << 4)
#define FTSDMC021_RAGR_CH3GW(x) (((x) & 0xff) << 8)
#define FTSDMC021_RAGR_CH4GW(x) (((x) & 0xff) << 12)
#define FTSDMC021_RAGR_CH5GW(x) (((x) & 0xff) << 16)
#define FTSDMC021_RAGR_CH6GW(x) (((x) & 0xff) << 20)
#define FTSDMC021_RAGR_CH7GW(x) (((x) & 0xff) << 24)
#define FTSDMC021_RAGR_CH8GW(x) (((x) & 0xff) << 28)
#define FTSDMC021_FRR_FLUSHCHN(x) (((x) & 0x7) << 0)
#define FTSDMC021_FRR_FLUSHCMPLT (1 << 3) /* Flush Req Flag */
#define FTSDMC021_EBISR_MR(x) ((x) & 0xfff) /* Far-end mode */
#define FTSDMC021_EBISR_PRSMR (1 << 12) /* Pre-SMR */
#define FTSDMC021_EBISR_POPREC (1 << 13)
#define FTSDMC021_EBISR_POSMR (1 << 14) /* Post-SMR */
#define FTSDMC021_CRR_REV_VER (((x) >> 0) & 0xff)
#define FTSDMC021_CRR_MINOR_VER (((x) >> 8) & 0xff)
#define FTSDMC021_CRR_MAJOR_VER (((x) >> 16) & 0xff)
#define FTSDMC021_CFR_EBNK (((x) >> 0) & 0xf)
#define FTSDMC021_CFR_CHN (((x) >> 8) & 0xf)
#define FTSDMC021_CFR_EBI (((x) >> 16) & 0x1)
#define FTSDMC021_CFR_CH1_FDEPTH (((x) >> 24) & 0x1)
#define FTSDMC021_CFR_CH2_FDEPTH (((x) >> 25) & 0x1)
#define FTSDMC021_CFR_CH3_FDEPTH (((x) >> 26) & 0x1)
#define FTSDMC021_CFR_CH4_FDEPTH (((x) >> 27) & 0x1)
#define FTSDMC021_CFR_CH5_FDEPTH (((x) >> 28) & 0x1)
#define FTSDMC021_CFR_CH6_FDEPTH (((x) >> 29) & 0x1)
#define FTSDMC021_CFR_CH7_FDEPTH (((x) >> 30) & 0x1)
#define FTSDMC021_CFR_CH8_FDEPTH (((x) >> 31) & 0x1)
#endif /* __FTSDMC021_H */
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