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#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
#define RTL_TIMEOUT 100000
#define ETH_FRAME_LEN 1514
#define ETH_ALEN 6
#define ETH_ZLEN 60
#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
#define TX_DMA_BURST 4 /* Calculate as 16<<val. */
#define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
#define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
#define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
#define DEBUG_TX 0 /* set to 1 to enable debug code */
#define DEBUG_RX 0 /* set to 1 to enable debug code */
#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
enum RTL8139_registers {
MAC0=0,
MAR0=8,
TxStatus0=0x10,
TxAddr0=0x20,
RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
IntrMask=0x3C, IntrStatus=0x3E,
TxConfig=0x40, RxConfig=0x44,
Timer=0x48,
RxMissed=0x4C,
Cfg9346=0x50, Config0=0x51, Config1=0x52,
TimerIntrReg=0x54,
MediaStatus=0x58,
Config3=0x59,
MultiIntr=0x5C,
RevisionID=0x5E,
TxSummary=0x60,
MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
NWayExpansion=0x6A,
DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
NWayTestReg=0x70,
RxCnt=0x72,
CSCR=0x74,
PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80,
};
enum ChipCmdBits {
CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
enum IntrStatusBits {
PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
};
enum TxStatusBits {
TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
TxOutOfWindow=0x20000000, TxAborted=0x40000000,
TxCarrierLost=0x80000000,
};
enum RxStatusBits {
RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
RxBadAlign=0x0002, RxStatusOK=0x0001,
};
enum MediaStatusBits {
MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
};
enum MIIBMCRBits {
BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
};
enum CSCRBits {
CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
CSCR_LinkDownCmd=0x0f3c0,
};
enum rx_mode_bits {
RxCfgWrap=0x80,
AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
};
static int ioaddr;
static unsigned int cur_rx,cur_tx;
static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
static int read_eeprom(int location, int addr_len);
static void rtl_reset(struct eth_device *dev);
static int rtl_transmit(struct eth_device *dev, void *packet, int length);
static int rtl_poll(struct eth_device *dev);
static void rtl_disable(struct eth_device *dev);
#ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */
static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, u8 set)
{
return (0);
}
#endif
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
{PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
{}
};
int rtl8139_initialize(bd_t *bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase;
int idx=0;
while(1){
if ((devno = pci_find_devices(supported, idx++)) < 0)
break;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0xf;
debug ("rtl8139: REALTEK RTL8139 @0x%x
", iobase);
dev = (struct eth_device *)malloc(sizeof *dev);
if (!dev) {
printf("Can not allocate memory of rtl8139
");
break;
}
memset(dev, 0, sizeof(*dev));
sprintf (dev->name, "RTL8139#%d", card_number);
dev->priv = (void *) devno;
dev->iobase = (int)bus_to_phys(iobase);
dev->init = rtl8139_probe;
dev->halt = rtl_disable;
dev->send = rtl_transmit;
dev->recv = rtl_poll;
#ifdef CONFIG_MCAST_TFTP
dev->mcast = rtl_bcast_addr;
#endif
eth_register (dev);
card_number++;
pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
udelay (10 * 1000);
}
return card_number;
}
static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
{
int i;
int addr_len;
unsigned short *ap = (unsigned short *)dev->enetaddr;
ioaddr = dev->iobase;
outb(0x00, ioaddr + Config1);
addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
for (i = 0; i < 3; i++)
*ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
rtl_reset(dev);
if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
printf("Cable not connected or other link failure
");
return -1 ;
}
return 0;
}
#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
#define EE_CS 0x08 /* EEPROM chip select. */
#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
#define EE_WRITE_0 0x00
#define EE_WRITE_1 0x02
#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
#define EE_ENB (0x80 | EE_CS)
#define eeprom_delay() inl(ee_addr)
#define EE_WRITE_CMD (5)
#define EE_READ_CMD (6)
#define EE_ERASE_CMD (7)
static int read_eeprom(int location, int addr_len)
{
int i;
unsigned int retval = 0;
long ee_addr = ioaddr + Cfg9346;
int read_cmd = location | (EE_READ_CMD << addr_len);
outb(EE_ENB & ~EE_CS, ee_addr);
outb(EE_ENB, ee_addr);
eeprom_delay();
for (i = 4 + addr_len; i >= 0; i--) {
int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
outb(EE_ENB | dataval, ee_addr);
eeprom_delay();
outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
}
outb(EE_ENB, ee_addr);
eeprom_delay();
for (i = 16; i > 0; i--) {
outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
outb(EE_ENB, ee_addr);
eeprom_delay();
}
outb(~EE_CS, ee_addr);
eeprom_delay();
return retval;
}
static const unsigned int rtl8139_rx_config =
(RX_BUF_LEN_IDX << 11) |
(RX_FIFO_THRESH << 13) |
(RX_DMA_BURST << 8);
static void set_rx_mode(struct eth_device *dev) {
unsigned int mc_filter[2];
int rx_mode;
rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
mc_filter[1] = mc_filter[0] = 0xffffffff;
outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);
outl(mc_filter[0], ioaddr + MAR0 + 0);
outl(mc_filter[1], ioaddr + MAR0 + 4);
}
static void rtl_reset(struct eth_device *dev)
{
int i;
outb(CmdReset, ioaddr + ChipCmd);
cur_rx = 0;
cur_tx = 0;
for (i=0; i<100; ++i){
if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
udelay (100);
}
for (i = 0; i < ETH_ALEN; i++)
outb(dev->enetaddr[i], ioaddr + MAC0 + i);
outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
ioaddr + RxConfig);
outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
debug_cond(DEBUG_RX,
"rx ring address is %lX
",(unsigned long)rx_ring);
flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
outl(rtl8139_rx_config, ioaddr + RxConfig);
outl(0, ioaddr + RxMissed);
set_rx_mode(dev);
outw(0, ioaddr + IntrMask);
}
static int rtl_transmit(struct eth_device *dev, void *packet, int length)
{
unsigned int status;
unsigned long txstatus;
unsigned int len = length;
int i = 0;
ioaddr = dev->iobase;
memcpy((char *)tx_buffer, (char *)packet, (int)length);
debug_cond(DEBUG_TX, "sending %d bytes
", len);
while (len < ETH_ZLEN) {
tx_buffer[len++] = '\0';
}
flush_cache((unsigned long)tx_buffer, length);
outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
ioaddr + TxStatus0 + cur_tx*4);
do {
status = inw(ioaddr + IntrStatus);
outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
udelay(10);
} while (i++ < RTL_TIMEOUT);
txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
if (status & TxOK) {
cur_tx = (cur_tx + 1) % NUM_TX_DESC;
debug_cond(DEBUG_TX,
"tx done, status %hX txstatus %lX
",
status, txstatus);
return length;
} else {
debug_cond(DEBUG_TX,
"tx timeout/error (%d usecs), status %hX txstatus %lX
",
10*i, status, txstatus);
rtl_reset(dev);
return 0;
}
}
static int rtl_poll(struct eth_device *dev)
{
unsigned int status;
unsigned int ring_offs;
unsigned int rx_size, rx_status;
int length=0;
ioaddr = dev->iobase;
if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
return 0;
}
status = inw(ioaddr + IntrStatus);
outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status);
ring_offs = cur_rx % RX_BUF_LEN;
rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
rx_size = rx_status >> 16;
rx_status &= 0xffff;
if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
(rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
printf("rx error %hX
", rx_status);
rtl_reset(dev);
return 0;
}
length = rx_size - 4;
if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
int semi_count = RX_BUF_LEN - ring_offs - 4;
unsigned char rxdata[RX_BUF_LEN];
memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
NetReceive(rxdata, length);
debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
semi_count, rx_size-4-semi_count);
} else {
NetReceive(rx_ring + ring_offs + 4, length);
debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size-4);
}
flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
outw(cur_rx - 16, ioaddr + RxBufPtr);
outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
return length;
}
static void rtl_disable(struct eth_device *dev)
{
int i;
ioaddr = dev->iobase;
outb(CmdReset, ioaddr + ChipCmd);
for (i=0; i<100; ++i){
if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
udelay (100);
}
}
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