Blame view

kernel/linux-imx6_3.14.28/drivers/clk/mxs/clk-pll.c 2.45 KB
6b13f685e   김민수   BSP 최초 추가
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
  /*
   * Copyright 2012 Freescale Semiconductor, Inc.
   *
   * The code contained herein is licensed under the GNU General Public
   * License. You may obtain a copy of the GNU General Public License
   * Version 2 or later at the following locations:
   *
   * http://www.opensource.org/licenses/gpl-license.html
   * http://www.gnu.org/copyleft/gpl.html
   */
  
  #include <linux/clk.h>
  #include <linux/clk-provider.h>
  #include <linux/delay.h>
  #include <linux/err.h>
  #include <linux/io.h>
  #include <linux/slab.h>
  #include "clk.h"
  
  /**
   * struct clk_pll - mxs pll clock
   * @hw: clk_hw for the pll
   * @base: base address of the pll
   * @power: the shift of power bit
   * @rate: the clock rate of the pll
   *
   * The mxs pll is a fixed rate clock with power and gate control,
   * and the shift of gate bit is always 31.
   */
  struct clk_pll {
  	struct clk_hw hw;
  	void __iomem *base;
  	u8 power;
  	unsigned long rate;
  };
  
  #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
  
  static int clk_pll_prepare(struct clk_hw *hw)
  {
  	struct clk_pll *pll = to_clk_pll(hw);
  
  	writel_relaxed(1 << pll->power, pll->base + SET);
  
  	udelay(10);
  
  	return 0;
  }
  
  static void clk_pll_unprepare(struct clk_hw *hw)
  {
  	struct clk_pll *pll = to_clk_pll(hw);
  
  	writel_relaxed(1 << pll->power, pll->base + CLR);
  }
  
  static int clk_pll_enable(struct clk_hw *hw)
  {
  	struct clk_pll *pll = to_clk_pll(hw);
  
  	writel_relaxed(1 << 31, pll->base + CLR);
  
  	return 0;
  }
  
  static void clk_pll_disable(struct clk_hw *hw)
  {
  	struct clk_pll *pll = to_clk_pll(hw);
  
  	writel_relaxed(1 << 31, pll->base + SET);
  }
  
  static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
  					 unsigned long parent_rate)
  {
  	struct clk_pll *pll = to_clk_pll(hw);
  
  	return pll->rate;
  }
  
  static const struct clk_ops clk_pll_ops = {
  	.prepare = clk_pll_prepare,
  	.unprepare = clk_pll_unprepare,
  	.enable = clk_pll_enable,
  	.disable = clk_pll_disable,
  	.recalc_rate = clk_pll_recalc_rate,
  };
  
  struct clk *mxs_clk_pll(const char *name, const char *parent_name,
  			void __iomem *base, u8 power, unsigned long rate)
  {
  	struct clk_pll *pll;
  	struct clk *clk;
  	struct clk_init_data init;
  
  	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  	if (!pll)
  		return ERR_PTR(-ENOMEM);
  
  	init.name = name;
  	init.ops = &clk_pll_ops;
  	init.flags = 0;
  	init.parent_names = (parent_name ? &parent_name: NULL);
  	init.num_parents = (parent_name ? 1 : 0);
  
  	pll->base = base;
  	pll->rate = rate;
  	pll->power = power;
  	pll->hw.init = &init;
  
  	clk = clk_register(NULL, &pll->hw);
  	if (IS_ERR(clk))
  		kfree(pll);
  
  	return clk;
  }