/*
   *  linux/include/linux/mtd/nand.h
   *
   *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
   *                        Steven J. Hill <sjhill@realitydiluted.com>
   *		          Thomas Gleixner <tglx@linutronix.de>
   *
   * This program is free software; you can redistribute it and/or modify
   * it under the terms of the GNU General Public License version 2 as
   * published by the Free Software Foundation.
   *
   * Info:
   *	Contains standard defines and IDs for NAND flash devices
   *
   * Changelog:
   *	See git changelog.
   */
  #ifndef __LINUX_MTD_NAND_H
  #define __LINUX_MTD_NAND_H
  
  #include <linux/wait.h>
  #include <linux/spinlock.h>
  #include <linux/mtd/mtd.h>
  #include <linux/mtd/flashchip.h>
  #include <linux/mtd/bbm.h>
  
  struct mtd_info;
  struct nand_flash_dev;
  /* Scan and identify a NAND device */
  extern int nand_scan(struct mtd_info *mtd, int max_chips);
  /*
   * Separate phases of nand_scan(), allowing board driver to intervene
   * and override command or ECC setup according to flash type.
   */
  extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  			   struct nand_flash_dev *table);
  extern int nand_scan_tail(struct mtd_info *mtd);
  
  /* Free resources held by the NAND device */
  extern void nand_release(struct mtd_info *mtd);
  
  /* Internal helper for board drivers which need to override command function */
  extern void nand_wait_ready(struct mtd_info *mtd);
  
  /* locks all blocks present in the device */
  extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  
  /* unlocks specified locked blocks */
  extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  
  /* The maximum number of NAND chips in an array */
  #define NAND_MAX_CHIPS		8
  
  /*
   * Constants for hardware specific CLE/ALE/NCE function
   *
   * These are bits which can be or'ed to set/clear multiple
   * bits in one go.
   */
  /* Select the chip by setting nCE to low */
  #define NAND_NCE		0x01
  /* Select the command latch by setting CLE to high */
  #define NAND_CLE		0x02
  /* Select the address latch by setting ALE to high */
  #define NAND_ALE		0x04
  
  #define NAND_CTRL_CLE		(NAND_NCE | NAND_CLE)
  #define NAND_CTRL_ALE		(NAND_NCE | NAND_ALE)
  #define NAND_CTRL_CHANGE	0x80
  
  /*
   * Standard NAND flash commands
   */
  #define NAND_CMD_READ0		0
  #define NAND_CMD_READ1		1
  #define NAND_CMD_RNDOUT		5
  #define NAND_CMD_PAGEPROG	0x10
  #define NAND_CMD_READOOB	0x50
  #define NAND_CMD_ERASE1		0x60
  #define NAND_CMD_STATUS		0x70
  #define NAND_CMD_SEQIN		0x80
  #define NAND_CMD_RNDIN		0x85
  #define NAND_CMD_READID		0x90
  #define NAND_CMD_ERASE2		0xd0
  #define NAND_CMD_PARAM		0xec
  #define NAND_CMD_GET_FEATURES	0xee
  #define NAND_CMD_SET_FEATURES	0xef
  #define NAND_CMD_RESET		0xff
  
  #define NAND_CMD_LOCK		0x2a
  #define NAND_CMD_UNLOCK1	0x23
  #define NAND_CMD_UNLOCK2	0x24
  
  /* Extended commands for large page devices */
  #define NAND_CMD_READSTART	0x30
  #define NAND_CMD_RNDOUTSTART	0xE0
  #define NAND_CMD_CACHEDPROG	0x15
  
  #define NAND_CMD_NONE		-1
  
  /* Status bits */
  #define NAND_STATUS_FAIL	0x01
  #define NAND_STATUS_FAIL_N1	0x02
  #define NAND_STATUS_TRUE_READY	0x20
  #define NAND_STATUS_READY	0x40
  #define NAND_STATUS_WP		0x80
  
  /*
   * Constants for ECC_MODES
   */
  typedef enum {
  	NAND_ECC_NONE,
  	NAND_ECC_SOFT,
  	NAND_ECC_HW,
  	NAND_ECC_HW_SYNDROME,
  	NAND_ECC_HW_OOB_FIRST,
  	NAND_ECC_SOFT_BCH,
  } nand_ecc_modes_t;
  
  /*
   * Constants for Hardware ECC
   */
  /* Reset Hardware ECC for read */
  #define NAND_ECC_READ		0
  /* Reset Hardware ECC for write */
  #define NAND_ECC_WRITE		1
  /* Enable Hardware ECC before syndrome is read back from flash */
  #define NAND_ECC_READSYN	2
  
  /* Bit mask for flags passed to do_nand_read_ecc */
  #define NAND_GET_DEVICE		0x80
  
  
  /*
   * Option constants for bizarre disfunctionality and real
   * features.
   */
  /* Buswidth is 16 bit */
  #define NAND_BUSWIDTH_16	0x00000002
  /* Chip has cache program function */
  #define NAND_CACHEPRG		0x00000008
  /*
   * Chip requires ready check on read (for auto-incremented sequential read).
   * True only for small page devices; large page devices do not support
   * autoincrement.
   */
  #define NAND_NEED_READRDY	0x00000100
  
  /* Chip does not allow subpage writes */
  #define NAND_NO_SUBPAGE_WRITE	0x00000200
  
  /* Device is one of 'new' xD cards that expose fake nand command set */
  #define NAND_BROKEN_XD		0x00000400
  
  /* Device behaves just like nand, but is readonly */
  #define NAND_ROM		0x00000800
  
  /* Device supports subpage reads */
  #define NAND_SUBPAGE_READ	0x00001000
  
  /* Options valid for Samsung large page devices */
  #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
  
  /* Macros to identify the above */
  #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
  #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
  
  /* Non chip related options */
  /* This option skips the bbt scan during initialization. */
  #define NAND_SKIP_BBTSCAN	0x00010000
  /*
   * This option is defined if the board driver allocates its own buffers
   * (e.g. because it needs them DMA-coherent).
   */
  #define NAND_OWN_BUFFERS	0x00020000
  /* Chip may not exist, so silence any errors in scan */
  #define NAND_SCAN_SILENT_NODEV	0x00040000
  /*
   * This option could be defined by controller drivers to protect against
   * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
   */
  #define NAND_USE_BOUNCE_BUFFER	0x00080000
  /*
   * Autodetect nand buswidth with readid/onfi.
   * This suppose the driver will configure the hardware in 8 bits mode
   * when calling nand_scan_ident, and update its configuration
   * before calling nand_scan_tail.
   */
  #define NAND_BUSWIDTH_AUTO      0x00080000
  
  /* Options set by nand scan */
  /* Nand scan has allocated controller struct */
  #define NAND_CONTROLLER_ALLOC	0x80000000
  
  /* Cell info constants */
  #define NAND_CI_CHIPNR_MSK	0x03
  #define NAND_CI_CELLTYPE_MSK	0x0C
  #define NAND_CI_CELLTYPE_SHIFT	2
  
  /* Keep gcc happy */
  struct nand_chip;
  
  /* ONFI features */
  #define ONFI_FEATURE_16_BIT_BUS		(1 << 0)
  #define ONFI_FEATURE_EXT_PARAM_PAGE	(1 << 7)
  
  /* ONFI timing mode, used in both asynchronous and synchronous mode */
  #define ONFI_TIMING_MODE_0		(1 << 0)
  #define ONFI_TIMING_MODE_1		(1 << 1)
  #define ONFI_TIMING_MODE_2		(1 << 2)
  #define ONFI_TIMING_MODE_3		(1 << 3)
  #define ONFI_TIMING_MODE_4		(1 << 4)
  #define ONFI_TIMING_MODE_5		(1 << 5)
  #define ONFI_TIMING_MODE_UNKNOWN	(1 << 6)
  
  /* ONFI feature address */
  #define ONFI_FEATURE_ADDR_TIMING_MODE	0x1
  
  /* Vendor-specific feature address (Micron) */
  #define ONFI_FEATURE_ADDR_READ_RETRY	0x89
  
  /* ONFI subfeature parameters length */
  #define ONFI_SUBFEATURE_PARAM_LEN	4
  
  /* ONFI optional commands SET/GET FEATURES supported? */
  #define ONFI_OPT_CMD_SET_GET_FEATURES	(1 << 2)
  
  struct nand_onfi_params {
  	/* rev info and features block */
  	/* 'O' 'N' 'F' 'I'  */
  	u8 sig[4];
  	__le16 revision;
  	__le16 features;
  	__le16 opt_cmd;
  	u8 reserved0[2];
  	__le16 ext_param_page_length; /* since ONFI 2.1 */
  	u8 num_of_param_pages;        /* since ONFI 2.1 */
  	u8 reserved1[17];
  
  	/* manufacturer information block */
  	char manufacturer[12];
  	char model[20];
  	u8 jedec_id;
  	__le16 date_code;
  	u8 reserved2[13];
  
  	/* memory organization block */
  	__le32 byte_per_page;
  	__le16 spare_bytes_per_page;
  	__le32 data_bytes_per_ppage;
  	__le16 spare_bytes_per_ppage;
  	__le32 pages_per_block;
  	__le32 blocks_per_lun;
  	u8 lun_count;
  	u8 addr_cycles;
  	u8 bits_per_cell;
  	__le16 bb_per_lun;
  	__le16 block_endurance;
  	u8 guaranteed_good_blocks;
  	__le16 guaranteed_block_endurance;
  	u8 programs_per_page;
  	u8 ppage_attr;
  	u8 ecc_bits;
  	u8 interleaved_bits;
  	u8 interleaved_ops;
  	u8 reserved3[13];
  
  	/* electrical parameter block */
  	u8 io_pin_capacitance_max;
  	__le16 async_timing_mode;
  	__le16 program_cache_timing_mode;
  	__le16 t_prog;
  	__le16 t_bers;
  	__le16 t_r;
  	__le16 t_ccs;
  	__le16 src_sync_timing_mode;
  	__le16 src_ssync_features;
  	__le16 clk_pin_capacitance_typ;
  	__le16 io_pin_capacitance_typ;
  	__le16 input_pin_capacitance_typ;
  	u8 input_pin_capacitance_max;
  	u8 driver_strength_support;
  	__le16 t_int_r;
  	__le16 t_ald;
  	u8 reserved4[7];
  
  	/* vendor */
  	__le16 vendor_revision;
  	u8 vendor[88];
  
  	__le16 crc;
  } __packed;
  
  #define ONFI_CRC_BASE	0x4F4E
  
  /* Extended ECC information Block Definition (since ONFI 2.1) */
  struct onfi_ext_ecc_info {
  	u8 ecc_bits;
  	u8 codeword_size;
  	__le16 bb_per_lun;
  	__le16 block_endurance;
  	u8 reserved[2];
  } __packed;
  
  #define ONFI_SECTION_TYPE_0	0	/* Unused section. */
  #define ONFI_SECTION_TYPE_1	1	/* for additional sections. */
  #define ONFI_SECTION_TYPE_2	2	/* for ECC information. */
  struct onfi_ext_section {
  	u8 type;
  	u8 length;
  } __packed;
  
  #define ONFI_EXT_SECTION_MAX 8
  
  /* Extended Parameter Page Definition (since ONFI 2.1) */
  struct onfi_ext_param_page {
  	__le16 crc;
  	u8 sig[4];             /* 'E' 'P' 'P' 'S' */
  	u8 reserved0[10];
  	struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
  
  	/*
  	 * The actual size of the Extended Parameter Page is in
  	 * @ext_param_page_length of nand_onfi_params{}.
  	 * The following are the variable length sections.
  	 * So we do not add any fields below. Please see the ONFI spec.
  	 */
  } __packed;
  
  struct nand_onfi_vendor_micron {
  	u8 two_plane_read;
  	u8 read_cache;
  	u8 read_unique_id;
  	u8 dq_imped;
  	u8 dq_imped_num_settings;
  	u8 dq_imped_feat_addr;
  	u8 rb_pulldown_strength;
  	u8 rb_pulldown_strength_feat_addr;
  	u8 rb_pulldown_strength_num_settings;
  	u8 otp_mode;
  	u8 otp_page_start;
  	u8 otp_data_prot_addr;
  	u8 otp_num_pages;
  	u8 otp_feat_addr;
  	u8 read_retry_options;
  	u8 reserved[72];
  	u8 param_revision;
  } __packed;
  
  struct jedec_ecc_info {
  	u8 ecc_bits;
  	u8 codeword_size;
  	__le16 bb_per_lun;
  	__le16 block_endurance;
  	u8 reserved[2];
  } __packed;
  
  /* JEDEC features */
  #define JEDEC_FEATURE_16_BIT_BUS	(1 << 0)
  
  struct nand_jedec_params {
  	/* rev info and features block */
  	/* 'J' 'E' 'S' 'D'  */
  	u8 sig[4];
  	__le16 revision;
  	__le16 features;
  	u8 opt_cmd[3];
  	__le16 sec_cmd;
  	u8 num_of_param_pages;
  	u8 reserved0[18];
  
  	/* manufacturer information block */
  	char manufacturer[12];
  	char model[20];
  	u8 jedec_id[6];
  	u8 reserved1[10];
  
  	/* memory organization block */
  	__le32 byte_per_page;
  	__le16 spare_bytes_per_page;
  	u8 reserved2[6];
  	__le32 pages_per_block;
  	__le32 blocks_per_lun;
  	u8 lun_count;
  	u8 addr_cycles;
  	u8 bits_per_cell;
  	u8 programs_per_page;
  	u8 multi_plane_addr;
  	u8 multi_plane_op_attr;
  	u8 reserved3[38];
  
  	/* electrical parameter block */
  	__le16 async_sdr_speed_grade;
  	__le16 toggle_ddr_speed_grade;
  	__le16 sync_ddr_speed_grade;
  	u8 async_sdr_features;
  	u8 toggle_ddr_features;
  	u8 sync_ddr_features;
  	__le16 t_prog;
  	__le16 t_bers;
  	__le16 t_r;
  	__le16 t_r_multi_plane;
  	__le16 t_ccs;
  	__le16 io_pin_capacitance_typ;
  	__le16 input_pin_capacitance_typ;
  	__le16 clk_pin_capacitance_typ;
  	u8 driver_strength_support;
  	__le16 t_ald;
  	u8 reserved4[36];
  
  	/* ECC and endurance block */
  	u8 guaranteed_good_blocks;
  	__le16 guaranteed_block_endurance;
  	struct jedec_ecc_info ecc_info[4];
  	u8 reserved5[29];
  
  	/* reserved */
  	u8 reserved6[148];
  
  	/* vendor */
  	__le16 vendor_rev_num;
  	u8 reserved7[88];
  
  	/* CRC for Parameter Page */
  	__le16 crc;
  } __packed;
  
  /**
   * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
   * @lock:               protection lock
   * @active:		the mtd device which holds the controller currently
   * @wq:			wait queue to sleep on if a NAND operation is in
   *			progress used instead of the per chip wait queue
   *			when a hw controller is available.
   */
  struct nand_hw_control {
  	spinlock_t lock;
  	struct nand_chip *active;
  	wait_queue_head_t wq;
  };
  
  /**
   * struct nand_ecc_ctrl - Control structure for ECC
   * @mode:	ECC mode
   * @steps:	number of ECC steps per page
   * @size:	data bytes per ECC step
   * @bytes:	ECC bytes per step
   * @strength:	max number of correctible bits per ECC step
   * @total:	total number of ECC bytes per page
   * @prepad:	padding information for syndrome based ECC generators
   * @postpad:	padding information for syndrome based ECC generators
   * @layout:	ECC layout control struct pointer
   * @priv:	pointer to private ECC control data
   * @hwctl:	function to control hardware ECC generator. Must only
   *		be provided if an hardware ECC is available
   * @calculate:	function for ECC calculation or readback from ECC hardware
   * @correct:	function for ECC correction, matching to ECC generator (sw/hw)
   * @read_page_raw:	function to read a raw page without ECC
   * @write_page_raw:	function to write a raw page without ECC
   * @read_page:	function to read a page according to the ECC generator
   *		requirements; returns maximum number of bitflips corrected in
   *		any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
   * @read_subpage:	function to read parts of the page covered by ECC;
   *			returns same as read_page()
   * @write_subpage:	function to write parts of the page covered by ECC.
   * @write_page:	function to write a page according to the ECC generator
   *		requirements.
   * @write_oob_raw:	function to write chip OOB data without ECC
   * @read_oob_raw:	function to read chip OOB data without ECC
   * @read_oob:	function to read chip OOB data
   * @write_oob:	function to write chip OOB data
   */
  struct nand_ecc_ctrl {
  	nand_ecc_modes_t mode;
  	int steps;
  	int size;
  	int bytes;
  	int total;
  	int strength;
  	int prepad;
  	int postpad;
  	struct nand_ecclayout	*layout;
  	void *priv;
  	void (*hwctl)(struct mtd_info *mtd, int mode);
  	int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
  			uint8_t *ecc_code);
  	int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
  			uint8_t *calc_ecc);
  	int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  			uint8_t *buf, int oob_required, int page);
  	int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  			const uint8_t *buf, int oob_required);
  	int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
  			uint8_t *buf, int oob_required, int page);
  	int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
  			uint32_t offs, uint32_t len, uint8_t *buf, int page);
  	int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
  			uint32_t offset, uint32_t data_len,
  			const uint8_t *data_buf, int oob_required);
  	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
  			const uint8_t *buf, int oob_required);
  	int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  			int page);
  	int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  			int page);
  	int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
  	int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
  			int page);
  };
  
  /**
   * struct nand_buffers - buffer structure for read/write
   * @ecccalc:	buffer pointer for calculated ECC, size is oobsize.
   * @ecccode:	buffer pointer for ECC read from flash, size is oobsize.
   * @databuf:	buffer pointer for data, size is (page size + oobsize).
   *
   * Do not change the order of buffers. databuf and oobrbuf must be in
   * consecutive order.
   */
  struct nand_buffers {
  	uint8_t	*ecccalc;
  	uint8_t	*ecccode;
  	uint8_t *databuf;
  };
  
  /**
   * struct nand_chip - NAND Private Flash Chip Data
   * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the
   *			flash device
   * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the
   *			flash device.
   * @read_byte:		[REPLACEABLE] read one byte from the chip
   * @read_word:		[REPLACEABLE] read one word from the chip
   * @write_byte:		[REPLACEABLE] write a single byte to the chip on the
   *			low 8 I/O lines
   * @write_buf:		[REPLACEABLE] write data from the buffer to the chip
   * @read_buf:		[REPLACEABLE] read data from the chip into the buffer
   * @select_chip:	[REPLACEABLE] select chip nr
   * @block_bad:		[REPLACEABLE] check if a block is bad, using OOB markers
   * @block_markbad:	[REPLACEABLE] mark a block bad
   * @cmd_ctrl:		[BOARDSPECIFIC] hardwarespecific function for controlling
   *			ALE/CLE/nCE. Also used to write command and address
   * @init_size:		[BOARDSPECIFIC] hardwarespecific function for setting
   *			mtd->oobsize, mtd->writesize and so on.
   *			@id_data contains the 8 bytes values of NAND_CMD_READID.
   *			Return with the bus width.
   * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accessing
   *			device ready/busy line. If set to NULL no access to
   *			ready/busy is available and the ready/busy information
   *			is read from the chip status register.
   * @cmdfunc:		[REPLACEABLE] hardwarespecific function for writing
   *			commands to the chip.
   * @waitfunc:		[REPLACEABLE] hardwarespecific function for wait on
   *			ready.
   * @setup_read_retry:	[FLASHSPECIFIC] flash (vendor) specific function for
   *			setting the read-retry mode. Mostly needed for MLC NAND.
   * @ecc:		[BOARDSPECIFIC] ECC control structure
   * @buffers:		buffer structure for read/write
   * @hwcontrol:		platform-specific hardware control structure
   * @erase:		[REPLACEABLE] erase function
   * @scan_bbt:		[REPLACEABLE] function to scan bad block table
   * @chip_delay:		[BOARDSPECIFIC] chip dependent delay for transferring
   *			data from array to read regs (tR).
   * @state:		[INTERN] the current state of the NAND device
   * @oob_poi:		"poison value buffer," used for laying out OOB data
   *			before writing
   * @page_shift:		[INTERN] number of address bits in a page (column
   *			address bits).
   * @phys_erase_shift:	[INTERN] number of address bits in a physical eraseblock
   * @bbt_erase_shift:	[INTERN] number of address bits in a bbt entry
   * @chip_shift:		[INTERN] number of address bits in one chip
   * @options:		[BOARDSPECIFIC] various chip options. They can partly
   *			be set to inform nand_scan about special functionality.
   *			See the defines for further explanation.
   * @bbt_options:	[INTERN] bad block specific options. All options used
   *			here must come from bbm.h. By default, these options
   *			will be copied to the appropriate nand_bbt_descr's.
   * @badblockpos:	[INTERN] position of the bad block marker in the oob
   *			area.
   * @badblockbits:	[INTERN] minimum number of set bits in a good block's
   *			bad block marker position; i.e., BBM == 11110111b is
   *			not bad when badblockbits == 7
   * @bits_per_cell:	[INTERN] number of bits per cell. i.e., 1 means SLC.
   * @ecc_strength_ds:	[INTERN] ECC correctability from the datasheet.
   *			Minimum amount of bit errors per @ecc_step_ds guaranteed
   *			to be correctable. If unknown, set to zero.
   * @ecc_step_ds:	[INTERN] ECC step required by the @ecc_strength_ds,
   *                      also from the datasheet. It is the recommended ECC step
   *			size, if known; if unknown, set to zero.
   * @numchips:		[INTERN] number of physical chips
   * @chipsize:		[INTERN] the size of one chip for multichip arrays
   * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
   * @pagebuf:		[INTERN] holds the pagenumber which is currently in
   *			data_buf.
   * @pagebuf_bitflips:	[INTERN] holds the bitflip count for the page which is
   *			currently in data_buf.
   * @subpagesize:	[INTERN] holds the subpagesize
   * @onfi_version:	[INTERN] holds the chip ONFI version (BCD encoded),
   *			non 0 if ONFI supported.
   * @jedec_version:	[INTERN] holds the chip JEDEC version (BCD encoded),
   *			non 0 if JEDEC supported.
   * @onfi_params:	[INTERN] holds the ONFI page parameter when ONFI is
   *			supported, 0 otherwise.
   * @jedec_params:	[INTERN] holds the JEDEC parameter page when JEDEC is
   *			supported, 0 otherwise.
   * @read_retries:	[INTERN] the number of read retry modes supported
   * @onfi_set_features:	[REPLACEABLE] set the features for ONFI nand
   * @onfi_get_features:	[REPLACEABLE] get the features for ONFI nand
   * @bbt:		[INTERN] bad block table pointer
   * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash
   *			lookup.
   * @bbt_md:		[REPLACEABLE] bad block table mirror descriptor
   * @badblock_pattern:	[REPLACEABLE] bad block scan pattern used for initial
   *			bad block scan.
   * @controller:		[REPLACEABLE] a pointer to a hardware controller
   *			structure which is shared among multiple independent
   *			devices.
   * @priv:		[OPTIONAL] pointer to private chip data
   * @errstat:		[OPTIONAL] hardware specific function to perform
   *			additional error status checks (determine if errors are
   *			correctable).
   * @write_page:		[REPLACEABLE] High-level page write function
   */
  
  struct nand_chip {
  	void __iomem *IO_ADDR_R;
  	void __iomem *IO_ADDR_W;
  
  	uint8_t (*read_byte)(struct mtd_info *mtd);
  	u16 (*read_word)(struct mtd_info *mtd);
  	void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
  	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
  	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
  	void (*select_chip)(struct mtd_info *mtd, int chip);
  	int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
  	int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
  	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
  	int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
  			u8 *id_data);
  	int (*dev_ready)(struct mtd_info *mtd);
  	void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
  			int page_addr);
  	int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
  	int (*erase)(struct mtd_info *mtd, int page);
  	int (*scan_bbt)(struct mtd_info *mtd);
  	int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
  			int status, int page);
  	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
  			uint32_t offset, int data_len, const uint8_t *buf,
  			int oob_required, int page, int cached, int raw);
  	int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
  			int feature_addr, uint8_t *subfeature_para);
  	int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
  			int feature_addr, uint8_t *subfeature_para);
  	int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
  
  	int chip_delay;
  	unsigned int options;
  	unsigned int bbt_options;
  
  	int page_shift;
  	int phys_erase_shift;
  	int bbt_erase_shift;
  	int chip_shift;
  	int numchips;
  	uint64_t chipsize;
  	int pagemask;
  	int pagebuf;
  	unsigned int pagebuf_bitflips;
  	int subpagesize;
  	uint8_t bits_per_cell;
  	uint16_t ecc_strength_ds;
  	uint16_t ecc_step_ds;
  	int badblockpos;
  	int badblockbits;
  
  	int onfi_version;
  	int jedec_version;
  	union {
  		struct nand_onfi_params	onfi_params;
  		struct nand_jedec_params jedec_params;
  	};
  
  	int read_retries;
  
  	flstate_t state;
  
  	uint8_t *oob_poi;
  	struct nand_hw_control *controller;
  
  	struct nand_ecc_ctrl ecc;
  	struct nand_buffers *buffers;
  	struct nand_hw_control hwcontrol;
  
  	uint8_t *bbt;
  	struct nand_bbt_descr *bbt_td;
  	struct nand_bbt_descr *bbt_md;
  
  	struct nand_bbt_descr *badblock_pattern;
  
  	void *priv;
  };
  
  /*
   * NAND Flash Manufacturer ID Codes
   */
  #define NAND_MFR_TOSHIBA	0x98
  #define NAND_MFR_SAMSUNG	0xec
  #define NAND_MFR_FUJITSU	0x04
  #define NAND_MFR_NATIONAL	0x8f
  #define NAND_MFR_RENESAS	0x07
  #define NAND_MFR_STMICRO	0x20
  #define NAND_MFR_HYNIX		0xad
  #define NAND_MFR_MICRON		0x2c
  #define NAND_MFR_AMD		0x01
  #define NAND_MFR_MACRONIX	0xc2
  #define NAND_MFR_EON		0x92
  #define NAND_MFR_SANDISK	0x45
  #define NAND_MFR_INTEL		0x89
  
  /* The maximum expected count of bytes in the NAND ID sequence */
  #define NAND_MAX_ID_LEN 8
  
  /*
   * A helper for defining older NAND chips where the second ID byte fully
   * defined the chip, including the geometry (chip size, eraseblock size, page
   * size). All these chips have 512 bytes NAND page size.
   */
  #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts)          \
  	{ .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
  	  .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
  
  /*
   * A helper for defining newer chips which report their page size and
   * eraseblock size via the extended ID bytes.
   *
   * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
   * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
   * device ID now only represented a particular total chip size (and voltage,
   * buswidth), and the page size, eraseblock size, and OOB size could vary while
   * using the same device ID.
   */
  #define EXTENDED_ID_NAND(nm, devid, chipsz, opts)                      \
  	{ .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
  	  .options = (opts) }
  
  #define NAND_ECC_INFO(_strength, _step)	\
  			{ .strength_ds = (_strength), .step_ds = (_step) }
  #define NAND_ECC_STRENGTH(type)		((type)->ecc.strength_ds)
  #define NAND_ECC_STEP(type)		((type)->ecc.step_ds)
  
  /**
   * struct nand_flash_dev - NAND Flash Device ID Structure
   * @name: a human-readable name of the NAND chip
   * @dev_id: the device ID (the second byte of the full chip ID array)
   * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
   *          memory address as @id[0])
   * @dev_id: device ID part of the full chip ID array (refers the same memory
   *          address as @id[1])
   * @id: full device ID array
   * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
   *            well as the eraseblock size) is determined from the extended NAND
   *            chip ID array)
   * @chipsize: total chip size in MiB
   * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
   * @options: stores various chip bit options
   * @id_len: The valid length of the @id.
   * @oobsize: OOB size
   * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
   *                   @ecc_strength_ds in nand_chip{}.
   * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
   *               @ecc_step_ds in nand_chip{}, also from the datasheet.
   *               For example, the "4bit ECC for each 512Byte" can be set with
   *               NAND_ECC_INFO(4, 512).
   */
  struct nand_flash_dev {
  	char *name;
  	union {
  		struct {
  			uint8_t mfr_id;
  			uint8_t dev_id;
  		};
  		uint8_t id[NAND_MAX_ID_LEN];
  	};
  	unsigned int pagesize;
  	unsigned int chipsize;
  	unsigned int erasesize;
  	unsigned int options;
  	uint16_t id_len;
  	uint16_t oobsize;
  	struct {
  		uint16_t strength_ds;
  		uint16_t step_ds;
  	} ecc;
  };
  
  /**
   * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
   * @name:	Manufacturer name
   * @id:		manufacturer ID code of device.
  */
  struct nand_manufacturers {
  	int id;
  	char *name;
  };
  
  extern struct nand_flash_dev nand_flash_ids[];
  extern struct nand_manufacturers nand_manuf_ids[];
  
  extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
  extern int nand_default_bbt(struct mtd_info *mtd);
  extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
  extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
  extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
  			   int allowbbt);
  extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
  			size_t *retlen, uint8_t *buf);
  
  /**
   * struct platform_nand_chip - chip level device structure
   * @nr_chips:		max. number of chips to scan for
   * @chip_offset:	chip number offset
   * @nr_partitions:	number of partitions pointed to by partitions (or zero)
   * @partitions:		mtd partition list
   * @chip_delay:		R/B delay value in us
   * @options:		Option flags, e.g. 16bit buswidth
   * @bbt_options:	BBT option flags, e.g. NAND_BBT_USE_FLASH
   * @ecclayout:		ECC layout info structure
   * @part_probe_types:	NULL-terminated array of probe types
   */
  struct platform_nand_chip {
  	int nr_chips;
  	int chip_offset;
  	int nr_partitions;
  	struct mtd_partition *partitions;
  	struct nand_ecclayout *ecclayout;
  	int chip_delay;
  	unsigned int options;
  	unsigned int bbt_options;
  	const char **part_probe_types;
  };
  
  /* Keep gcc happy */
  struct platform_device;
  
  /**
   * struct platform_nand_ctrl - controller level device structure
   * @probe:		platform specific function to probe/setup hardware
   * @remove:		platform specific function to remove/teardown hardware
   * @hwcontrol:		platform specific hardware control structure
   * @dev_ready:		platform specific function to read ready/busy pin
   * @select_chip:	platform specific chip select function
   * @cmd_ctrl:		platform specific function for controlling
   *			ALE/CLE/nCE. Also used to write command and address
   * @write_buf:		platform specific function for write buffer
   * @read_buf:		platform specific function for read buffer
   * @read_byte:		platform specific function to read one byte from chip
   * @priv:		private data to transport driver specific settings
   *
   * All fields are optional and depend on the hardware driver requirements
   */
  struct platform_nand_ctrl {
  	int (*probe)(struct platform_device *pdev);
  	void (*remove)(struct platform_device *pdev);
  	void (*hwcontrol)(struct mtd_info *mtd, int cmd);
  	int (*dev_ready)(struct mtd_info *mtd);
  	void (*select_chip)(struct mtd_info *mtd, int chip);
  	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
  	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
  	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
  	unsigned char (*read_byte)(struct mtd_info *mtd);
  	void *priv;
  };
  
  /**
   * struct platform_nand_data - container structure for platform-specific data
   * @chip:		chip level chip structure
   * @ctrl:		controller level device structure
   */
  struct platform_nand_data {
  	struct platform_nand_chip chip;
  	struct platform_nand_ctrl ctrl;
  };
  
  /* Some helpers to access the data structures */
  static inline
  struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
  {
  	struct nand_chip *chip = mtd->priv;
  
  	return chip->priv;
  }
  
  /* return the supported features. */
  static inline int onfi_feature(struct nand_chip *chip)
  {
  	return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
  }
  
  /* return the supported asynchronous timing mode. */
  static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
  {
  	if (!chip->onfi_version)
  		return ONFI_TIMING_MODE_UNKNOWN;
  	return le16_to_cpu(chip->onfi_params.async_timing_mode);
  }
  
  /* return the supported synchronous timing mode. */
  static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
  {
  	if (!chip->onfi_version)
  		return ONFI_TIMING_MODE_UNKNOWN;
  	return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
  }
  
  /*
   * Check if it is a SLC nand.
   * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
   * We do not distinguish the MLC and TLC now.
   */
  static inline bool nand_is_slc(struct nand_chip *chip)
  {
  	return chip->bits_per_cell == 1;
  }
  
  /**
   * Check if the opcode's address should be sent only on the lower 8 bits
   * @command: opcode to check
   */
  static inline int nand_opcode_8bits(unsigned int command)
  {
  	switch (command) {
  	case NAND_CMD_READID:
  	case NAND_CMD_PARAM:
  	case NAND_CMD_GET_FEATURES:
  	case NAND_CMD_SET_FEATURES:
  		return 1;
  	default:
  		break;
  	}
  	return 0;
  }
  
  /* return the supported JEDEC features. */
  static inline int jedec_feature(struct nand_chip *chip)
  {
  	return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
  		: 0;
  }
  #endif /* __LINUX_MTD_NAND_H */