6b13f685e
 김민수
BSP 최초 추가
|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
|
#include <linux/kernel.h>
#include <linux/pci.h>
#include <asm/bootinfo.h>
#include <asm/lasat/lasat.h>
#include <asm/nile4.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
#define LO(reg) (reg / 4)
#define HI(reg) (reg / 4 + 1)
volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE;
static DEFINE_SPINLOCK(nile4_pci_lock);
static int nile4_pcibios_config_access(unsigned char access_type,
struct pci_bus *bus, unsigned int devfn, int where, u32 *val)
{
unsigned char busnum = bus->number;
u32 adr, mask, err;
if ((busnum == 0) && (PCI_SLOT(devfn) > 8))
/* The addressing scheme chosen leaves room for just
* 8 devices on the first busnum (besides the PCI
* controller itself) */
return PCIBIOS_DEVICE_NOT_FOUND;
if ((busnum == 0) && (devfn == PCI_DEVFN(0, 0))) {
/* Access controller registers directly */
if (access_type == PCI_ACCESS_WRITE) {
vrc_pciregs[(0x200 + where) >> 2] = *val;
} else {
*val = vrc_pciregs[(0x200 + where) >> 2];
}
return PCIBIOS_SUCCESSFUL;
}
/* Temporarily map PCI Window 1 to config space */
mask = vrc_pciregs[LO(NILE4_PCIINIT1)];
vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (busnum ? 0x200 : 0);
/* Clear PCI Error register. This also clears the Error Type
* bits in the Control register */
vrc_pciregs[LO(NILE4_PCIERR)] = 0;
vrc_pciregs[HI(NILE4_PCIERR)] = 0;
/* Setup address */
if (busnum == 0)
adr =
KSEG1ADDR(PCI_WINDOW1) +
((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8)
| (where & ~3));
else
adr = KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8) |
(where & ~3);
if (access_type == PCI_ACCESS_WRITE)
*(u32 *) adr = *val;
else
*val = *(u32 *) adr;
/* Check for master or target abort */
err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7;
/* Restore PCI Window 1 */
vrc_pciregs[LO(NILE4_PCIINIT1)] = mask;
if (err)
return PCIBIOS_DEVICE_NOT_FOUND;
return PCIBIOS_SUCCESSFUL;
}
static int nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
unsigned long flags;
u32 data = 0;
int err;
if ((size == 2) && (where & 1))
return PCIBIOS_BAD_REGISTER_NUMBER;
else if ((size == 4) && (where & 3))
return PCIBIOS_BAD_REGISTER_NUMBER;
spin_lock_irqsave(&nile4_pci_lock, flags);
err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
&data);
spin_unlock_irqrestore(&nile4_pci_lock, flags);
if (err)
return err;
if (size == 1)
*val = (data >> ((where & 3) << 3)) & 0xff;
else if (size == 2)
*val = (data >> ((where & 3) << 3)) & 0xffff;
else
*val = data;
return PCIBIOS_SUCCESSFUL;
}
static int nile4_pcibios_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
unsigned long flags;
u32 data = 0;
int err;
if ((size == 2) && (where & 1))
return PCIBIOS_BAD_REGISTER_NUMBER;
else if ((size == 4) && (where & 3))
return PCIBIOS_BAD_REGISTER_NUMBER;
spin_lock_irqsave(&nile4_pci_lock, flags);
err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
&data);
spin_unlock_irqrestore(&nile4_pci_lock, flags);
if (err)
return err;
if (size == 1)
data = (data & ~(0xff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
else if (size == 2)
data = (data & ~(0xffff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
else
data = val;
if (nile4_pcibios_config_access
(PCI_ACCESS_WRITE, bus, devfn, where, &data))
return -1;
return PCIBIOS_SUCCESSFUL;
}
struct pci_ops nile4_pci_ops = {
.read = nile4_pcibios_read,
.write = nile4_pcibios_write,
};
|