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#ifndef _DDR_SPD_H_
#define _DDR_SPD_H_
typedef struct ddr1_spd_eeprom_s {
unsigned char info_size;
unsigned char chip_size;
unsigned char mem_type;
unsigned char nrow_addr;
unsigned char ncol_addr;
unsigned char nrows;
unsigned char dataw_lsb;
unsigned char dataw_msb;
unsigned char voltage;
unsigned char clk_cycle;
unsigned char clk_access;
unsigned char config;
unsigned char refresh;
unsigned char primw;
unsigned char ecw;
unsigned char min_delay;
unsigned char burstl;
unsigned char nbanks;
unsigned char cas_lat;
unsigned char cs_lat;
unsigned char write_lat;
unsigned char mod_attr;
unsigned char dev_attr;
unsigned char clk_cycle2;
unsigned char clk_access2;
unsigned char clk_cycle3;
unsigned char clk_access3;
unsigned char trp;
unsigned char trrd;
unsigned char trcd;
unsigned char tras;
unsigned char bank_dens;
unsigned char ca_setup;
unsigned char ca_hold;
unsigned char data_setup;
unsigned char data_hold;
unsigned char res_36_40[5];
unsigned char trc;
unsigned char trfc;
unsigned char tckmax;
unsigned char tdqsq;
unsigned char tqhs;
unsigned char res_46;
unsigned char dimm_height;
unsigned char res_48_61[14];
unsigned char spd_rev;
unsigned char cksum;
unsigned char mid[8];
unsigned char mloc;
unsigned char mpart[18];
unsigned char rev[2];
unsigned char mdate[2];
unsigned char sernum[4];
unsigned char mspec[27];
} ddr1_spd_eeprom_t;
typedef struct ddr2_spd_eeprom_s {
unsigned char info_size;
unsigned char chip_size;
unsigned char mem_type;
unsigned char nrow_addr;
unsigned char ncol_addr;
unsigned char mod_ranks;
unsigned char dataw;
unsigned char res_7;
unsigned char voltage;
unsigned char clk_cycle;
unsigned char clk_access;
unsigned char config;
unsigned char refresh;
unsigned char primw;
unsigned char ecw;
unsigned char res_15;
unsigned char burstl;
unsigned char nbanks;
unsigned char cas_lat;
unsigned char mech_char;
unsigned char dimm_type;
unsigned char mod_attr;
unsigned char dev_attr;
unsigned char clk_cycle2;
unsigned char clk_access2;
unsigned char clk_cycle3;
unsigned char clk_access3;
unsigned char trp;
unsigned char trrd;
unsigned char trcd;
unsigned char tras;
unsigned char rank_dens;
unsigned char ca_setup;
unsigned char ca_hold;
unsigned char data_setup;
unsigned char data_hold;
unsigned char twr;
unsigned char twtr;
unsigned char trtp;
unsigned char mem_probe;
unsigned char trctrfc_ext;
unsigned char trc;
unsigned char trfc;
unsigned char tckmax;
unsigned char tdqsq;
unsigned char tqhs;
unsigned char pll_relock;
unsigned char t_casemax;
unsigned char psi_ta_dram;
unsigned char dt0_mode;
unsigned char dt2n_dt2q;
unsigned char dt2p;
unsigned char dt3n;
unsigned char dt3pfast;
unsigned char dt3pslow;
unsigned char dt4r_dt4r4w;
unsigned char dt5b;
unsigned char dt7;
unsigned char psi_ta_pll;
unsigned char psi_ta_reg;
unsigned char dtpllactive;
unsigned char dtregact;
unsigned char spd_rev;
unsigned char cksum;
unsigned char mid[8];
unsigned char mloc;
unsigned char mpart[18];
unsigned char rev[2];
unsigned char mdate[2];
unsigned char sernum[4];
unsigned char mspec[27];
} ddr2_spd_eeprom_t;
typedef struct ddr3_spd_eeprom_s {
unsigned char info_size_crc;
unsigned char spd_rev;
unsigned char mem_type;
unsigned char module_type;
unsigned char density_banks;
unsigned char addressing;
unsigned char module_vdd;
unsigned char organization;
unsigned char bus_width;
unsigned char ftb_div;
unsigned char mtb_dividend;
unsigned char mtb_divisor;
unsigned char tck_min;
unsigned char res_13;
unsigned char caslat_lsb;
unsigned char caslat_msb;
unsigned char taa_min;
unsigned char twr_min;
unsigned char trcd_min;
unsigned char trrd_min;
unsigned char trp_min;
unsigned char tras_trc_ext;
unsigned char tras_min_lsb;
unsigned char trc_min_lsb;
unsigned char trfc_min_lsb;
unsigned char trfc_min_msb;
unsigned char twtr_min;
unsigned char trtp_min;
unsigned char tfaw_msb;
unsigned char tfaw_min;
unsigned char opt_features;
unsigned char therm_ref_opt;
unsigned char therm_sensor;
unsigned char device_type;
int8_t fine_tck_min;
int8_t fine_taa_min;
int8_t fine_trcd_min;
int8_t fine_trp_min;
int8_t fine_trc_min;
unsigned char res_39_59[21];
union {
struct {
unsigned char mod_height;
unsigned char mod_thickness;
unsigned char ref_raw_card;
unsigned char addr_mapping;
unsigned char res_64_116[53];
} unbuffered;
struct {
unsigned char mod_height;
unsigned char mod_thickness;
unsigned char ref_raw_card;
unsigned char modu_attr;
unsigned char thermal;
unsigned char reg_id_lo;
unsigned char reg_id_hi;
unsigned char reg_rev;
unsigned char reg_type;
unsigned char rcw[8];
} registered;
unsigned char uc[57];
} mod_section;
unsigned char mmid_lsb;
unsigned char mmid_msb;
unsigned char mloc;
unsigned char mdate[2];
unsigned char sernum[4];
unsigned char crc[2];
unsigned char mpart[18];
unsigned char mrev[2];
unsigned char dmid_lsb;
unsigned char dmid_msb;
unsigned char msd[26];
unsigned char cust[80];
} ddr3_spd_eeprom_t;
struct ddr4_spd_eeprom_s {
uint8_t info_size_crc;
uint8_t spd_rev;
uint8_t mem_type;
uint8_t module_type;
uint8_t density_banks;
uint8_t addressing;
uint8_t package_type;
uint8_t opt_feature;
uint8_t thermal_ref;
uint8_t oth_opt_features;
uint8_t res_10;
uint8_t module_vdd;
uint8_t organization;
uint8_t bus_width;
uint8_t therm_sensor;
uint8_t ext_type;
uint8_t res_16;
uint8_t timebases;
uint8_t tck_min;
uint8_t tck_max;
uint8_t caslat_b1;
uint8_t caslat_b2;
uint8_t caslat_b3;
uint8_t caslat_b4;
uint8_t taa_min;
uint8_t trcd_min;
uint8_t trp_min;
uint8_t tras_trc_ext;
uint8_t tras_min_lsb;
uint8_t trc_min_lsb;
uint8_t trfc1_min_lsb;
uint8_t trfc1_min_msb;
uint8_t trfc2_min_lsb;
uint8_t trfc2_min_msb;
uint8_t trfc4_min_lsb;
uint8_t trfc4_min_msb;
uint8_t tfaw_msb;
uint8_t tfaw_min;
uint8_t trrds_min;
uint8_t trrdl_min;
uint8_t tccdl_min;
uint8_t res_41[60-41];
uint8_t mapping[78-60];
uint8_t res_78[117-78];
int8_t fine_tccdl_min;
int8_t fine_trrdl_min;
int8_t fine_trrds_min;
int8_t fine_trc_min;
int8_t fine_trp_min;
int8_t fine_trcd_min;
int8_t fine_taa_min;
int8_t fine_tck_max;
int8_t fine_tck_min;
uint8_t crc[2];
union {
struct {
uint8_t mod_height;
uint8_t mod_thickness;
uint8_t ref_raw_card;
uint8_t addr_mapping;
uint8_t res_132[254-132];
uint8_t crc[2];
} unbuffered;
struct {
uint8_t mod_height;
uint8_t mod_thickness;
uint8_t ref_raw_card;
uint8_t modu_attr;
uint8_t thermal;
uint8_t reg_id_lo;
uint8_t reg_id_hi;
uint8_t reg_rev;
uint8_t reg_map;
uint8_t res_137[254-137];
uint8_t crc[2];
} registered;
struct {
uint8_t mod_height;
uint8_t mod_thickness;
uint8_t ref_raw_card;
uint8_t modu_attr;
uint8_t thermal;
uint8_t reg_id_lo;
uint8_t reg_id_hi;
uint8_t reg_rev;
uint8_t reg_map;
uint8_t reg_drv;
uint8_t reg_drv_ck;
uint8_t data_buf_rev;
uint8_t vrefqe_r0;
uint8_t vrefqe_r1;
uint8_t vrefqe_r2;
uint8_t vrefqe_r3;
uint8_t data_intf;
uint8_t data_drv_1866;
uint8_t data_drv_2400;
uint8_t data_drv_3200;
uint8_t dram_drv;
uint8_t dram_odt_1866;
uint8_t dram_odt_2400;
uint8_t dram_odt_3200;
uint8_t dram_odt_park_1866;
uint8_t dram_odt_park_2400;
uint8_t dram_odt_park_3200;
uint8_t res_155[254-155];
uint8_t crc[2];
} loadreduced;
uint8_t uc[128];
} mod_section;
uint8_t res_256[320-256];
uint8_t mmid_lsb;
uint8_t mmid_msb;
uint8_t mloc;
uint8_t mdate[2];
uint8_t sernum[4];
uint8_t mpart[20];
uint8_t mrev;
uint8_t dmid_lsb;
uint8_t dmid_msb;
uint8_t stepping;
uint8_t msd[29];
uint8_t res_382[2];
uint8_t user[512-384];
};
extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd);
extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd);
extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd);
extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd);
extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd);
#define SPD_MEMTYPE_FPM (0x01)
#define SPD_MEMTYPE_EDO (0x02)
#define SPD_MEMTYPE_PIPE_NIBBLE (0x03)
#define SPD_MEMTYPE_SDRAM (0x04)
#define SPD_MEMTYPE_ROM (0x05)
#define SPD_MEMTYPE_SGRAM (0x06)
#define SPD_MEMTYPE_DDR (0x07)
#define SPD_MEMTYPE_DDR2 (0x08)
#define SPD_MEMTYPE_DDR2_FBDIMM (0x09)
#define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A)
#define SPD_MEMTYPE_DDR3 (0x0B)
#define SPD_MEMTYPE_DDR4 (0x0C)
#define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00)
#define DDR2_SPD_DIMMTYPE_RDIMM (0x01)
#define DDR2_SPD_DIMMTYPE_UDIMM (0x02)
#define DDR2_SPD_DIMMTYPE_SO_DIMM (0x04)
#define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM (0x06)
#define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM (0x07)
#define DDR2_SPD_DIMMTYPE_MICRO_DIMM (0x08)
#define DDR2_SPD_DIMMTYPE_MINI_RDIMM (0x10)
#define DDR2_SPD_DIMMTYPE_MINI_UDIMM (0x20)
#define DDR3_SPD_MODULETYPE_MASK (0x0f)
#define DDR3_SPD_MODULETYPE_RDIMM (0x01)
#define DDR3_SPD_MODULETYPE_UDIMM (0x02)
#define DDR3_SPD_MODULETYPE_SO_DIMM (0x03)
#define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04)
#define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05)
#define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06)
#define DDR3_SPD_MODULETYPE_MINI_CDIMM (0x07)
#define DDR3_SPD_MODULETYPE_72B_SO_UDIMM (0x08)
#define DDR3_SPD_MODULETYPE_72B_SO_RDIMM (0x09)
#define DDR3_SPD_MODULETYPE_72B_SO_CDIMM (0x0A)
#define DDR3_SPD_MODULETYPE_LRDIMM (0x0B)
#define DDR3_SPD_MODULETYPE_16B_SO_DIMM (0x0C)
#define DDR3_SPD_MODULETYPE_32B_SO_DIMM (0x0D)
#define DDR4_SPD_MODULETYPE_MASK (0x0f)
#define DDR4_SPD_MODULETYPE_EXT (0x00)
#define DDR4_SPD_MODULETYPE_RDIMM (0x01)
#define DDR4_SPD_MODULETYPE_UDIMM (0x02)
#define DDR4_SPD_MODULETYPE_SO_DIMM (0x03)
#define DDR4_SPD_MODULETYPE_LRDIMM (0x04)
#define DDR4_SPD_MODULETYPE_MINI_RDIMM (0x05)
#define DDR4_SPD_MODULETYPE_MINI_UDIMM (0x06)
#define DDR4_SPD_MODULETYPE_72B_SO_UDIMM (0x08)
#define DDR4_SPD_MODULETYPE_72B_SO_RDIMM (0x09)
#define DDR4_SPD_MODULETYPE_16B_SO_DIMM (0x0C)
#define DDR4_SPD_MODULETYPE_32B_SO_DIMM (0x0D)
#endif /* _DDR_SPD_H_ */
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