에프에이리눅스 / 1611_0007_prime_oven

Blame view

kernel/linux-imx6_3.14.28/arch/arm/mach-omap2/cm3xxx.h 2.98 KB
edit raw normal view history
6b13f685e   김민수   BSP 최초 추가 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
 
  /*
   * OMAP2/3 Clock Management (CM) register definitions
   *
   * Copyright (C) 2007-2009 Texas Instruments, Inc.
   * Copyright (C) 2007-2010 Nokia Corporation
   * Paul Walmsley
   *
   * This program is free software; you can redistribute it and/or modify
   * it under the terms of the GNU General Public License version 2 as
   * published by the Free Software Foundation.
   *
   * The CM hardware modules on the OMAP2/3 are quite similar to each
   * other.  The CM modules/instances on OMAP4 are quite different, so
   * they are handled in a separate file.
   */
  #ifndef __ARCH_ASM_MACH_OMAP2_CM3XXX_H
  #define __ARCH_ASM_MACH_OMAP2_CM3XXX_H
  
  #include "prcm-common.h"
  #include "cm2xxx_3xxx.h"
  
  #define OMAP34XX_CM_REGADDR(module, reg)				\
  			OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
  
  
  /*
   * OMAP3-specific global CM registers
   * Use cm_{read,write}_reg() with these registers.
   * These registers appear once per CM module.
   */
  
  #define OMAP3430_CM_REVISION		OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
  #define OMAP3430_CM_SYSCONFIG		OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
  #define OMAP3430_CM_POLCTRL		OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
  
  #define OMAP3_CM_CLKOUT_CTRL_OFFSET	0x0070
  #define OMAP3430_CM_CLKOUT_CTRL		OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
  
  /*
   * Module specific CM register offsets from CM_BASE + domain offset
   * Use cm_{read,write}_mod_reg() with these registers.
   * These register offsets generally appear in more than one PRCM submodule.
   */
  
  /* OMAP3-specific register offsets */
  
  #define OMAP3430_CM_CLKEN_PLL				0x0004
  #define OMAP3430ES2_CM_CLKEN2				0x0004
  #define OMAP3430ES2_CM_FCLKEN3				0x0008
  #define OMAP3430_CM_IDLEST_PLL				CM_IDLEST2
  #define OMAP3430_CM_AUTOIDLE_PLL			CM_AUTOIDLE2
  #define OMAP3430ES2_CM_AUTOIDLE2_PLL			CM_AUTOIDLE2
  #define OMAP3430_CM_CLKSEL1				CM_CLKSEL
  #define OMAP3430_CM_CLKSEL1_PLL				CM_CLKSEL
  #define OMAP3430_CM_CLKSEL2_PLL				CM_CLKSEL2
  #define OMAP3430_CM_SLEEPDEP				CM_CLKSEL2
  #define OMAP3430_CM_CLKSEL3				OMAP2_CM_CLKSTCTRL
  #define OMAP3430_CM_CLKSTST				0x004c
  #define OMAP3430ES2_CM_CLKSEL4				0x004c
  #define OMAP3430ES2_CM_CLKSEL5				0x0050
  #define OMAP3430_CM_CLKSEL2_EMU				0x0050
  #define OMAP3430_CM_CLKSEL3_EMU				0x0054
  
  
  /* CM_IDLEST bit field values to indicate deasserted IdleReq */
  
  #define OMAP34XX_CM_IDLEST_VAL				1
  
  
  #ifndef __ASSEMBLER__
  
  extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
  extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
  extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
  extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
  
  extern bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
  extern int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
  					 u8 idlest_shift);
  
  extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
  					s16 *prcm_inst, u8 *idlest_reg_id);
  
  extern void omap3_cm_save_context(void);
  extern void omap3_cm_restore_context(void);
  extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
  
  extern int __init omap3xxx_cm_init(void);
  
  #endif
  
  #endif