6b13f685e
 김민수
BSP 최초 추가
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#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/mach/time.h>
#include <mach/netx-regs.h>
#define TIMER_CLOCKEVENT 0
#define TIMER_CLOCKSOURCE 1
static void netx_set_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
u32 tmode;
writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
writel(LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
tmode = NETX_GPIO_COUNTER_CTRL_RST_EN |
NETX_GPIO_COUNTER_CTRL_IRQ_EN |
NETX_GPIO_COUNTER_CTRL_RUN;
break;
case CLOCK_EVT_MODE_ONESHOT:
writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
tmode = NETX_GPIO_COUNTER_CTRL_IRQ_EN |
NETX_GPIO_COUNTER_CTRL_RUN;
break;
default:
WARN(1, "%s: unhandled mode %d
", __func__, mode);
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_RESUME:
tmode = 0;
break;
}
writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
}
static int netx_set_next_event(unsigned long evt,
struct clock_event_device *clk)
{
writel(0 - evt, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKEVENT));
return 0;
}
static struct clock_event_device netx_clockevent = {
.name = "netx-timer" __stringify(TIMER_CLOCKEVENT),
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = netx_set_next_event,
.set_mode = netx_set_mode,
};
static irqreturn_t
netx_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = &netx_clockevent;
writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction netx_timer_irq = {
.name = "NetX Timer Tick",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = netx_timer_interrupt,
};
void __init netx_timer_init(void)
{
writel(0, NETX_GPIO_COUNTER_CTRL(0));
writel(0, NETX_GPIO_COUNTER_CURRENT(0));
writel(LATCH, NETX_GPIO_COUNTER_MAX(0));
writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
writel(COUNTER_BIT(0), NETX_GPIO_IRQ_ENABLE);
writel(NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN,
NETX_GPIO_COUNTER_CTRL(0));
setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq);
writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
writel(0, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE));
writel(0xffffffff, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKSOURCE));
writel(NETX_GPIO_COUNTER_CTRL_RUN,
NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE),
"netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up);
netx_clockevent.cpumask = cpumask_of(0);
clockevents_config_and_register(&netx_clockevent, CLOCK_TICK_RATE,
0xa00, 0xfffffffe);
}
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