6b13f685e
김민수
BSP 최초 추가
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SOCFPGA Documentation for U-Boot and SPL
This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
based SOCFPGA. To know more about the hardware itself, please refer to
www.altera.com.
socfpga_dw_mmc
Here are macro and detailed configuration required to enable DesignWare SDMMC
controller support within SOCFPGA
-> To enable the SD MMC framework support
-> The base address of CSR register for DesignWare SDMMC controller
-> Enable the generic MMC driver
-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
-> Enable the common DesignWare SDMMC controller framework
-> Enable the SOCFPGA specific driver for DesignWare SDMMC controller
-> The FIFO depth for SOCFPGA DesignWare SDMMC controller
-> Phase-shifted clock of sdmmc_clk for controller to drive command and data to
the card to meet hold time requirements. SD clock is running at 50MHz and
drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time
is 135 / 360 * 20ns = 7.5ns.
-> Phase-shifted clock of sdmmc_clk used to sample the command and data from
the card
-> Bus width of data line which either 1, 4 or 8 and based on board routing.
-> The clock rate to controller. Do note the controller have a wrapper which
divide the clock from PLL by 4.
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