/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
   *
   * This program is free software; you can redistribute it and/or modify
   * it under the terms of the GNU General Public License version 2 and
   * only version 2 as published by the Free Software Foundation.
   *
   * This program is distributed in the hope that it will be useful,
   * but WITHOUT ANY WARRANTY; without even the implied warranty of
   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   * GNU General Public License for more details.
   *
   * You should have received a copy of the GNU General Public License
   * along with this program; if not, write to the Free Software
   * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
   * 02110-1301, USA.
   */
  
  #ifndef MSM_IOMMU_H
  #define MSM_IOMMU_H
  
  #include <linux/interrupt.h>
  #include <linux/clk.h>
  
  /* Sharability attributes of MSM IOMMU mappings */
  #define MSM_IOMMU_ATTR_NON_SH		0x0
  #define MSM_IOMMU_ATTR_SH		0x4
  
  /* Cacheability attributes of MSM IOMMU mappings */
  #define MSM_IOMMU_ATTR_NONCACHED	0x0
  #define MSM_IOMMU_ATTR_CACHED_WB_WA	0x1
  #define MSM_IOMMU_ATTR_CACHED_WB_NWA	0x2
  #define MSM_IOMMU_ATTR_CACHED_WT	0x3
  
  /* Mask for the cache policy attribute */
  #define MSM_IOMMU_CP_MASK		0x03
  
  /* Maximum number of Machine IDs that we are allowing to be mapped to the same
   * context bank. The number of MIDs mapped to the same CB does not affect
   * performance, but there is a practical limit on how many distinct MIDs may
   * be present. These mappings are typically determined at design time and are
   * not expected to change at run time.
   */
  #define MAX_NUM_MIDS	32
  
  /**
   * struct msm_iommu_dev - a single IOMMU hardware instance
   * name		Human-readable name given to this IOMMU HW instance
   * ncb		Number of context banks present on this IOMMU HW instance
   */
  struct msm_iommu_dev {
  	const char *name;
  	int ncb;
  };
  
  /**
   * struct msm_iommu_ctx_dev - an IOMMU context bank instance
   * name		Human-readable name given to this context bank
   * num		Index of this context bank within the hardware
   * mids		List of Machine IDs that are to be mapped into this context
   *		bank, terminated by -1. The MID is a set of signals on the
   *		AXI bus that identifies the function associated with a specific
   *		memory request. (See ARM spec).
   */
  struct msm_iommu_ctx_dev {
  	const char *name;
  	int num;
  	int mids[MAX_NUM_MIDS];
  };
  
  
  /**
   * struct msm_iommu_drvdata - A single IOMMU hardware instance
   * @base:	IOMMU config port base address (VA)
   * @ncb		The number of contexts on this IOMMU
   * @irq:	Interrupt number
   * @clk:	The bus clock for this IOMMU hardware instance
   * @pclk:	The clock for the IOMMU bus interconnect
   *
   * A msm_iommu_drvdata holds the global driver data about a single piece
   * of an IOMMU hardware instance.
   */
  struct msm_iommu_drvdata {
  	void __iomem *base;
  	int irq;
  	int ncb;
  	struct clk *clk;
  	struct clk *pclk;
  };
  
  /**
   * struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
   * @num:		Hardware context number of this context
   * @pdev:		Platform device associated wit this HW instance
   * @attached_elm:	List element for domains to track which devices are
   *			attached to them
   *
   * A msm_iommu_ctx_drvdata holds the driver data for a single context bank
   * within each IOMMU hardware instance
   */
  struct msm_iommu_ctx_drvdata {
  	int num;
  	struct platform_device *pdev;
  	struct list_head attached_elm;
  };
  
  /*
   * Look up an IOMMU context device by its context name. NULL if none found.
   * Useful for testing and drivers that do not yet fully have IOMMU stuff in
   * their platform devices.
   */
  struct device *msm_iommu_get_ctx(const char *ctx_name);
  
  /*
   * Interrupt handler for the IOMMU context fault interrupt. Hooking the
   * interrupt is not supported in the API yet, but this will print an error
   * message and dump useful IOMMU registers.
   */
  irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
  
  #endif