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#ifndef __FSL_SEC_H
#define __FSL_SEC_H
#include <common.h>
#include <asm/io.h>
#ifdef CONFIG_SYS_FSL_SEC_LE
#define sec_in32(a) in_le32(a)
#define sec_out32(a, v) out_le32(a, v)
#define sec_in16(a) in_le16(a)
#define sec_clrbits32 clrbits_le32
#define sec_setbits32 setbits_le32
#elif defined(CONFIG_SYS_FSL_SEC_BE)
#define sec_in32(a) in_be32(a)
#define sec_out32(a, v) out_be32(a, v)
#define sec_in16(a) in_be16(a)
#define sec_clrbits32 clrbits_be32
#define sec_setbits32 setbits_be32
#else
#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
#endif
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
struct rng4tst {
#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
u32 rtmctl;
u32 rtscmisc;
u32 rtpkrrng;
#define RTSDCTL_ENT_DLY_MIN 1200
#define RTSDCTL_ENT_DLY_MAX 12800
union {
u32 rtpkrmax;
u32 rtpkrsq;
};
#define RTSDCTL_ENT_DLY_SHIFT 16
#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
u32 rtsdctl;
union {
u32 rtsblim;
u32 rttotsam;
};
u32 rtfreqmin;
union {
u32 rtfreqmax;
u32 rtfreqcnt;
};
u32 rsvd1[40];
#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
u32 rdsta;
u32 rsvd2[15];
};
typedef struct ccsr_sec {
u32 res0;
u32 mcfgr;
u8 res1[0x4];
u32 scfgr;
struct {
u32 ms;
u32 ls;
} jrliodnr[4];
u8 res2[0x2c];
u32 jrstartr;
struct {
u32 ms;
u32 ls;
} rticliodnr[4];
u8 res3[0x1c];
u32 decorr;
struct {
u32 ms;
u32 ls;
} decoliodnr[8];
u8 res4[0x40];
u32 dar;
u32 drr;
u8 res5[0x4d8];
struct rng4tst rng;
u8 res11[0x8a0];
u32 crnr_ms;
u32 crnr_ls;
u32 ctpr_ms;
u32 ctpr_ls;
u8 res6[0x10];
u32 far_ms;
u32 far_ls;
u32 falr;
u32 fadr;
u8 res7[0x4];
u32 csta;
u8 res8[0x8];
u32 rvid;
u32 ccbvid;
u32 chavid_ms;
u32 chavid_ls;
u32 chanum_ms;
u32 chanum_ls;
u32 secvid_ms;
u32 secvid_ls;
u8 res9[0x6020];
u32 qilcr_ms;
u32 qilcr_ls;
u8 res10[0x8fd8];
} ccsr_sec_t;
#define SEC_CTPR_MS_AXI_LIODN 0x08000000
#define SEC_CTPR_MS_QI 0x02000000
#define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
#define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
#define SEC_RVID_MA 0x0f000000
#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
#define SEC_CHANUM_MS_JRNUM_SHIFT 28
#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
#define SEC_CHANUM_MS_DECONUM_SHIFT 24
#define SEC_SECVID_MS_IPID_MASK 0xffff0000
#define SEC_SECVID_MS_IPID_SHIFT 16
#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
#define SEC_SECVID_MS_MAJ_REV_SHIFT 8
#define SEC_CCBVID_ERA_MASK 0xff000000
#define SEC_CCBVID_ERA_SHIFT 24
#define SEC_SCFGR_RDBENABLE 0x00000400
#define SEC_SCFGR_VIRT_EN 0x00008000
#define SEC_CHAVID_LS_RNG_SHIFT 16
#define SEC_CHAVID_RNG_LS_MASK 0x000f0000
#define CONFIG_JRSTARTR_JR0 0x00000001
struct jr_regs {
#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
u32 irba_l;
u32 irba_h;
#else
u32 irba_h;
u32 irba_l;
#endif
u32 rsvd1;
u32 irs;
u32 rsvd2;
u32 irsa;
u32 rsvd3;
u32 irja;
#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
u32 orba_l;
u32 orba_h;
#else
u32 orba_h;
u32 orba_l;
#endif
u32 rsvd4;
u32 ors;
u32 rsvd5;
u32 orjr;
u32 rsvd6;
u32 orsf;
u32 rsvd7;
u32 jrsta;
u32 rsvd8;
u32 jrint;
u32 jrcfg0;
u32 jrcfg1;
u32 rsvd9;
u32 irri;
u32 rsvd10;
u32 orwi;
u32 rsvd11;
u32 jrcr;
};
struct sg_entry {
#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6)
uint32_t addr_lo;
uint16_t addr_hi;
uint16_t reserved_zero;
#else
uint16_t reserved_zero;
uint16_t addr_hi;
uint32_t addr_lo;
#endif
uint32_t len_flag;
#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
#define SG_ENTRY_EXTENSION_BIT 0x80000000
#define SG_ENTRY_FINAL_BIT 0x40000000
uint32_t bpid_offset;
#define SG_ENTRY_BPID_MASK 0x00FF0000
#define SG_ENTRY_BPID_SHIFT 16
#define SG_ENTRY_OFFSET_MASK 0x00001FFF
#define SG_ENTRY_OFFSET_SHIFT 0
};
#ifdef CONFIG_MX6
#define SMCSJR_PO (3 << 6)
#define SMCSJR_AERR (3 << 12)
#define CAAM_SMPO_0 CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC
#define CAAM_SMCJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10f4
#define CAAM_SMCSJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10fc
#define CAAM_SMAPJR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16)
#define CAAM_SMAG2JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16)
#define CAAM_SMAG1JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16)
#define CMD_PAGE_ALLOC 0x1
#define CMD_PAGE_DEALLOC 0x2
#define CMD_PART_DEALLOC 0x3
#define CMD_INQUIRY 0x5
#define CMD_COMPLETE (3 << 14)
#define PAGE_AVAILABLE 0
#define PAGE_OWNED (3 << 6)
#define PAGE(x) (x << 16)
#define PARTITION(x) (x << 8)
#define PARTITION_OWNER(x) (0x3 << (x*2))
#define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
#define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
#define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
#define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
#define JR_MID 2 /* Matches ROM configuration */
#define KS_G1 (1 << JR_MID) /* CAAM only */
#define PERM 0x0000B008 /* Clear on release, lock SMAP
* lock SMAG group 1 Blob */
#define BLOB_SIZE(x) (x + 32 + 16) /* Blob buffer size */
#define WRP_HDR_SIZE 0x08
#define HDR_TAG 0x81
#define HDR_PAR 0x41
#define HAB_MOD 0x66
#define HAB_ALG 0x55
#define HAB_FLG 0x00
#define PARTITION_1 1
#define PAGE_1 1
#define ERROR_IN_PAGE_ALLOC 1
#define ECONSTRJDESC -1
#endif
int sec_init(void);
int blob_dek(const u8 *src, u8 *dst, u8 len);
#endif
#endif /* __FSL_SEC_H */
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