Blame view

kernel/linux-imx6_3.14.28/arch/blackfin/lib/outs.S 1.35 KB
6b13f685e   김민수   BSP 최초 추가
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
  /*
   * Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
   *
   * Copyright 2005-2009 Analog Devices Inc.
   *                2005 BuyWays BV
   *                      Bas Vermeulen <bas@buyways.nl>
   *
   * Licensed under the GPL-2.
   */
  
  #include <linux/linkage.h>
  
  .align 2
  
  ENTRY(_outsl)
  	CC = R2 == 0;
  	IF CC JUMP 1f;
  	P0 = R0;	/* P0 = port */
  	P1 = R1;	/* P1 = address */
  	P2 = R2;	/* P2 = count */
  
  	LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
  .Llong_loop_s: R0 = [P1++];
  .Llong_loop_e: [P0] = R0;
  1:	RTS;
  ENDPROC(_outsl)
  
  ENTRY(_outsw)
  	CC = R2 == 0;
  	IF CC JUMP 1f;
  	P0 = R0;	/* P0 = port */
  	P1 = R1;	/* P1 = address */
  	P2 = R2;	/* P2 = count */
  
  	LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
  .Lword_loop_s: R0 = W[P1++];
  .Lword_loop_e: W[P0] = R0;
  1:	RTS;
  ENDPROC(_outsw)
  
  ENTRY(_outsb)
  	CC = R2 == 0;
  	IF CC JUMP 1f;
  	P0 = R0;	/* P0 = port */
  	P1 = R1;	/* P1 = address */
  	P2 = R2;	/* P2 = count */
  
  	LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
  .Lbyte_loop_s: R0 = B[P1++];
  .Lbyte_loop_e: B[P0] = R0;
  1:	RTS;
  ENDPROC(_outsb)
  
  ENTRY(_outsw_8)
  	CC = R2 == 0;
  	IF CC JUMP 1f;
  	P0 = R0;	/* P0 = port */
  	P1 = R1;	/* P1 = address */
  	P2 = R2;	/* P2 = count */
  
  	LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
  .Lword8_loop_s: R1 = B[P1++];
  		R0 = B[P1++];
  		R0 = R0 << 8;
  		R0 = R0 + R1;
  .Lword8_loop_e: W[P0] = R0;
  1:	RTS;
  ENDPROC(_outsw_8)