Blame view

kernel/linux-imx6_3.14.28/Documentation/arm/nwfpe/README.FPE 6.02 KB
6b13f685e   김민수   BSP 최초 추가
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
  The following describes the current state of the NetWinder's floating point
  emulator.
  
  In the following nomenclature is used to describe the floating point
  instructions.  It follows the conventions in the ARM manual.
  
  <S|D|E> = <single|double|extended>, no default
  {P|M|Z} = {round to +infinity,round to -infinity,round to zero},
            default = round to nearest
  
  Note: items enclosed in {} are optional.
  
  Floating Point Coprocessor Data Transfer Instructions (CPDT)
  ------------------------------------------------------------
  
  LDF/STF - load and store floating
  
  <LDF|STF>{cond}<S|D|E> Fd, Rn
  <LDF|STF>{cond}<S|D|E> Fd, [Rn, #<expression>]{!}
  <LDF|STF>{cond}<S|D|E> Fd, [Rn], #<expression>
  
  These instructions are fully implemented.
  
  LFM/SFM - load and store multiple floating
  
  Form 1 syntax:
  <LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn]
  <LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn, #<expression>]{!}
  <LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn], #<expression>
  
  Form 2 syntax:
  <LFM|SFM>{cond}<FD,EA> Fd, <count>, [Rn]{!}
  
  These instructions are fully implemented.  They store/load three words
  for each floating point register into the memory location given in the 
  instruction.  The format in memory is unlikely to be compatible with
  other implementations, in particular the actual hardware.  Specific
  mention of this is made in the ARM manuals.  
  
  Floating Point Coprocessor Register Transfer Instructions (CPRT)
  ----------------------------------------------------------------
  
  Conversions, read/write status/control register instructions
  
  FLT{cond}<S,D,E>{P,M,Z} Fn, Rd          Convert integer to floating point
  FIX{cond}{P,M,Z} Rd, Fn                 Convert floating point to integer
  WFS{cond} Rd                            Write floating point status register
  RFS{cond} Rd                            Read floating point status register
  WFC{cond} Rd                            Write floating point control register
  RFC{cond} Rd                            Read floating point control register
  
  FLT/FIX are fully implemented.
  
  RFS/WFS are fully implemented.
  
  RFC/WFC are fully implemented.  RFC/WFC are supervisor only instructions, and
  presently check the CPU mode, and do an invalid instruction trap if not called
  from supervisor mode.
  
  Compare instructions
  
  CMF{cond} Fn, Fm        Compare floating
  CMFE{cond} Fn, Fm       Compare floating with exception
  CNF{cond} Fn, Fm        Compare negated floating
  CNFE{cond} Fn, Fm       Compare negated floating with exception
  
  These are fully implemented.
  
  Floating Point Coprocessor Data Instructions (CPDT)
  ---------------------------------------------------
  
  Dyadic operations:
  
  ADF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - add
  SUF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - subtract
  RSF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse subtract
  MUF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - multiply
  DVF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - divide
  RDV{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse divide
  
  These are fully implemented.
  
  FML{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast multiply
  FDV{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast divide
  FRD{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast reverse divide
  
  These are fully implemented as well.  They use the same algorithm as the
  non-fast versions.  Hence, in this implementation their performance is
  equivalent to the MUF/DVF/RDV instructions.  This is acceptable according
  to the ARM manual.  The manual notes these are defined only for single
  operands, on the actual FPA11 hardware they do not work for double or
  extended precision operands.  The emulator currently does not check
  the requested permissions conditions, and performs the requested operation.
  
  RMF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - IEEE remainder
  
  This is fully implemented.
  
  Monadic operations:
  
  MVF{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - move
  MNF{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - move negated
  
  These are fully implemented.
  
  ABS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - absolute value
  SQT{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - square root
  RND{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - round
  
  These are fully implemented.
  
  URD{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - unnormalized round
  NRM{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - normalize
  
  These are implemented.  URD is implemented using the same code as the RND
  instruction.  Since URD cannot return a unnormalized number, NRM becomes
  a NOP.
  
  Library calls:
  
  POW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - power
  RPW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse power
  POL{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - polar angle (arctan2)
  
  LOG{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base 10
  LGN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base e 
  EXP{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - exponent
  SIN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - sine
  COS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - cosine
  TAN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - tangent
  ASN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arcsine
  ACS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arccosine
  ATN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arctangent
  
  These are not implemented.  They are not currently issued by the compiler,
  and are handled by routines in libc.  These are not implemented by the FPA11
  hardware, but are handled by the floating point support code.  They should 
  be implemented in future versions.
  
  Signalling:
  
  Signals are implemented.  However current ELF kernels produced by Rebel.com
  have a bug in them that prevents the module from generating a SIGFPE.  This
  is caused by a failure to alias fp_current to the kernel variable
  current_set[0] correctly.
  
  The kernel provided with this distribution (vmlinux-nwfpe-0.93) contains
  a fix for this problem and also incorporates the current version of the
  emulator directly.  It is possible to run with no floating point module
  loaded with this kernel.  It is provided as a demonstration of the 
  technology and for those who want to do floating point work that depends
  on signals.  It is not strictly necessary to use the module.
  
  A module (either the one provided by Russell King, or the one in this 
  distribution) can be loaded to replace the functionality of the emulator
  built into the kernel.